An efficient paxallel ransparent BIST method for ...

An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers D. C. Huang , W. B. Jone and S. Et Das* Department of CS & IE, National Chung-Cheng University, Taiwan, R . 0 . C Department of EE, University of Ottawa, Ottawa, Ontario, CA K l K 6N5'

AbstractIn this paper, we propose a new transparent built-in self-test ( TBIST ) method t o test multiple embedded memory arrays with various sizes i n parallel. First, a new transparent test interface is designed t o perform testing i n the normal mode and t o cope with nested interrupts in a realtime manner. The circular scan test interface facilitates the processes of both test pattern generation and signature analysis. B y tolerating redundant read/write/shzft operations, we develop a new march algorithm called TRSMarch t o achieve the goals of low hardware overhead, short test time, and high fault coverage. Index Words: Memory Test, Serial Interfacing technique, h n s p a r e n t Test, Interrupt

I. INTRODUCTIOK

background data are various. However, the predication phase will increase the test time. Regarding to the signature predication, [7] proposed a symmetric method to eliminate the signature predication phase. This method adopt a reciprocal LFSR and reversed order data to obtain a predicable signature, and this will increase hardware overhead. Most of these methods do not deal with testing multiple memory buffers in parallel. Further, we still need to provide a method to deal with the interrupt event while performing test and this is very important for most real-time application. Therefore, we propose a new transparent BIST to resolve these problems.

Due to the improvement of VLSI technology, most systems can be condensed into a chip. The problem of observability and controllability are becoming serious in the embedded system. The observation of the test response is becoming difficult via the tester such that the BIST ( Built-in self-test ) technology is more important now. Traditionally, the memory BIST will destroy the data of memory after testing. Thus, for many applications, the normal operation can not be continued because data are changed. Further, if the BIST can be used many times and performed periodically without destroying the content of memory, then the BIST will become more attractive.

In traditional method, one critical issue is that how to verify the test response for transparent BIST. There are several papers have discussed this [5)[6]. Most of these paper need some additional test time to verify. Recently, V. N. Yarmolik et. al. propose a systematic method to reduce the test time and hardware overhead [7]. Nevertheless, it requires some reciprocal LFSR and reversing order data. In our method, the signature prediction is implied in the test procedure and without a reciprocal LFSR. There are no test time increased, very few hardware (i.e., one converter and one multiplexer) and no fault coverage loss in our approach.

In order to resolve the problem, a new concept of BIST, called transparent BIST ( TBIST ), was proposed by B. Koeneman in 1986 [l].A XOR test pattern has been introduced to keep the initial value after testing. But, this method only can be used for the linear compactor. Based on the transparent BIST, the memory content will be recovered to its original form after testing, such that the normal operation can be continued. In 121, a transparent BIST has been proposed for bitoriented or word-oriented memory. A coupling fault has been detected by (31 and this method use a Nicolaids' transformation. Moreover, (41 propose the method for a synthesizable transparent BIST and detect a patternsensitive fault. The technique to transform any RAM test algorithm to a transparent BIST is provided by [5][6]. In [5], a new signature predication concept was proposed to verify the correctness of memory because the

BIST method that is able to concurrently test many

In this paper, we develop an efficient transparent RAM buffers with different sizes. A new march testing method, called TRSMarch, has been investigated to enable all RAM buffers that share the same BIST controller. The basic idea of TRSmarch is to use a background data to generate the test pattern and adopt a circular shifter to test multiple memory buffers in parallel.

11.

The multiple input shift register (MISR) is a popular scheme to compress the multiple streams in a parallel manner. This scheme is commonly used in Built-In SelfTest and provides the higher test quality. However, the information loss during the compaction is still existing. Fortunately, the alias probability is proportional to the inverted length of MISR. In our research, evaluating the correctness of multiple bit streams from memory can be easily dealt with by the MISR.

This research was supported in part by the Satural Sciences and Engineering Research Council of Canada under Grant A 4750

379 0-7695-083I -6/00 $10.00 02000 IEEE

BACKCROUSD

The major component of a small buffer is the memory cell array which is generally implemented using SRAM. Thus, an appropriate memory cell array fault model must be used to deal with SRAM fault models[9]. To consider the test budget, the fault model we consider can not be too complicated. Thus, only stuck-at faults, transition faults, coupling faults, and sequential faults are considered as many commercial tools do. Neighborhood pattern sensitive faults are not considered because of the complexity and vast number of ways in which the fault can occur. Here, we will focus on the testing of memory cell. Hence we will discuss the testing of SAF,TF and CF in the following sections. Next we will give some detail explanations about these memory fault models. 1. Stuck-at fault (SAF): The logic value of a memory cell is always stuck-at 1 (SA1) or 0 (SAO). 2. Transition Fault (TF): A cell fails to undergo a 0+1 transition (TF 0-1) and/or a 1+0 transition (TF l+O). 3. Coupling Fault (CF): In this case, a write operation in one cell i can influence the value of another cell j, and cell i is called the coupling cell whereas cell j is called the coupled cell. As in [9], three types of coupling faults are considered below: State coupling fault (CFst): A coupled cell is forced to a certain value x if the coupling cell is in a given state Y.

Indempotent coupling fault (CFid): A 0-1 and/or 1-0 transition in the coupling cell forces a certain value in the coupled cell. Inversion coupling fault (CFin): A O + l and/or 1-0 transition in the coupling cell inverts the content of the coupled cell. 111. A NEW TRASSPAREXT TESTISTERFACE Although the serial interfacing technique is very powerful for manufacturing testing, it is difficult to be a p plied in the domain of transparent testing. The basic requirements for transparent BIST are: (1) The test process cannot destroy the memory contents, when it is finished or interrupted; (2) The test process must switch to the normal execution mode within a very short time, when an interrupt occurs; (3) The test coverage must be high enough to justify the extra hardware added; (4) The test time must be short enough to prevent the test process from being excessively interfered by interrupts; ( 5 ) The hardware overhead must be as small as possible to justify the implementation cost. Obviously, the requirements for transparent BIST are more restrictive than those of traditional memory BIST for manufacturing testing. It can also be found that traditional serial interfacing techniques cannot meet the basic requirements for transparent BIST of memory arrays.

b

+YSR

Rr

Fig. 1. Transparent memory interface.

To deal with the difficulties of implementing an efficient transparent BIST technique, we propose a new test interface that is able to meet all the basic requirements mentioned above. Based on the memory contents left by normal operations, the test interface can read each word and then shift the entire word bit by bit for testing. The test interface can also generate new test patterns based on the current memory contents to detect the majority of memory faults. Further, the test interface is able to support test rc:sponse evaluation effectively. As shown in Figure 1, the proposed test interface is designed by adding several more multiplexers to the original input/output port of the memory array under test. It mainly implements the functions of circular chain shifting, test pattern generation, and signature analysis support. The circular chain is used to test multiple memory arrays with various sizes in parallel. Based on this scheme, each word of a memory array can be latched and scanned along the circular chain as shown in Figure 1. Note that in conventional serial interfacing techniques, during scan testing, the scan chain content will be written into the memory array and then read hack to the scan chain for each bit shifting [8] [lo]. On the contrary, the proposed test interface keeps shifting the entire scan chain for test evaluation (without writin,: back the scan chain content), once a word has been read. Since all memory arrays are tested in parallel, the number of bit shifts for each memory read operation equals the maximum word width of all memory arrays. 'Thus, for memory arrays with small word widths, the word content latched in each circular scan chain might circulate several times. As will be shown later, this test concept will greatly ease the signature analysis for test responses. In summary, the advantages of this circular scan chain scheme are: (1) No memory access will be involved once a word has been latched for scan testing, and this greatly accelerates the test speed; (2) The minimum level of memory array in-

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MISR

Fig. 3. The TRSMarch algorithm.

Fig. 2 . A transparent BlST system scheme

volvement during testing enables the transparent BIST process to be switched to normal execution mode in a very short time; (3) The circular test architecture allows memory arrays with different word sizes to be tested in parallel. In conventional memory BIST methods, generally, new test patterns are generated by the test controller and routed t o each memory array either in serial or in parallel. However, for transparent BIST, it is preferred to have the test interface generate test patterns locally to avoid test data routing from test controller to each memory array. In the proposed test interface, test patterns are generated by alternatively selecting Q or /& as an input to each memory cell as shown in Figure 1,so the transition of Q-/& and /&-Q will be exercised in each memory cell. Thus, based on the memory content left by normal operations, new test patterns are generated by complementing each memory word several times. Unlike manufacturing testing, test patterns used by transparent BIST are not known until the test process is started. Thus, it is impossible to calculate digital signatures and store the golden values on the chip for test response analysis. The best solution to this problem is to design a digital signature analysis method that does not need to determine the signature golden values beforehand. Fortunately, our test interface can achieve this goal by just adding an inverter to the circular scan chain, so that the MISR can receive inputs with or without complementing the data scanned out as shown in Figure 1. The basic idea is to read all memory words and compress their values into digital signature S1 by scanning the word contents (bit by bit for each array) into the MISR. Then, the memory words are complemented by the test interface circuit, and their contents

are read and shifted into the MISR again to generate signature S2. But, this time, test responses are complemented before they are shifted into the MISR. Thus, S1 and S2 should have the same value, if the MISR is seeded the same value for both compressions and the memory words are fault-free. Based on this new test concept, the test response evaluation process can be performed without knowing the test patterns in advance. The relationship between the transparent test interface circuit and other components is illustrated in Figure 2. It can be found that all memory modules and interface circuits receive the same test control signals from the transparent BIST controller, and test responses of all memory arrays are fed into a global MISR. The test responses might be complemented before sending t o the M E R , depending on the march element executed as will be discussed later.

IV. THEPARALLEL TRAMPAREST MARCII ALGORITHN Based on the test interface discussed above, we propose a transparent march algorithm called TRSMarch to test all memory arrays in parallel. As shown in Figure 3, the test algorithm mainly contains six march elements, and no test patterns are required for memory array initialization. To simplify the test circuit, redundant test patterns are tolerated for small memory arrays without hurting the fault coverage as in (81. The test algorithm does not need to use a finite-state machine to generate the test patterns, since all test patterns are converted from the memory contents left by normal operations. In the following discussions, each march element of TRSMarch will be discussed in detail. However: unlike RSMarch in [8],TRSMarch does not allow the vertical redundant operations, and the reason will be thoroughly described. As shown in Figure 3: each march element includes read/shift data operations and test pattern write operations. It can be found that the read operation is r e p

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bits for each word in memory array A will be shifted into the MISR for test data compression. Thepormal and extra bits shifted are represented by ~ ( / , a ; ) ~and s(/a,)'-'' respectively, where c represents the largest word width of all memory arrays, and c' represents the word width of the memory module considered.

Fig. 4. Horizontal redundant shift operation.

resented by r(ai), shift operation is represented by s(ai), while write operation is represented by w(ai). Note that (ai) denotes the word i in a memory array. In M1, M2, M4 and M5, each march element contains two scans of entire memory array. In Figure 3, sub-march element scan1 is used t o generate the digital signature of the memory array, while sub-march element scan2 is used to generate new test patterns by reversing each word content. The read/shift operations are used to verify the correctness of each memory bit operation, and they will not change the memory contents. For each memory array, given an address, one memory word will be read into the circular scan chain and then the word bits are successively shifted out for signature analysis (without destroying the memory contents). Thus, once a memory word has been read, the shift operations are continued until all bits in the scan chain have been shifted out a t least once. Note that the operations are executed a t all memory arrays concurrently, and the memory array with the largest word width determines the number of bit shifts (for simplifying the test controller). It can be noticed that memory arrays with smaller word widths will have redundant test data shifted into the MISR for test compression. The reason for allowing redundant test data is to simplify the test circuits in that all memory arrays can receive the same test control signal for read/shift operations. Fortunately, these excessive shift operations do not have any influence on the memory contents, and the redundant test outputs can be easily handled by the MISR without damaging the test coverage. The beauty of the circular scan chain technique is that it allows all memory modules to be tested concurrently, regardless of their different widths. Especially, digital signature analysis can be easily accomplished for arrays with smaller widths by circulating extra bits into the MISR deterministically. For the example in Figure 4, each word contains 4 (6) bits in memory array A (B) and march element M1 is executed. Since memory array B has word width equal 6, the number of shift operations is determined 6. Thus, two extra

Test response evaluation is one or the most critical issues in transparent BIST and it has been well solved in this work. The major problem of test evaluation for transparent BIST is how to determine the digital signatures without knowing test patterns applied. This problem is unique in transparent RIST since, unlike the manufacturing testing, no test patterns are generated during testing. As discussed above, our test interface can achieve this goal by just adding an inverter to the circular scan chain, so that the MISR can receive inputs with or without complementing the data scanned out as shown in Figure 1. Depending on the march element. if the memory contents have been Complemented. then the test responses must be inverted bcDfore they are sending t o M E R . For the example in Figure 5, suppose the output response from the scan chain is "001000 (i.e.. a,) in march element M1. According to TRSMarch, the test response for the same word by inarch element M2 is "110111" (i.e. /ae) because data in the memory word has been complemented. Thus, if the word does not p r e duce erroneous test data, the signature of M1 must be the same as that of M2 ( since the test data for M2 has been complemented by an inverter before shifting to the MISR). By comparing both signatures, errorneous test responses can be observed. Here, we notice that M1. M2. and M3 (M4, M5, and M6) must have the same memory addressing order. Consequently, test output data from M1 to M6 can be verified by comparing each pair of the signatures produced by M1 and M2, M2 and M3, M4 and M5 , and M5 and M6, accordingly. In RSMarch, besides horizontal redundant operations. vertical redundant operations are allowed for memory arrays with smaller word numbers to simplify the test control design (81. But, vertical redundant operations must be avoided in TRSMarch because of the disparity between both march methods. In FLSMarch; the vertical redundant operations do not cliange the memory contents for memory arrays that are excessively tested. Thus, there is no side-effect existent and this good p r o p erty can be used to save the test hardware. However, the w(/ai) operations in TRSMarch will ciiuse trouble if they are excessively applied to shallow memory arrays. Thus. this side-effect makes the test pattern generation process extremely difficult to control. Fortunately, this problem can be easily solved by terminating the march operations temporarily, every time when i i shallow memory

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Fig. 5. A predicable signature by comparision. MI:

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(drcady bc u d a i c d )

(do not bc uzddslrd)

M4-

Fig. 7. A transparent BIST memory interface to deal with interrupt.

M 2

For example, M1 and M5 will leave the same memory map as shown in Figure 6 where the upper (lower) part of the memory array has been complemented (unchanged). Similarly, march elements M2 and M4 will leave the same memory map, if they are interrupted. To guarantee the proper execution for an ISR, we have enhanced the transparent test interface as shown in Figure 7 where more multiplexers are added. The enhanced test interface is able t o switch control from the test mode to the ISR mode with the memory contents properly manipulated. It will be found that the hardware overhead is very small, and the function mode switching can be done in a very limited number of clock cycles.

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.v5

Fig. 6 . Data format in the memory vs. march operation

array has been completely scanned by a specific march element. Thus, the testing of shallow arrays will be terminated until the deepest memory array finishes the current march element. The terminating circuit can be designed by taking advantage of the selection line of the last word in each shallow memory array.

v.

TRASSPAREST TESTISCA S D ISTERRUPTS

The other special feature of transparent testing is that, unlike manufacturing test, the transparent test process might be interfered by interrupts that can occur at any time. Since the memory contents have been changed during testing, unless they can be recovered immediately, error will occur when the interrupt service routine (ER) is executed. Of course; it is possible to solve this problem by terminating the test process and executing a set of special march operations for memory recovery. However, execution of the recovering march operations is generally quite time-consuming, and prevents the ISR from being executed in a real-time manner. Even worse, the nested interrupts might occur, and this makes the problem even more difficult to be handled. Here, we have found that data map left in the memory array is highly related to the kind of march operations.

In Figure 7, two more multiplexers and one inverter (shaded) are added to each 1/0 register t o select a proper path for different march operations. The selection of control signal "data , /data" is dependent on whether M1/M5 or M2/M4 is being executed. For example, if an interrupt occurs when M1 or M5 is executed and part of memory contents have been changed, then the control signal will be switched to "/data" ("data") for each memory access occurring at the upper (lower) part of the memory array shown in Figure 6. The discussions can be extended to other march elements. Thus, the ISR can be executed without concerning any change in memory contents. Based on this scheme, we can read/write a correct data from/to each memory array by selecting a proper data path. Further, this test strategy also allow nested interrupts since each memory array still can be accessed with the same path selection circuit. This method also guarantees that the switch activity can be finished in a very limited number of clock cycles. That is, we do not require a significant amount of time to restore the memory data, and this enables the scheme to satisfy real-time applications. Once a transparent BIST process has been interrupted, the process cannot be resumed by continuing from the interrupted operation. The reason comes from

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(M2 or M4) must be reorganized stairting from the break point in a decreasing (an increasing) address order.

I

I

VI. COSCLUSIOSS

I-&

Fig. 8. Interrupt during memory reorganization

the fact that the ISR might change the memory contents, and this will cause signature mismatch even for fault-free memory array. That is, killing error might occur if the transparent B E T is resumed from the interrupted operation. Thus, the entire transparent BIST process which has just been interrupted must be abandoned. Every time when an ISR execution is completed, the memory contents must be reorganized, provided that a transparent BIST process has been interrupted and it has reversed some memory contents. The reorganization process can be easily accomplished by reversing the complemented part of the array back to uncompleted values based on current memory contents. Note that the memory reorganization process also depends on the march element that was interrupted. For example, suppose a transparent BIST is executing MI or M5 and then it is interrupted with the memory map shown in Figure 6. After the ISR has been completed, the memory map might have been modified by the ISR by writing complemented (upper memory map) or uncompleted (lower memory map) data. The reorganization process does nothing but reverse the complemented memory map back to the uncompleted values. After this, another round of the transparent BIST process can be initiated. The new test strategy is so powerful that it also can handle interrupt that occurs during the memory reorganization process. As shown in Figure 8(a), an interrupt occurs when the transparent BIST process is performing the M l march element, and the upper part of the memory array (area A) has been changed (address x is the breaking point). Now; assume that the ISR execution has been finished, and the memory reorganization process is being performed. Further, suppose another interrupt occurs when the reorganization process moves to word y shown in Figure 8(b). It can be found that the test scheme still handle this case well by inverting all memory accesses occurring in area A’. We emphasize that the memory reorganization process must be done in a correct marching order to avoid any memory fragmentation. For example, the memory map left by M1 or M5

In this paper, we have proposed an efficient transparent BIST method to concurrently test multiple memory arrays that are spatially distributed on the entire chip. To achieve this goal, a transparent test interface is developed to implement the functions of test pattern generation and test response evaluation. The interface is in fact composed of a circular scan chain and several multiplexers, and has the advantage of low hardware overhead. Test responses are evaluated by a single global MISR and this further reduces the hardware overhead significantly. We have also developed a very powerful signature analysis method t o eliminate the tedious signature prediction process with almost no hard”are cost. Based on the memory background data, an efficient march algorithm, TRSMarch, has also been developed t o generate test patterns and expected test results. The TRSMarch algorithm contains six march elements, and can detect all SAF, TF, and CFst, CFid, CFin occurring in different words. By allowing redundant operations in TRSMarch, all memory arrays receive the same control signals and this greatly reduce the hardware overhead without losing fault coverage. Another very attractive feature of the proposed method is the capability of handing (nested) interrupts in a real-time basis. Again, the purpose is achieved by invested very limited hardware cost.

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Interfacing Technique for Embedded Ilernory Testing”. IEEE Design and Test of Compnler, pages 52-63, April 1990.