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An HDR Pixel With Over 60-dB Dynamic Range Enhancement Using In-Pixel Parametric Amplification Gaurav Musalgaonkar , Neha Priyadarshini, and Mukul Sarkar, Member, IEEE
Abstract — This paper discusses a method to enhance the dynamic range (DR) of a conventional CMOS image sensor in low- and high-light environment using in-pixel parametric amplification. The parametric amplification gives a linear and noiseless gain. The source follower in a conventional 4T pixel is used as a capacitor for charge amplification by varying its capacitance periodically. This reconfiguration helps in signal amplification without affecting the pixel fill factor drastically. The simulation results show that over 60-dB DR extension in the low and high illuminations can be achieved enhancing the total DR of the pixel to 120 dB. Index Terms — 4T pixel, CMOS image sensors (CISs), parametric amplifier, wide dynamic range (DR).
I. I NTRODUCTION
D
IGITAL cameras are being used in various applications, such as security and surveillance systems, medical imaging, satellites, and star tracking. Many applications require the image to have an excellent contrast between the high- and low-exposure areas. This can be achieved by increasing the dynamic range (DR) of the pixel, which is defined as the ratio of the largest nonsaturating output signal level and the smallest detectable output signal level. In the conventional 4T pixel, the image contrast at low-illumination levels is degraded due to a very few photogenerated charge carriers per exposure interval. In very high illumination, the photodiode saturates because of excess charge carriers saturating the output signal level. In applications like automobiles and security, the illumination of a scene can vary by many orders of magnitude and thus requires a DR of over 100 dB. However, commercially available CMOS image sensors (CISs) have a DR range of around 60 dB. To overcome the limitation of the conventional CISs, DR enhancement using logarithmic compression [1], a lateral overflow capacitor [2], and multiple exposures [3] is used.
Manuscript received September 21, 2017; accepted December 3, 2017. Date of publication December 28, 2017; date of current version January 22, 2018. The review of this paper was arranged by Editor A. Lahav. (Corresponding author: Gaurav Musalgaonkar.) The authors are with the Electrical Engineering Department, IIT Delhi, New Delhi 110016, India (e-mail:
[email protected];
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2017.2782735
Linear-logarithmic compression involves linear response in low illumination and a logarithmic response in high illumination. The linear-logarithmic pixel extends the DR by several decades of photocurrents but has a nonlinear response and lower SNR in the low-light region. Lateral overflow capacitors [2] integrate the overflowed charges after the photodiode saturates, increasing the DR. However, use of in-pixel lateral overflow capacitors decreases the fill factor of the pixel. Multiple exposure is an extremely popular DR enhancement technique, since it does not change the conventional architecture of the pixel [3]. In this approach, images are scanned for different exposure times and then combined. However, it requires extra storage elements in the column and a more complex readout circuit. Furthermore, multiple exposure times affect imaging of moving targets, since the motion blur and object locations will be different for objects with a different brightness. The DR enhancement techniques in the pixel are mostly limited to a higher signal range. In the lower signal range, the noise floor of the image sensor limits the DR. The noise floor is a combination of many noise sources within the sensor [4]. To increase the DR in the lower signal range, either the noise floor has to be reduced or the photogenerated charges must be multiplied. Charge multiplication is not compatible with standard CMOS technology. In this paper, a DR enhancement technique in lower as well as higher signal range is proposed using an in-pixel charge amplification using a parametric amplifier. Using a parametric amplifier, the conversion gain on the floating diffusion (FD) node is increased. The increase in the conversion gain in the lowillumination regimes helps to detect two low light level signals by increasing the voltage levels on the FD node above the noise floor. This in turn helps in achieving higher DR. A parametric amplifier consists of a time-varying reactive element, which is a periodic function of time [5]. As the gain depends on the time-varying capacitance, the amplification is inherently noiseless and linear, maintaining the signal-to-noise ratio at the output. In a 4T pixel, the back-biased junction diodes or the source follower (SF) transistor can be used as a variable capacitance for parametric amplification. The SF transistor in the pixel is initially configured as an MOS capacitor, whose capacitance is varied as a function of time
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The source–drain terminal is referred to as control terminal. The switches S1 and S2 are placed in the column; therefore, there are effectively only five transistors in the pixel. After the integration period, TG is closed and the charges from the PPD node are sampled on the FD node or the gate terminal of the SF. The switch SPA is closed, and the SF transistor works as an MOS variable capacitor. The transferred charges on the gate of the SF transistor will induce depletion or inversion charges in the SF substrate depending on the voltage applied on the control terminal. The charges held on the gate of an SF capacitor when the control terminal is connected to VPA1 through S1 are given by Q G1 = VFD1 Cgb1 + (VFD1 −VPA1 )(Cgs1 + Cgd1 ) + VPA1 (Csb1 + Cdb1 )
Fig. 1. (a) Proposed 5T pixel. (b) Timing diagram for the conventional 4T pixel.
giving linear amplification in both low- and high-illumination scenes. After the amplification phase, the MOS capacitor is reconfigured as an SF to be used to transfer the pixel information onto the column for further processing. A 60-dB enhancement in the DR as compared with conventional CIS in low and high illumination is obtained using in-pixel charge amplification. The rest of this paper is organized as follows. Section II describes the pixel structure and in-pixel charge amplification using the SF transistor as a parametric amplifier. Section III presents the pixel operation in low- and high-illumination conditions. Section IV presents the simulation results showing the obtained enhancement of the DR. Section V concludes this paper. II. P IXEL S TRUCTURE A conventional 4T pixel comprises of a pinned photodiode (PPD), a transfer gate (TG), a reset transistor, an SF, and a row select transistor (SEL), as shown in Fig. 1(a). The timing diagram associated with conventional pixel is shown in Fig. 1(b). The incident photons generate electron–hole pairs in the PPD. After the integration period, the charges collected in the PPD are transferred to the FD node. In a conventional pixel, the sampled FD node potential is transferred to the column circuitry through the SF buffer and SEL switch for further processing. In the proposed pixel, an additional transistor SPA is used to short the source and drain terminals of the SF transistor also shown in Fig. 1(a). The SF transistor thus acts as a storage capacitor prior to its use as a buffer for transferring the FD node output to column. The potential on the SF source–drain terminal is controlled using bias voltages VPA1 and VPA2 through switches S1 and S2, respectively.
(1)
where VFD1 is the sampled voltage on the FD node and Cgb1 is the series combination of oxide (Cox ) and depletion (Cdep1 ) capacitances of the SF capacitor. The depletion capacitance is due to the source–drain terminal shorted to VPA1 . Cgs1 and Cgd1 are the gate to source and gate to drain capacitances. Csb1 and Cdb1 are the source–drain and substrate p-n junction capacitances when source–drain is connected to VPA1 . The TG gate is open, after the transfer of charges from PPD to FD node, and thus the stored gate charges on the SF capacitor have no path to leave and will stay on the gate. After the charge balancing, the SF source–drain is disconnected from VPA1 by opening switch S1 and connected to VPA2 by closing switch S2. The change in the source–drain bias voltage correspondingly changes the charges in the substrate balancing the SF gate charges. The SF gate charges will now be equal to Q G2 = VFD2 Cgb2 + (VFD2 −VPA2 )(Cgs2 + Cgd2 ) + VPA2 (Csb2 + Cdb2 )
(2)
where VFD2 is the new gate potential balancing the substrate charges and Cgb2 is the series combination of Cox and Cdep2 . Cdep2 , Cgs2 , Cgd2 , Csb2 , and Cdb2 are the depletion, gate to source, gate to drain, and source–drain p-n junction capacitances when control terminal is connected to VPA2 . Since the gate of the SF capacitor is floating, the charges in (1) and (2) must be the same (3) Q G1 = Q G2 VFD1 Cgb1 + (VFD1 −VPA1 )(Cgs1 + Cgd1 ) + VPA1 (Csb1 + Cdb1) = VFD2 Cgb2 + (VFD2 −VPA2 )(Cgs2 + Cgd2) + VPA2 (Csb2 + Cdb2 )
(4)
solving for VFD2 (FD node output) in terms of VFD1 (sampled input) VFD2 VFD1 (Cgb1 + Cgs1 + Cgd1 ) (VPA1 −VPA2 )(Cgs2 + Cgd2 ) = − Cgb2 + Cgs2 + Cgd2 Cgb2 + Cgs2 + Cgd2 VPA2 (Csb2 + Cdb2 )−VPA1 (Csb1 + Cdb1 ) − (5) Cgb2 + Cgs2 + Cgd2 or (6), as shown at the bottom of the next page. The first term in (6) relates the VFD2 to VFD1 through the SF capacitances. The change in the SF capacitance changes
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the conversion gain. As the source–drain bias voltage changes from VPA1 to VPA2 , the change in the SF capacitance for different inputs displays a nonlinear behavior. The SF capacitance is a function of gate to body Cgb , junction capacitances Csb and Cdb , and overlap capacitances Cgs and Cgd . The junction capacitances (7) are source–drain bias-dependent and are nonlinear in nature [6] V −m j (7) C j = ac j o 1 + ψo where A is the area of the p-n junction. ψo and V are the builtin potential and applied bias voltage across source–drain and substrate p-n junction, respectively. m j is a process-dependent junction grading coefficient and its value lies in between 0.33 and 0.5. C j o is the zero bias junction capacitance per unit area. The number of depletion charges in the silicon balancing the gate charges shows a linear relation with gate potential, as shown in the following [6]: VGate
Q 2dep −Q dep = + Cox 2q Na
(8)
where q is the electronic charge, Na is the acceptor doping concentration of nMOS SF, and is the permittivity of the bulk material. The second term of (6) shows how VFD2 depends upon VPA1 and VPA2 . Due to the nonlinear nature of the capacitances, an input-dependent term is subtracted from the first term in (6). Thus, by choosing appropriate VPA1 and VPA2 , the detection range of FD node potential can be increased for low as well as high illuminations. III. P IXEL O PERATION In this section, the proposed pixel operation for low and high illumination is discussed. The switches S1 and S2 operate differently for different illumination conditions to give a relative differential gain in the pixel.
A. Low-Illumination Conditions In CIS, the DR is determined by the maximum and minimum number of electrons detectable. The minimum number of electrons that can be readout depends on the noise floor. For a typical low-noise image sensor, the noise floor is 2 to 5 e−1 . For low illumination, the number of electron– hole pairs generated is low. If the generated electrons are lower than the read noise floor, then it cannot be detected, decreasing the DR of the pixel. For detecting the generated electrons in low illumination, charge-based amplification described in Section II is used. Fig. 2 shows the timing diagram for the proposed pixel operation in low illumination. The pixel is simulated with a supply voltage (V DD ) of 1.8 V and the reset potential of the FD node is 1.57 V. The source–drain terminal
VFD2 =
Fig. 2. Timing diagram for the proposed 5T pixel in low-illumination conditions.
of the SF is shorted with SPA closed and is connected to VPA1 , which is initially set to 1.8 V. The integrated charges on the FD node induce bulk depletion charges in the channel. The SF capacitor channel is completely depleted, as the high potential VPA1 applied to the drain–source terminal removes the mobile negative inversion charges induced by the sampled gate voltage in the channel. After the charge balancing, the source–drain potential is switched to VPA2 by opening switch S1 and closing switch S2. VPA2 for the simulations is chosen to be 1.4 V, which is lower than VPA1 . The depletion charges in the channel balancing the gate voltage of the SF will reduce, as mobile negative inversion charges will start to appear. The reduction in depletion charges corresponds to reduction in the depletion width when the drain–source terminal is switched from higher to lower potential. The reduction in the depletion width is shown in Fig. 3(a) and (b). The pixel is simulated in Cogenda Genius TCAD [7]. The SF aspect ratio is choose to be 1/0.18 μm. The substrate doping used is 5 × 1016 cm−3 and the Vt implant doping used is 5 × 1018 cm−3 . For control terminal connected to VPA1 = 1.8 V, the depletion width was 54 nm, while for control terminal connected to VPA2 = 1.4 V, the depletion width is 45 nm. This correspondingly changes the depletion capacitance (Cdep1 ); however, Cox remain constant irrespective of the biasing voltage. The SF gate capacitance being proportional to depletion capacitance increases with source–drain bias voltage. The variations in Cgb1 , Cgb2 , and total SF gate capacitance with VPA1 = 1.8 V and varying VPA2 are shown in Fig. 4. Csb and Cdb are junction capacitances [see (7)] and are biasdependent and nonlinear in nature. As the source–drain voltage acts as a reverse bias voltage at the source–drain p-n junction, Csb2 and Cdb2 change with change in VPA2 . However, this change is not significant compared with the change in the depletion capacitance of the SF. Cgs and Cgd do not change much with respect to operating voltages of the SF capacitor.
VFD1 (Cgb1 + Cgs1 + Cgd1 ) Cgb2 + Cgs2 + Cgd2 VPA1 (Cgs1 + Cgd1 + Csb1 + Cdb1 )−VPA2 (Cgs2 + Cgd2 + Csb2 + Cdb2 ) − Cgb2 + Cgs2 + Cgd2
(6)
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Fig. 3. 2-D profile of simulated pixel in low illumination. (a) and (b) Change in depletion width (Xj ) under the gate of an SF capacitor for VPA1 = 1.8 V and VPA2 = 1.4 V, respectively.
Fig. 4. SF capacitance variation for varying VPA2 . The capacitances are corresponding to 1-µW/cm2 illumination level.
The SF capacitor operates in a depletion region and Cgs and Cgd are equal to overlap capacitances. Thus, lowering the source–drain potential from VPA1 = 1.8 V results in Cgb2 > Cgb1 . Equation (6) can now be simplified as VFD2 =
VFD1 (Cgb1 ) −Voffset . Cgb2
(9)
Thus, the first term in (9) gives a reduction in the FD node potential by Cgb1 /Cgb2 . The offset voltage is proportional to the differential bias potential applied to the source–drain of the SF capacitor. For VPA2 = 1.4 V, Cgb2 increased by almost 15% as compared with Cgb1 . This reduces the FD node by the same amount as per (8). Increase in VPA2 reduces the FD node potential. VRST −VFD is the total voltage change at the FD node from its reset potential. A higher change in this voltage is desired to be able to detect the low illumination charges. As VPA2 decreases from 1.5 to 1.2 V, the FD node voltage with respect to reset potential provides a 400-mV window for signal detection. Lowering VPA2 reduces the number of depletion charges in the SF and correspondingly surface potential being proportional to Q 2dep also reduces. Fig. 5 shows the change in the surface potential (the potential drop from the oxide– semiconductor interface to the bulk) of the SF capacitor, for VPA1 = 1.8 V and varying VPA2 . The surface potential is a monotonically increasing function of bulk charges [6]. For lower illuminations, FD node potential is close to its reset level, which corresponds to more depletion charge in the SF capacitor and thus large surface potential. As the illumination increases, FD node potential reduces from its reset level and the surface potential also reduces. The potential drop across the oxide remains unchanged. Thus, by controlling the source– drain bias of the SF capacitor surface potential, the FD node potential decreases. Hence, overall change (VRST − VFD ) for signal detection at FD node increases for low illumination, as shown in Fig. 5. The buried channel SF (BSF) in image sensors is commonly used to lower the noise level in the pixel. The parametric amplification in BSF is shown in Fig. 6. The buried channel width and doping are chosen to be 35 nm and 1017 cm−3 , respectively. In the BSF, channel is formed below the surface; this additional separation between the gate and the channel
Fig. 5. Surface potential of an SF capacitor and FD node potential variation from its reset level for varying VPA2 when VPA1 is fixed at 1.8 V.
Fig. 6. 2-D profile of simulated n-buried channel showing depletion width variation when VPA2 is varied from 1.8 to 1.4 V.
reduces the effective gate capacitance of the BSF at the FD node. In the BSF, the change in the depletion capacitance is higher as compared with conventional SF because of the lower depletion width [8]. For VPA1 = 1.8 V, depletion width is around 30 nm, while for VPA2 = 1.4 V, it is around 18 nm. Thus, from (9), gain due to Cgb1 /Cgb2 is higher for BSF as compared with conventional SF. This gives larger amplification at the FD node. The parametric amplification process is thus actually better than the surface channel SF. The amplification, however, depends on the doping profile used for BSF and the distance of the buried channel from the surface.
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Fig. 7. Timing diagram for the proposed 5T pixel under high-illumination conditions.
Fig. 8. 2-D profile of simulated pixel in high illumination. (a) and (b) Change in depletion width (Xj ) under the gate of the SF capacitor for VPA1 = 0.7 V and VPA2 = 1.8 V, respectively.
B. High-Illumination Conditions In high illumination, PPD approaches saturation quickly, limiting the DR. The charge amplification used to increase the DR for low illumination can also be used to enhance the detection range for high illumination. Fig. 7 shows the timing diagram for the proposed pixel operation in high illumination. In high illumination, VPA1 is initially set to 0.7 V. After the charge transfer from PPD to FD node, source–drain voltage of an SF capacitor changes to VPA2 = 1.8 V. This is just the reverse operation as performed for low illumination, where bias voltage is changed from a high potential to a lower potential. As VPA1 < VPA2 , the large potential at the source– drain terminal will attract all the mobile inversion charges available beneath the oxide layer. The depletion charges in the SF capacitor increase to balance the gate charges. The increase in the depletion region width for the SF capacitor is shown in Fig. 8. For VPA1 = 0.7 V, the depletion width is 37 nm, while for VPA2 = 1.8 V, the depletion width is 57 nm. The change in the depletion width changes the SF capacitance. The variations in Cgb1 and Cgb2 with VPA1 = 0.7 V and varying VPA2 is shown in Fig. 9. For VPA2 = 1.8 V, Cgb2 reduced by almost 36% as compared with Cgb1 . Increasing the source–drain potential from VPA1 = 0.7 V results in Cgb1 > Cgb2 . Equation (9) thus shows an amplification in the FD node potential by Cgb1 /Cgb2 . Fig. 10 shows the change in the surface potential of the SF capacitor, for varying VPA2
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Fig. 9. SF capacitance variation for varying VPA2 . The capacitances are corresponding to 2000-µW/cm2 illumination level.
Fig. 10. Surface potential of an SF capacitor and FD node potential variation from its reset level for varying VPA2 when VPA1 is fixed at 0.7 V.
in high illuminations. Increasing VPA2 increases the depletion charges and correspondingly increases the surface potential. By varying VPA2 from 1.2 to 1.8 V keeping VPA1 = 0.7 V, the FD node voltage with respect to reset potential provides around 800-mV window for signal detection in high-illumination condition. IV. E NHANCING DYNAMIC R ANGE As discussed in Section I, the DR of a CIS is limited by the ability to detect the minimum and maximum number of electrons in low and high illumination, respectively. In Section II, a charge-based amplification scheme for the integrated charges on the FD node is discussed. The differential potentials VPA1 and VPA2 applied to the source–drain of an SF capacitor in lowand high-illumination regimes help in increasing the overall DR of the image sensor. Fig. 11 shows the FD potential after integration for varying illumination levels for a conventional 4T pixel. The downconversion and upconversion of the FD node voltage during low and high illumination are also shown in the figure. In the conventional pixel, VRST − VFD for low illumination is very low. For light intensities lower than 1 μW/cm2 , the change in FD node potential is very small compared with the reset voltage. After the charge amplification, the change in the FD node voltage from the reset level increases by 350 mV for illumination of 1 μW/cm2 . The transfer curve shown in Fig. 11
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TABLE I C ONVERSION G AIN FOR D IFFERENT VALUES OF VPA2
Fig. 11. FD node potential levels before and after charge amplification. For low-light amplification, VPA1 = 1.8 V and VPA2 = 1.4 V and for high light, VPA1 = 0.7 V and VPA2 = 1.8 V.
Fig. 13. Upconversion of FD node potential with high illumination for varying VPA2 .
Fig. 12. Downconversion of the FD node potential with low illumination for varying VPA2 .
would be continuous as either upconversion or downconversion alone would be used depending on the illumination conditions. In low-illumination environment downconversion and in high-illumination environment upconversion will be used. In case of moderate illumination, the pixel operation will be conventional and no parametric amplification is required. Fig. 12 shows the signal levels after amplification of the FD node charges in low illumination for varying VPA2 . The slope of the FD node potential for varying illumination corresponds to the sensitivity of the change in FD node voltage. The slope is seen to increase for decreasing VPA2 . The slope without the amplification process is 0.022, and is 0.027, 0.036, and 0.042 for VPA2 of 1.6, 1.5, and 1.4 V, respectively. The increase in the slope is due to the nonlinear behavior of the SF capacitance. The second term in (6) reduces the FD node potential in such a way such that the slope for signal detection at the FD node increases for lower illuminations. The increase in the slope of the FD node potential provides a linear signal amplification for the low illumination when parametric amplification is used. In parametric amplification, the minimum number of electrons generated in the photodiode does not change. For detection, the number of electrons transferred from PPD to FD node must be higher than the noise floor of the column readout circuit. Using parametric amplification, the conversion gain on the FD node is changed, as shown
in Table I for varying VPA2 . Without parametric amplification, the two low light levels are difficult to distinguish, and thus conventional 4T pixel has limited DR of 60 dB. The increase in the conversion gain increases the contrast between two illumination levels, enhancing the DR by another 40 dB in low-illumination environment. The parametric amplification thus increases the overall DR to 100 dB under low-light conditions. Lowering source–drain bias voltage VPA2 increases the signal gain as well as slope for signal detection. But VPA2 cannot be decreased below a critical value, since VPA2 later becomes the drain voltage of the nMOS SF transistor when used as a buffer. The SF as a buffer is required to transfer the FD node voltage onto the column for column processing and readout. The drain voltage of the SF should be high enough to maintain the SF in saturation, else the transfer of signal from the pixel to the column is affected. This puts a constraint on the choice of the control terminal voltage. In the simulation, the maximum gain was obtained when control terminal voltage VPA2 was chosen to be 1.4 V and VPA1 was fixed at 1.8 V. For high illumination, a large number of charges are integrated on the FD node, and thus the FD node potential decreases rapidly after 1000 μW/cm2 , as shown in Fig. 13. Thus, in the saturation region, the conventional pixel fails to detect the output beyond 0.4 V, the minimum potential required to keep the SF turned ON. The saturation edge can be extended using the charge amplification process described in Section III-B for high-illumination conditions. Fig. 13 shows the amplified signal levels at FD node under high illumination after charge amplification. It also shows the potential levels of conventional and proposed pixel at FD node with varying VPA2 . The upconversion of the FD node voltage by increasing VPA2
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Fig. 14. Error bar plot of 0.5% variation of VPA2 .
prevents the saturation for high illumination. This enhances the DR in the high light by another 20 dB. In total, the charge amplification process enhances the DR of a conventional pixel by 60 dB in low- and high-illumination conditions. The overall DR of the 4T conventional pixel is thus enhanced to 120 dB. For high illumination, VPA1 is chosen to be 0.7 V, which corresponds to the flat band voltage of the SF MOS capacitor. For VPA1 less than 0.7 V, a dc shift higher than reset level is obtained for VPA2 = 1.8 V. On the other hand, if it is more than 0.7, it is difficult to reach minimum potential at the FD node during transfer to the column. The voltages VPA1 and VPA2 used for parametric amplification are common to all pixels in the imaging array. Any variation in VPA1 and VPA2 varies the FD node parasitic and SF transistor capacitances. The variation in the capacitances changes the conversion gain when parametric amplification is used [9]. The variations in the conversion gain for a 0.5% variation in VPA2 are shown in Fig. 14. For 0.5% variation in VPA2 , the conversion gain varies by 0.62%, 0.67%, and 0.71% for VPA2 equals to 1.4, 1.5, and 1.6 V, respectively. However, for process where large conversion gain is used, for example, in jot-based devices, a standard deviation of 2.1% of the conversion gain has been reported [10], [11]. The variations in VPA1 and VPA2 thus will introduce pixel to pixel FPN. Just like the power supply variation needs to be minimized in conventional pixels, the variations in VPA1 and VPA2 should also be minimized to lower the FPN. After the parametric amplification, the SF transistor is reconfigured as a buffer for transferring the pixel information onto column when SEL is turned ON in Fig. 1(b). The variation in VPA2 changes the surface potential and, thus, the threshold voltage of the SF transistors, as shown in Fig. 15. The changes in the surface potential across SF are nonlinear. The variation in the surface potential is higher for higher VPA2 . However, in low-illumination amplification, the change in bulk–source voltage increases with lowering VPA2 values. Therefore, threshold voltage variation also increases as VPA2 is lowered from 1.8 V. In high illuminations, the change in the bulk–source voltage is higher for higher VPA2 . The surface potential is also a function of illumination or the number of electrons transferred to the FD node. The variations in the threshold voltage introduce gain error in the SF output.
Fig. 15. Surface potential and threshold voltage variations for varying VPA2 . (a) Low illumination. (b) High illumination.
Fig. 16. SF output with SEL switch open.
The potential profile at the output of the SF is shown in Fig. 16. The change in the slopes of the output of the SF in comparison to Fig. 12 is due to the nonlinearities and variations in the conversion gain. The SF gain error with respect to conventional pixel is 1.03%, 1.33%, and 1.65% for VPA2 = 1.6, 1.5, and 1.4 V, respectively. The SF gain error increases with decreasing VPA2 due to increasing threshold voltage variations. The SF gain error would be a dominant contributor to FPN. The FPN can be corrected using dark
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TABLE II C OMPARISON OF C ONVENTIONAL AND PARAMETRIC P IXELS IN THE C ASE OF R ESET F EEDTHROUGH
The variation in VPA2 changes the sampled kTC noise during reset and signal readout. Thus, the SF nonlinearity decreases the sensitivity at the output; however, the sensitivity is still higher compared with conventional 4T pixel. In parametric amplification, the charge amplification on the FD node is done before the charges being converted to a voltage. The amplification is in the charge domain and is thus ideally noiseless, maintaining the signal-to-noise ratio at the output [8]. Although, practically, it is observed that some noise can appear due to the substrate resistance that appears in series with the depletion capacitance, the substrate resistance noise can be made low by placing a guard ring block [12]. Fig. 17. Pixel output noise before and after parametric amplification in the low-illumination regime.
row and column calibration or on-chip double sampling. Furthermore, the conversion gain is more dependent on the junction capacitance at FD node and C G S (due to strong inversion of SF). These capacitances are bias-dependent and thus vary the conversion gain. The use of SF as an MOS capacitor parametric amplifier will increase the capacitive coupling on the FD node. However, when the SF transistor is reconfigured to act like a buffer, the amplification is still observed in the simulations. Increasing VPA1 − VPA2 results in further amplification of VRST − VFD . Photo response nonuniformity can be significant in this case and needs to be calibrated, but the signal charge can be amplified such that it is more than the error by choosing an appropriate VPA2 . In low illumination, CGB of SF increases after parametric amplification. Therefore, the FD capacitance before amplification is lower compared with after amplification. Due to a larger effective capacitance at the FD node, the kTC noise √ is expected to reduce. This reduction is only a few nV/ Hz, as shown in Fig. 17. Thus, this decrease in the noise floor does not affect the DR significantly. The increase in the effective CFD reduces the effect of reset feedthrough, as shown in Table II. The table shows that as VPA2 decreases, CFD increases resulting in lower potential drop on the FD node due to reset feedthrough. Additionally, the input-referred thermal noise is inversely proportional to the conversion gain. As the conversion gain increases in parametric amplification, the thermal noise will decrease. However, the kTC noise, which is canceled in the conventional 4T pixel by correlated double sampling, may not be completely canceled in the proposed structure.
V. C ONCLUSION The DR of commercially available CISs with a 4T pixel is limited to 60 dB due to low sensitivity on the FD node. In this paper, an in-pixel charge amplification using an SF transistor as a parametric amplifier is proposed to increase the DR in low as well as high illumination. The proposed technique reuses the SF for signal amplification, and as a buffer, thus, it does not compromise with the fill factor of the pixel. The time variation of the depletion charges due to the change in source–drain potential of the SF results in a variable depletion capacitance. This leads to an amplification of the sampled photodiode signal at the FD node or the gate of the SF. This amplification makes the overall signal for low and high illuminations detectable. This linear and noiseless amplification using SF as a parametric amplifier results in an over 60 dB increase in the DR of the pixel. The in-pixel charge amplification increased the DR of a convention 4T pixel to 120 dB. R EFERENCES [1] M. Vatteroni, P. Valdastri, A. Sartori, A. Menciassi, and P. Dario, “Linear–logarithmic CMOS pixel with tunable dynamic range,” IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1108–1115, Apr. 2011, doi: 10.1109/TED.2011.2106787. [2] N. Akahane, S. Sugawa, S. Adachi, K. Mori, T. Ishiuchi, and K. Mizobuchi, “A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 851–858, Apr. 2006, doi: 10.1109/JSSC.2006.870753. [3] Z. Gao, S. Yao, C. Yang, and J. Xu, “A dynamic range extension technique for CMOS image sensors with in-pixel dual exposure synthesis,” IEEE Sensors J., vol. 15, no. 6, pp. 3265–3273, Jun. 2015, doi: 10.1109/JSEN.2014.2379942. [4] H. Tian, B. Fowler, and A. El Gamal, “Analysis of temporal noise in CMOS photodiode active pixel sensor,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 92–101, Jan. 2001, doi: 10.1109/4.896233.
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[5] S. Ranganathan and Y. Tsividis, “Discrete-time parametric amplification based on a three-terminal MOS varactor: Analysis and experimental results,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2087–2093, Dec. 2003, doi: 10.1109/JSSC.2003.819162. [6] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor. London, U.K.: Oxford Univ. Press, 2011. [7] Cogenda TCAD Pvt. Ltd. (2008). Genius Semiconductor Device Simulator v1.7.4 Manual. [Online]. Available: http://www.cogenda.com/ downloads/docs/geniusugen.pdf [8] Y. Chen, X. Wang, A. J. Mierop, and A. J. P. Theuwissen, “A CMOS image sensor with in-pixel buried-channel source follower and optimized row selector,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2390–2397, Nov. 2009, doi: 10.1109/TED.2009.2030600. [9] A. Boukhayma, A. Peizerat, and C. Enz, “Temporal readout noise analysis and reduction techniques for low-light CMOS image sensors,” IEEE Trans. Electron Devices, vol. 63, no. 1, pp. 72–78, Jan. 2016, doi: 10.1109/TED.2015.2434799. [10] J. Ma, D. Starkey, A. Rao, K. Odame, and E. R. Fossum, “Characterization of quanta image sensor pump-gate jots with deep sub-electron read noise,” IEEE J. Electron Devices Soc., vol. 3, no. 6, pp. 472–480, Nov. 2015, doi: 10.1109/JEDS.2015.2480767. [11] D. A. Starkey and E. R. Fossum, “Determining conversion gain and read noise using a photon-counting histogram method for deep sub-electron read noise image sensors,” IEEE J. Electron Devices Soc., vol. 4, no. 3, pp. 129–135, May 2016, doi: 10.1109/JEDS.2016.2536719. [12] S. Ardalan and M. Sachdev, “An overview of substrate noise reduction techniques,” in Proc. 5th Int. Symp. Quality Electron. Design, Mar. 2004, pp. 291–296, doi: 10.1109/ISQED.2004.1283688.
Neha Priyadarshini received the M.Tech. degree in VLSI design from Thapar University, Patiala, India, in 2015. She is currently pursuing the Ph.D. degree with the Department of Electrical Engineering, IIT Delhi, New Delhi, India. Her current research interests include the area of analog/ mixed-signal circuit design and CMOS image sensors.
Gaurav Musalgaonkar received the M.Tech. degree in VLSI design from Thapar University, Patiala, India, in 2015. He is currently pursuing the Ph.D. degree with the Department of Electrical Engineering, IIT Delhi, New Delhi, India. His current research interests include microelectronics and nanoelectronics, semiconductor device modeling, and CMOS image sensors.
Mukul Sarkar (M’11) received the Ph.D. degree in electronic instrumentation engineering from the Technical University of Delft, Delft, The Netherlands, in 2011. He is currently an Associate Professor with the Department of Electrical Engineering, IIT Delhi, New Delhi, India. His current research interests include the areas of solid-state imaging, CMOS image sensors, bioinspired vision systems, analog/digital circuit design, and machine vision.
