An Integrated Approach to Retargetable Code Generation - CiteSeerX

An

Integrated

Approach Tom

Wilson,

to

Gary

Retargetable

Grewal,

Ben

VLSI-CAD University Guelph,

Ontario,

Halley,

challenge

Canada

N1G2W1

fied model of the problem,

instruction

compilers

set

of

because

processors

instruction

erful

(ILP)

model.

methodology

for

for

ILP for

modeling

code

on data;

Introduction

1

data

creasingly

Set wide

Processors

use in

of their

inherent

capable

of generating

matically such

compilers

monly

ular

chip

application,

for

which

tion

available

different

chip

We have

developed that

a variety

model

the

teger

linear

grated problems

code chips,

constrained compilers

a difficult to

task

for

mention

poorly

prepared another,

any

The

one

a family

entire

code

program

approach

both

very

purpose (ILP),

quality

problem

which We not

provides only

Most

have

$03.00 @ 1994 IEEE

compilers register

variable

conflicts

in-

example.

Special

signment

techniques

sub-

when

compiling

a uni-

code

generation

might

registers, in

the

purpose code

methods,

a

an address

is

an operand on yet

assignment

such

have focused

process, inspire Most

as [5-8],

stressed on

live

[I-4]

for

heuristic

the major chips.

that

to handle.

schemes

ISP

streams

parallelism

have

on

another.

operand

be able

registers

registers.

which

such

an”d provide for

of

used

and

been

to engender

operation

assignment

We an inte-

the

has

tends

to obtain

being several

from

purpose

as an

separate

among

markedly

general

70 0-81 86-5785-5/94

parallelism

used

operand

in

different

instruction-level

ensemble

style,

cycle,

the

code

architectures.

traditionally

generation.

and a work-

high

ISP

generation

to several

in code

a methodology

friendlier parallelism

on one with

differs

of

a

programming

conventional

can generate

of special

and

have

less

ex-

generating

research

with

be used

memory,

memory,

published

by

are quite

ones may

to data

registers

machines

instruction-level

pipelined

certain

different

relevant

of the toward

genera-

are make

And

to imple-

is surrounded

capabilities

program

Much

The

is often

from

reg-

memory;

er, possibly

writing

of capabilities!

parallelism

hardware

Only for

the from

address

to data

ALU

whose

combinations

oriented

a partic-

architecture,

features

not

(DSP)

specialized.

etc.

preparing

The

of registers

a constant

access

count

branch.

constants

addresses,

com-

itself;

program

operations,

tracting

Furthermore,

enough”

and

ALU

with

for the next

the

number

varied

is often are

this

to retargetable

of data to or from

a register

instruction

a value

a conditional

a small

designs.

ing prototype for

that

chips

approach

movement

loading

updating

for

consequence

optimizing

ISP

but

processing

~tjust

architectural

quality

special

to market,

to optimize

The

or heavily

Awkward

of high

of the

has

function.

an unconventional

ISP

signal

designed

it often

the

dra-

requirements.

is specially

perform

suit ed.

digital

would

of code .

with

ment

available.

quality

real-time

and

because

concurrent

of the

isters

in-

Compilers

chips

time

applications for

attendant

if the to

the

these

generally

is the high

by

finding

versatility.

product’s

are not

employed

with

for

are

products,

and

code

their

One problem demanded

commercial

flexibdity

hasten

(ISPS)

such integrated

memory;

a field Instruction

to important We believe

We have concentrated on ISP chips that are specially designed for DSP applications. The chips in question have a single ALU that can do a multiply and accumulate in a single instruction cycle, Although the instruction repertoire is limited, the instruction words are long, permitting several things to occur in parallel during each cycle. These include: one ALU operation

of ISPS.

a variety

adapted

architecture.

code generation.

a pow-

high-quality

but one which is sufficiently

it can be easily

in the target

is the first

level par-

provides

generating

that

variations

(lSPS)

allelism, small numbers of registers, and highly specialized register capabilities. Many traditionally separate subproblems in code generation have been unified a single integer linear proand jointly optimized within gramming

Banerji

Group

abstract purpose

Dilip

Generation

of Guelph

Abstract Special

Code

as-

bottleneck published

approach

the

problem ally

by solving

employing

extensive

a succession

heuristics.

peephole

unoptimized

of subproblems,

One

approach

optimization

generated

to make

code.

a code

generator

that

lem

at once

to obtain

an integrated

that

thrives

on special

the

In contrast,

have

considers

purpose

as sets of registers

usu-

edges

[9, 10] uses most

we not

the

solution,

gives

but

one

registers.

Code

Generation

which

model registers

instructions important

idea

that

The

2.1 We

Subproblems

begin

generated The

with

a data

by the front

following

that flow

are

graph

Included

(DFG),

which

end of an appropriate

subproblems

must

be handled

is

1. Map

combinations

onto

more

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inclusive

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and

generic

machine

DFG

use

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instructions,

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tions 2. Schedule them

operations

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3. Assign when

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units;

address)

“extra”

alternative

values

to

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into

ber

of registers,

ily

store

values

exceeds

spills

introduce

certain

5. Introduce

of live values

which

to

resolve

registers

and

temporar-

copies

problems

with

the

in memory;

register-to-register

points

the num-

values

with that

at

special around

loops;

are required concerns

Similarly,

across

control

block

generic

registers

boundaries

and

7. Correctly

around

compact

(highly

parallel)

imum 2.2

consistently loops;

the

individual

machine

number

of final

Important

components

instructions

into

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a min-

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ated

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gram.

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tioned of any

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off issues the

reflect model

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realities

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various

spill

result.

terms,

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supports example,

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use at another. at

one

point points useful

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subsume

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overlap

edges

require

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elements

in the

implication some

and

gener-

regions one

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plus

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be adcurrent

reserving

an ad-

the array

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of the

code,

use of the

point

selection using

access

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or by

reference

Similarly,

among

array

its

of access,

at

of in-

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may

Operations,

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groups machine

potentially

(recomputing

point

Within

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71

by

design.

active.

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either

final

as final

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copies

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which

objects.

dressed

menwhose

correctness

all

tional

pro-

inequalities,

ILP,

that

linear

subproblems

the

providing

actual

integer

linear

Since

by

thus

an

of the

specify

solution.

together

on all

terms

effect

“subproblems”, of the

based

model

in

feasible

considered late

we

above

combined

is

other,

generated

in the

DFG

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characteristics

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or register

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