technique is developed which enables the fabrication of RF. MEMS parallel-plate capacitors with a high quality factor and a very compact size. A 2-pole coupled ...
An Integrated Tunable Band-Pass Filter Using MEMS Parallel-Plate Variable Capacitors Implemented with 0.35[tm CMOS Technology S. Fouladi, M. Bakri-Kassem, and R. R. Mansour
University of Waterloo, Waterloo, Ontario, Canada, N2L3G1 the proposed high-Q and compact tuning elements. It demonstrates a fractional tuning range of 17% with a minimum insertion loss of 5.66dB and a return loss better than 20dB.
Abstract This paper presents an integrated tunable bandpass filter with RF MEMS varactors fabricated using the TSMC 0.35,um CMOS process. A maskless post-processing technique is developed which enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5GHz and a 9% relative bandwidth is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS capacitors with a quality factor exceeding 20. The filter has an insertion loss of 5.66dB and occupies a chip area of 1.2 x 2.1 mm2. Index Terms - CMOS, Integrated tunable filters, microelectromechanical devices, RF MEMS, tunable capacitors.
II. FABRICATION PROCESS
A CMOS micromachining process was reported by Fedder et al [3]-[4] to fabricate CMOS-MEMS tunable capacitors. The capacitors were based on interdigitated beam structure, and electro-thermal actuators were used for tuning. Our proposed post-processing technique presented in this section enables the fabrication of parallel-plate tunable capacitors with a higher capacitance value, smaller size and zero dc power consumption using the electrostatic actuation mechanism. The CMOS-MEMS post-processing of tunable capacitors starts with a chip fabricated using the TSMC 0.35tm 2P4M CMOS technology. There are two polysilicon and four metal layers available through this process. The process offers the possibility for the fabrication of MEMS structures using metal interconnect layers. The layout of the tunable parallel-plate capacitor and its cross-sectional view are presented in Fig. 1. The top and bottom plates are made of M3 and MI layers, respectively and the second metal layer (M2) is used as a sacrificial layer which will be removed after postprocessing in order to create an air gap between the plates. By using this approach after release, the total gap between the plates consists of two dielectric layers each having a thickness of 1 vm and a 0.6 m air gap. The dielectric layer prevents the occurrence of a short circuit when the dc tuning voltage
I. INTRODUCTION
There is a need for intelligent reconfigurable RF front-ends that can achieve maximum hardware sharing for various standards. Such an RF front-end requires reconfigurable blocks rather than switched architectures. These reconfigurable blocks need to meet several RF specifications such as smaller size, lower loss, higher tuning range, linearity, and low power consumption. The continuous shrinkage of minimum feature size in current silicon-based technologies such as CMOS provides an opportunity to meet these demands. Moreover, using these technologies, it is possible to integrate the reconfigurable RF blocks with the core signal processing circuitry leading to the implementation of compact intelligent reconfigurable RF front-ends. Tunable filters are among the reconfigurable blocks that if integrated with RF CMOS electronics can reduce the overall system size, weight and cost. A number of integrated tunable filters have been demonstrated using solid-state tuning elements [1]. Despite the small area and high quality factor of these active tuning elements, the major disadvantage is their susceptibility to noise and lower power handling due to nonlinearities in the active semiconductor devices. Using CMOS-MEMS technology it is possible to replace these active components with passive RF MEMS tuning elements possessing superior RF performance in terms of linearity and insertion loss. To our knowledge, very limited work has been reported in literature on silicon-based integrated filters using commercial CMOS technologies [2]. In this paper we present for the first time, a maskless post-processing technique for the realization of parallel-plate tunable CMOS-MEMS capacitors. An integrated tunable bandpass filter is constructed by TSMC 0.355pm CMOS technology and is highly miniaturized using
1-4244-0688-9/07/$20.00 C 2007 IEEE
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Fig. 1. layout and cross-sectional view of the parallel-plate MEMS tuning elements fabricated using the 2P4M 0.35[lm CMOS process.
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exceeds the pull-in voltage, and the top plate snaps down on the bottom plate. Three maskless post-processing steps are required to construct the tunable capacitors. They also include improving RF performance by etching away the silicon under the device and eliminating substrate loss. A schematic view of the postprocessing steps is presented in Fig. 2. The first processing stage involves the removal of silicon dioxide around the MEMS structure as presented in Fig. 2(a). This can be done using the last metal layer (M4) as a mask and reactive ion etching (RIE) of the oxide layer [3]. The main purpose of this step is twofold. First, to expose the sacrificial M2 layer that will be etched during the next post-processing step. Secondly, to create windows through the oxide down to the silicon substrate, which are used to form a trench under the capacitors improving their quality factor and self-resonance frequency. It is important to keep an oxide layer around the structural metal layers (MI and M3) to protect them during the removal of the M2 sacrificial layer. This is accomplished by extending the masking metal layer (M4) on top of the structural layers. However, the second metal layer which is required to be exposed after the RIE step, should be extended further than M4. As shown in the cross-sectional view of the proposed capacitor in Fig. 1, the extension of M4 over MI and M3 is 2km. assuming that the RIE etch recipe is anisotropic, this leaves a 2tm of side-wall oxide to protect the structural metal layers. The M4 layer also covers the CMOS electronics circuitry. Fig. 3(a) presents an SEM image of the capacitor after the first post-processing step. As shown in this figure, M2 and the silicon substrate are exposed and ready to be etched during the next step. The second post-processing step as shown in Fig. 2(b) involves the etching of the sacrificial layer and substrate using wet etching techniques. The sacrificial layer is removed using PAN etch followed by TiW etchant. In addition to the sacrificial layer removal, the exposed M4 layer used as a mask during the RIE step will be removed. For wet etching of
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Fig. 3. SEM image of the capacitor after first (a) and second (b) post-processing steps.
silicon, diluted 5% electronic grade TMAH is used. For an acceptable RF performance, a minimum trench depth of 75km is required. An SEM image of the CMOS-MEMS capacitor after the wet etching step is shown in Fig. 3(b). As shown in this figure, in order to facilitate the etching of the sacrificial metal layer sufficient number of release holes are included on the top plate of the capacitor. During the last post-processing step, devices are rinsed in IPA and released in a critical point dryer (CPD) system to avoid any stiction problems. This is followed by a final RIE step that is required to remove the protecting oxide layer on top of M3 and RF pads as shown in Fig. 2(c). III. FILTER DESIGN
An integrated tunable bandpass filter is designed using the proposed CMOS-MEMS tuning elements. The filter is realized as a 2-pole capacitively loaded interdigital filter with tapped line input and output coupling as shown in Fig. 4. The effective electrical length of each resonator and also the length
It measured from the resonator ground to the tap point can be tuned using the CMOS-MEMS tunable capacitors. This enables the tuning of filter center frequency and bandwidth. The filter is designed to have a center frequency of 10GHz, a fractional bandwidth of 10%, and 0.1dB ripple in the passband. Fig. 4. shows the layout and dimensions of this filter. The effective electrical length of each resonator loaded with two capacitors is 450 at the filter center frequency. The capacitance values were determined using optimization tools in Agilent ADS. The capacitance values for Cl and C2 at zero dc actuation voltage are 0.23pF and 1.8pF, respectively. Given the initial gap between the plates and a capacitance value of 1.8pF, the area of the capacitor can be calculated as being only 560x400 m2 leading to the compact implementation of tunable filter.
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Fig. 2. CMOS-MEMS post-processing steps, RIE oxide removal (a), wet etching (b), CPD and 2nd oxide RIE (c).
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one port on-wafer measurement of the tunable capacitors performed from 50MHz to 40GHz using an HP8722ES vector network analyzer and Cascade RF probe station. The capacitance values are extracted by fitting the simulated SI, of an equivalent series RC circuit to the measured SI,. Fig. 5 shows the extracted capacitance versus biasing voltage for the 0.23pF capacitor. The measured pull-in voltage for this capacitor is 43V. A tuning range of 193% is achieved before pull-in. The quality factor of the capacitor is determined from the measured Sll. As shown in Fig. 6, the measured quality factor is above 20 at IOGHz. This is due to the cancellation of substrate loss and its parasitic effects at GHz frequency range. Another important effect of removing the silicon substrate is the improved self-resonance frequency. The measured self resonance frequency is higher than IOGHz. An optical image of the fabricated filter is shown in Fig. 7. The size of the filter is only 1.2x2.1 mm2 including all the tuning elements, RF pads, and the dc bias pads for tunable capacitors. Fig. 8 shows the simulated and measured insertion was
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The capacitor set (C) is used to change the center frequency by varying the effective electrical length of each resonator section whereas the second set (C1) tunes the input/output coupling by changing the tapping location. Using these two sets of tunable capacitors it is possible to tune the filter center frequency while maintaining a constant bandwidth. As shown in Fig. 9, when only C2 is used for tuning, the bandwidth is reduced from 955MHz to 764MHz after tuning while using both sets of capacitors the bandwidth remains almost the
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Fig. 7. Optical photograph of the integrated tunable bandpass filter.
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and return loss of the filter at OV. Measurements agree with the simulated results. There is a shift in the center frequency from simulated 9.95GHz to measured 9.50GHz which is likely because of the deflection of the plates of the capacitors as a result of residual stress after post-processing. At OV, the minimum insertion loss is measured to be 5.66dB with a bandwidth of 0.86GHz (9%) and a return loss better than 20dB.
IV. SIMULATION AND MEASUREMENT RESULTS
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Fig. 6. Measured quality factor of the tunable capacitor.
Fig. 4. Layout of the 2-pole interdigital bandpass filter with CMOS-MEMS tunable capacitors.
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Measured insertion loss and return loss for different bias voltages ranging from OV to 40V are shown in Fig. 10. The
Fig. 5. Extracted capacitance versus biasing voltage.
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midband insertion loss ranges from 5.66dB to 5.95dB and the tuning range is measured to be 1.6GHz (17%) with a constant bandwidth of 855MHz. V. Conclusion
Design, fabrication and test results of an integrated tunable bandpass filter have been reported. Tuning is achieved using high-Q and compact parallel-plate tunable capacitors fabricated using a novel CMOS-MEMS post-processing technique. The filter has been measured to have a center frequency of 9.50GHz with a tuning range of 17% and is only 1.2mm by 2. 1mm in size. To our knowledge it is the first time that an integrated tunable bandpass filter with parallel-plate CMOS-MEMS capacitors has been ever reported.
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Fig. 10. Measured filter tuning using different biasing voltages.
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Fig. 8. Simulated and measured insertion and return loss at OV. ACKNOWLEDGEMENT
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The authors wish to acknowledge the Canadian Microelectronics Corporation for providing fabrication services, W. D. Yan and R. Al-Dahleh for their assistance and discussions, R. Grant and B. Jolley for their technical support.
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REFERENCES
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[1] K. W. Fan, C. C. Weng, Z. M. Tsai, H. Wang, and S. K. Jeng, "K-band MMIC Active Band-Pass Filters," IEEE Microwave and Wireless Components letters, vol. 15, no. 1, pp. 19-21, January 2005. [2] Y. C. Chiang, H. C. Chiu, and W. L. Hsieh, "Implementation of Second-order Ku-band Chip filter on Si Substrate with Commercial 0.18[lm CMOS Technology," 2006 IEEE MTT-S Int. Microwave Symp. Dig. pp. 1249-1252, June 2006. [3] G. K. Fedder, and T. Mukherjee, "Tunable RF and Analog Circuits Using On-Chip MEMS Passive Components," 2005 IEEE Solid-State Circuits Conf: Dig., vol. 1, pp. 390-391, February 2005. [4] A. Oz, and G. K. Fedder, "CMOS-compatible RF-MEMS Tunable Capacitors," 2003 IEEE MTT-S Int. Microwave Symp. Dig. pp. 97-100, June 2003.
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Fig. 9. Simulation results for tuning the filter center frequency which illustrates the need to use both sets of capacitors to maintain a constant bandwidth.
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