2014 International Conference on Parallel, Distributed and Grid Computing
Area and Power Efficient 4 – Bit Comparator Design by Using 1- Bit Full Adder Module Pranshu Sharma
Anjali Sharma
Department of Electronics and communication Engineering APG Shimla University Shimla, HP, 171009, India
[email protected]
Department of Electronics and communication Engineering APG Shimla University Shimla, HP, 171009, India
[email protected] Abstract- In this paper an area and power efficient 56T 4-bit comparator design has been presented by using GDI technique. The proposed 4-bit comparator design consist of 28 NMOS and 28 PMOS. A GDI full adder module has been used to design this comparator which consumes less area and power at 120 nm as compared to previous full adder designs. The proposed 4- bit comparator design is based on this area and power efficient 10T full adder module. To get area and power efficiency a centralized full adder module has been used which avoid cascade implementation of XOR module to get sum and carry output. Full adder modules outputs have been used for the generation of output of 4-bit comparator designs. The proposed 4-bit GDI comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power and current variation with respect to the supply voltage has been performed on BSIM-4 using 120nm technology. Results show that Area of proposed 4- bit comparator design is 1320.3μm2 on 120nm technology. At 1.2V input supply voltage the proposed 4bit GDI comparator consumes 13.739μW power at BSIM-4. At 1.2V proposed GDI 4-bit comparator has shown improvement of 6.3% in terms of area and 69.42% in power as compared to the PTL 4- bit comparator.
speed and vice versa, hence, most architectures referring to one of those important properties. All architectures provide different insight and therefore require different implementation [4]. Traditional CMOS technology, results in developing of many logic design techniques so as to improve performance of logic circuits. One form of logic that is popular in low-power digital circuits is PTL - pass-transistor logic. Some of the main advantages of PTL over standard CMOS design are: High speed - due to the small node capacitances, Low power dissipation - as a result of the reduced number of transistors, Lower interconnection effects - due to a small area [5]. But PTL implementations have two basic problems [6] i.e. threshold drop across the single-channel pass transistors and static power dissipation. There are techniques that intend to solve the problems mentioned above. One is Transmission gate CMOS (TG) uses transmission gate logic to realize complex logic functions using a small number of complementary transistors. It solves the problem of low logic level swing by using PMOS as well as NMOS but its disadvantage is higher area consumption. Second is Complementary pass-transistor logic (CPL) which features complementary inputs/outputs using NMOS pass-transistor logic.
II.4- BIT MAGNITUDE COMPARATOR A 4 bit magnitude comparator is a hardware electronic device that takes two numbers of 4 binary bits each as input and determines whether one number is greater than, less than or equal to the other number. A 4 bit magnitude comparator block has been shown is shown in Fig.1 which can compares two 4 bit binary numbers A and B and the outcome of the comparator has been specified by three binary variable G (A>B), E (A=B) and L (A B or A< B compare the MSB bits first. If MSB bits are equal, then compare the next LSB pair of bits until bit are unequal. Input section of 4-bit comparator consist 4 XNOR cells
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2014 International Conference on Parallel, Distributed and Grid Computing
which give XNOR output of individual binary bit of A and B shown in Fig 2. Output of each XNOR cell is indicated by X0, X1, X2 and X3 respectively. Output of XNOR cells has been given by −
−
Xj = AjBj + Aj Bj
inverter, but there are two important difference that GDI cell contains 3 inputs - G (common gate input of NMOS and PMOS), P (input to the source/drain of PMOS) and N (input to the source/drain of NMOS) and Bulks of both NMOS and PMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with a CMOS inverter [7].
(1)
Where j = 0, 1, 2, 3 Truth Table for 4- bit comparator has been shown in Table-1 which tale two four bit binary numbers as input.
TABLE 1. TRUTH TABLE OF 4-BIT COMPARATOR INPUTS of 4 bit Comparator
Fig.3 Basic Gate Diffusion Input Cell
OUTPUT
A3, B3
A2, B2
A3, B3
A2, B2
A3, B3
A2, B2
A3 > B3
X
X
X
H
L
A3, B3 L
A3 < B3
X
X
X
L
H
L
A3 = B3
A2 > B2
X
X
H
L
L
A3 = B3
A2 < B2
X
X
L
H
L
A3 = B3
A2 = B2
A1 > B1
X
H
L
L
A3 = B3
A2 = B2
A1 < B1
X
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 >B0
H
L
L
A3 = B3
A2 = B2
A1 = B1
A0 < B0
L
H
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
H
L
L
A3 = B3
A2 = B2
A1 = B1
A0 = B0
L
H
L
A2 = B2
A1 = B1
A0 = B0
L
L
H
A3 = B3
No of different logic functions can be implemented by only two transistors by using Gate diffusion input (GDI) approach. Various logic functions of GDI cell for different input combination is shown in Fig.4. Six different functions can be implemented by GDI cell. Colored box and output LED is showing high output.
Fig.4 Various Function of Basic GDI Cell [8]
Where H = High Output, L = Low Output, X = Don’t Care
The exact transient analysis for a basic GDI cell, in most cases, is similar to a standard CMOS inverter [9].This classic analysis is based on the Shockley model, where the drain current ID expressed as follows:
All three conditions G, E and L can be achieved by E ( A = B ) = X 0 X 1X 2 X 3 −
−
−
G ( A > B ) = A 3 B 3 + X 3 A 2 B 2 + X 3 X 3 A1 B1 −
−
−
−
L( A < B) = A3 B3 + X 3 A2 B2 + X 3X 2 A1B1 + X 3X 2X1 A0 B0
(2)
A. Subthreshold region
(3)
For Subthreshold region the gate source voltage is less then and equal to the threshold voltage i.e. VGS ≤ VTH. Drain current in subthreshold region is given as
(4)
I D= I DO (W / L)e qVGS / KT
(5)
B. Linear region For linear region the drain source voltage is less than that of the difference between gate source voltage and threshold voltage i.e. VDS < VGS-VTH. Drain current in linear region is given as 2 I D = K {(VGS − VTH )VDS − 0.5VDS
(6)
C. Saturation region For saturation region the drain source voltage is greater than and equal to that of the difference between gate source voltage and threshold voltage i.e. VDS ≥ VGS-VTH. Drain current in linear region is given as
Fig.2 Logic Diagram 4 - bit comparator
III.GDI TECHNIQUE GDI (Gate Diffusion Input) is a new technique of low power digital combinatorial circuit design. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. GDI approach allows implementation of a wide range of complex logic functions using only two transistors. GDI method is based on the use of a simple cell as shown in Fig.3. The basic GDI cell looks like the standard CMOS
I D = 0.5 K (VGS − VTH ) 2 Where
2
K = Drivability Factor VTH = Threshold voltage W = Channel Width L = Channel length.
(7)
2014 International Conference on Parallel, Distributed and Grid Computing
In contrast with CMOS inverter analysis [10], where VGS was taken as an input voltage, in most of GDI circuits VDS must be considered as a variable of input voltage in the Shockley model. The case of most interest is when a step signal is supplied to diffusion of NMOS transistor and causes a swing drop in output.
comparator designs consume less power and area as compared to complementary CMOS design. To reduce transistor count area and power efficient technique has been used to design a full adder which is further used in comparator design.
IV.COMPARATOR SCHEMATICS USING 1-BIT FULL ADDER Comparator is one of the basic building blocks of the arithmetic unit of digital signal processors and ASIC’s used in various digital applications. Various approaches to design CMOS Comparator by using various different logic styles have been presented in literature [11]-[14]. Area, speed and power consumption are the main performance estimation criteria in CMOS Comparator design and these criteria’s conflicts with each other i.e. each criteria’s can’t be achieved simultaneously.
Fig.7 PTL 1- Bit Comparator Design Comparator design can be implemented by using different logic style but one logic style can give good performance in estimation criteria and degraded performance in other. Charging or discharging of the load capacitance of any circuit can cause dynamic power dissipation in CMOS VLSI circuits [16]-[17]. To overcome this PTL based 18T 1-bit comparator design by using 10T full adder module has been shown in Fig.7 the PTL comparator circuit consumes less area and power as compared to CMOS and TG comparator designs.
V.PROPOSED 4-BIT COMPARATOR SCHEMATICS In proposed 4-Bit comparator design a 1-bit Full adder has been used as a basic building block. In this proposed 4-bit comparator four 1-bit Full adder modules have been used to obtain the comparative outputs as shown in Fig. 8.
Fig.5 CMOS 1-Bit Comparator Design [15] In [15] various 1-bit comparator designs have been presented by using 1-bit Full Adder as a basic building block. To achieve output of 1-bit comparator C input of full adder has been connected to the ground and an inverted input has been given at B input terminal. By using these input connections carry output of 1-bit Full Adder directly act as A>B output and for the generation of A=B and B>A different input combinations for AND gate has been used in the comparator circuit.
Fig.8 Logic Block Diagram of Proposed 4-bit comparator An inverted input has been given at the B input terminal of the used full adder design and C input of 1st full adder has been connected to the ground. Carry output of 1st full adder acts as a Cin to the next full adder module and so on. Carry output of 4th Full adder directly act as B>A output of the 4-bit comparator. For the generation of A=B four AND gates have been used and output of 1st AND gate is cascaded to one of the input in next AND gate with SUM output of full adder as another input. Proposed 4-bit GDI comparator in Fig. 10 has been implemented by using only 56 transistors. Proposed comparator has been designed by using four 10T GDI full adder modules [9] shown in Fig.9. In this GDI full adder module XOR-XNOR module has been implemented by 6 transistors. Output of GDI XOR-XNOR cell is used to for the
Fig.6 TG 1- Bit Comparator Design [15] In Fig.5 a 42T 1-Bit CMOS comparator design has been presented by using complementary CMOS 1-bit Full Adder design. This 1-Bit CMOS comparator design gives the full voltage swing at the output by disadvantage of this design is the large area consumption as compared to other designs. A TG 36t 1-bit comparator design by using 22T Full Adder has been shown in Fig. 6 [15]. TG based 1-bit
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2014 International Conference on Parallel, Distributed and Grid Computing
carry and sum output generation in used full adder module. The proposed 4-bit comparator consist 28 PMOS and 28 NMOS which is least as compared to other 4- bit comparator designs by CMOS, TG and PTL logic. As shown in Fig.10 the proposed 4-bit comparator consist four full adder modules designed by GDI logic which is area and power efficient as compared to CMOS, TG and PTL comparator.
Table 2. Comparative Analysis of 1-bit GDI Full Adder 120nm 1-Bit Full Adder Design
CMOS
TG
58.7
Width (μm)
PTL
48.6
GDI
22.7
21.2
Height (μm)
9.8
8.4
7.9
8.4
Area (μm2 )
577.4
408.2
179.6
177.9
Proposed 4- bit comparator is best in terms of area as compared to CMOS, TG and PTL comparator. Comparative analysis on 120nm has been shown in Table.3. Different 4-Bit comparator designs by using conventional CMOS, TG and PTL Styles have been shown in Fig.13. 4-Bit comparator by conventional CMOS consist 176 transistors, TG comparator consists 116 transistors and PTL comparator consists 36 transistors. TABLE 3. COMPARATIVE ANALYSIS OF 4-BIT GDI COMPARATOR 120NM Fig.9 GDI 1 - Bit Full Adder Design
4-bit comparator design
Two hexadecimal input has been used to get two 4 bit binary numbers. Four AND gates has been used in the cascade mode to get A=B output of 4-bit comparator. Sum output of first full adder acts as one of the input to the first AND gate. Carry output of first GDI Full adder acts as a Cin input of the next Full Adder. Carry output of last full adder act as B> A output of 4-bit comparator. Glowing LED in Fig.10 shows high output. The proposed comparator design only shows two output A=B and B>A. If both LED’s at the output are OFF then output of 4-Bit comparator is considered as A>B. The used GDI Full adder and the proposed 4- bit comparator has been compared with other adder and comparator designed by the CMOS, TG and PTL logic in terms of area and power in MICROWIND 3.1 designing tool on 120nm technology.
CMOS
TG
PTL
Proposed GDI
NMOS
88
60
28
28
PMOS
88
56
28
28
Width (μm)
231.5
185.4
93.2
93.2
Height (μm)
16.6
16.1
15.1
14.2
Area (μm2 )
3833.3
2981.2
1409.8
1320.3
VI.LAYOUT ANALYSIS For a very complex circuit it become very difficult to conduct the manual layout so an automatic layout generation approach is preferred. The schematic diagram has been firstly designed and validated using DSCH tool at logic level. Although at logic level DSCH have feature to analyze timing simulation as well as power consumption but accurate layout information is still missing.
Fig.10 GDI 4 - Bit Comparator Design MICROWIND designing tool deals with both front end and back end designing of the VLSI circuits. In front end DSCH designing tool has been used which has ability of transistor level and gate level designing and can generate VERILOG file which can be compiled by the MICROWIND back end designing tool to get power and area consumption. Design flow from logic design to layout and proposed 4- bit comparator has been shown in Fig.12 and Fig.13 respectively which shows exact functionally of GDI Full Adder for SUM and Carry output and exact functionally 4-bit comparator for A=B and B>A. Comparator designs by using CMOS and PTL logic have been shown in Fig. 13 and comparative analysis has been shown in Table 2 and 3.
Fig.12 Design flow from logic design to layout [18] VERILOG file is generated by the DSCH tool which is understandable by the MICROWIND to construct the corresponding layout with exact desired design rules. Another way to create the design is by NMOS and PMOS devices using cell generator provided by the MICROWIND. The advantage of this approach is to avoid any design rule error. W/L can be adjusted by the MOS generator option on MICROWIND tool. In DSCH designing tool design should be improved before its conversion in to VERILOG file. Layout of GDI 4 Bit comparator has been shown in Fig. 14.
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2014 International Conference on Parallel, Distributed and Grid Computing
Fig 13.a CMOS 4-bit Comparator
Fig 13.b PTL 4-bit comparator Fig 13: 4- Bit Comparator Designs
Fig.14 Layout of GDI 4-bit Comparator on 120nm Area and power consumption of proposed 4- bit comparator has been evaluated on 120nm technology by using MICROWIND designing tool. Simulation of proposed 4-bit comparator has been performed to get power and current variation with respect to the supply voltage. Parametric analyses of proposed 4-bit comparator have been performed using the MOS Empherical model Level-3 and BSIM Model-4 at different power five different supply voltages.
3D view of proposed 4-bit comparator design has been shown in Fig.15.
Fig.15 3D view of proposed 4-bit comparator design Various steps used for the creation of this structure are- initial substrate creation, N- diffusion, SiO2 isolation, thin oxide growth, thin oxide reduction, polysilicon deposit, N+ implant, P+ implant, 2nd polysilicon deposit, contact creation, metal layers deposition and via hole creation, passivation oxide deposition and passivation etching. This layout consist 6 metal layers and 2 polysilicon layers.
VII.SIMULATION RESULTS
Fig.17 Power vs. Supply Voltage on LEVEL-3 Threshold voltage has been taken as 0.4V for both levels which is the voltage above which the power and current starts increasing with the increase in supply voltage. Operating temperature has been taken 270C for both LEVEL-3 and BSIM-4.MOS Empherical model Level-3 and BSIM Model-4 provides the feature of different curve fitting parameters which is useful in parametric analysis. MOS
Fig.16 Power vs. Supply Voltage on BSIM-4
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2014 International Conference on Parallel, Distributed and Grid Computing
Empherical model Level-3 has features of 10 different curve fitting parameters whereas BSIM Model-4 works with 19 different parameters. Graph for variation in power with respect to Vdd has been shown in Fig.16 for BSIM-4 and in and Fig. 17 for LEVEL-3. The proposed 4-bit comparator design has been compared with CMOS, TG and PTL 4- bit comparator in terms of power consumption and comparison has been shown in Fig. 18. On five different supply voltages the proposed 4-bit comparator shows best performance in terms of power consumption as compared to the CMOS, TG and PTL 4- bit comparator on BSIM-4 analytical model.
[5]
[6]
[7]
[8]
Journal of Emerging Technologies in Computational and Applied Sciences, Vol. 4 , No. 1, pp. 102-108. A Morgenshtein, Fish, Wagner, “Gate - Diffusion input (GDI) A novel power efficient method for digital circuits: A Design Methodology ,” IEEE International Conference, pp. 39 – 43, 2001. Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gatediffusion input (GDI): A Power Efficient Method For Digital Combinational circuits,” IEEE Transaction on Very Large Scale Integration Systems, Vol. 10 , No . 5, pp. 566 - 581, 2002. Agrawal, A.K.; Mishra, S.; Nagaria, R.K. , “Proposing a Novel Low Power High Speed mixed GDI Full Adder Topology,” International Conference on Power, Control and Embedded System, pp. 1 – 6, 2010 Anjali Sharma, Rajesh Mehra, “Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique,” International Journal of Computer Applications, Vol.66, No.
4, pp. 15-22. [9] Anjuli, Satyajit Anand, “2-Bit Magnitude Comparator Design Using Different Logic Styles,” International Journal of Engineering Science Invention, Vol. 2, No. 1, pp. 13-24 [10] A.N. Nagamani, H V Jayashree , H R Bhagyalakshmi, “Novel Low Power Comparator Design using Reversible Logic Gates,” International Journal of Computer Science and Engineering,Vol.2, No. 4, pp. 566-574. [11] H V Jayashree, A.N. Nagamani, H R Bhagyalakshmi, “Modified TOFFOLI GATE and its Applications in Designing Components of Reversible Arithmetic and Logic Unit,” international journal of Advance Research in Computer Science and Software Engineering, Vol.2, No. 7, pp. 207-210. [12] H G Rangaraju, Vinayak Hegde, K B Raja, “Design and Optimization of n-bit Reversible Binary Comparator,” International Journal of Computer Applications, Vol. 55, No.18, pp. 22-30. [13] Anjuli, Satyajit Anand, “High speed 64-Bit CMOS Binary Comparator,” International Journal of Innovative Systems Design and Engineering, Vol. 4, No. 2, pp. 45-58. [14] Geetanjali Sharma, Uma Nirmal, Yogesh Misra, “A Low Power 8-bit Magnitude Comparator with Small Transistor Count using Hybrid PTL/CMOS Logic,” International Journal of Computational [15] Anjali Sharma, Richa Singh, Pankaj Kajla “Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic,” International Journal of Computer Applications, Vol.82, No. 10, pp. 5-13. [16] Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; GuoShing Huang,” A Low -Power High-speed Hybrid CMOS Full Adder For Embedded System,” IEEE transactions on Design and Diagnostics of Electronic Circuits and Systems, vol.13, No.6, pp.-1 – 4, 2007. [17] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, “New Design Methodologies for High Speed Mixed Mode Full Adder Circuits,” International Journal of VLSI and Communication Systems, Vol. 2, No. 2, pp.-78-98, 2011. [18] Etienne Sicard, Sonia Delmas Bendhia, Basic of CMOS Cell
Fig.18 Comparison of Power Consumption on BSIM-4 VIII.CONCLUSION An alternative 4-bit comparator design by using GDI approach has been proposed which consists 56 transistors. Proposed 4-bit comparator has been implemented by using 28 NMOS and 28 PMOS transistors. Proposed 4- bit comparator has been designed using an area efficient GDI Full adder module which has been implemented by using only 10 transistors. Area and power consumption of proposed 4-bit comparator has been shown on120nm using LEVEL-3 and BSIM-4 analytical models. Area of proposed 4- bit comparator design is 1320.3μm2 on 120nm technology. At 1.2V input supply voltage the proposed 4- bit GDI comparator consume 13.739μW power at BSIM-4 and 14.407 μW power at LEVEL-3. The proposed 4-bit comparator circuit can work efficiently with minimum voltage supply of 0.4V and can work on wide range of frequency range between 2MHz to 400MHz. Proposed GDI 4-bit comparator has been shown 65.5% efficiency as compared to CMOS, 55.7% efficiency as compared to TG and 6.3% efficiency as compared to PTL 4- bit comparator in terms of area. At 1.2V input supply the proposed 4- bit GDI comparator has been shown 87.6%, 84.7% and 69.42% power efficiency as compared to the CMOS, TG and PTL 4- bit comparator respectively.
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