Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop Raghavendra R G
Bharadwaj Amrutur
Electrical Communication Engineering Indian Institute of Science Bangalore, India
Electrical Communication Engineering Indian Institute of Science Bangalore, India
[email protected]
[email protected]
ABSTRACT In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CSM analog process with 1.8V supply. The proposed circuits achieved up to 85% savings in capacitor area. Simulations showed good match of the new circuits with the conventional circuit. The proposed circuits are particularly useful in applications that demand low die area.
Keywords Dual-path loop filter.
1. INTRODUCTION A PLL is an integral component of clock generation circuits. An on-chip implementation of a CPPLL poses numerous challenges. One such challenge that is worth mentioning is the on-chip integration of loop filter. It is worth mentioning because the area occupied by loop filter contributes to a significant percentage of the overall area occupied by the CPPLL. The continuous-time linear model of a 3rd order CPPLL [1] is as shown in Figure 1 below.
The simplified open loop transfer function, HOPEN(s), for the above CPPLL model of Figure 1 is given by, HOPEN(s) = (KPLL * (1 + (s/ωZ)) * ωZ) / (s2 * (1 + (s/ωP2))) (1) Where, KPLL = (ICP * R * KVCO * B) / (2 * π * N* (B+1)) (2) B = CZ / CP, is the ratio of two capacitors used in the loop filter,
ωZ = 1 / (R * CZ), is the location of zero of the loop filter, (3)
ωP2= (CZ + CP) / (R * CZ * CP), is the location of second pole of the loop filter. (4) The optimum crossover frequency (ωC) [2] and maximized phase margin (φM) for above HOPEN(s), is given by ωC = KPLL,
(5)
φM = tan-1√(ωP2/ωZ) -tan-1√(ωZ/ωP2) = tan-1 (B /(2*(√B+1))) (6)
From the above equation (6), it is clear that the stability of the 3rd order charge pump PLL depends on the ratio of two capacitors used in the loop filter. Table 1 below shows the phase margin obtained for various values of capacitor ratios. Table 1. Phase Margin (φM) Vs Capacitor Ratio (B) Capacitor Ratio (B)
Phase Margin (φM)
2
30o
4
41.8o
8
53.1o
14
61o
From above table 1, it is clear that the phase margin depends heavily on the capacitor ratio (B) and that for a 60o phase margin; the capacitor ratio should be greater than 14. Figure 1. Continuous-Time Linear Model of CPPLL
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A straightforward passive implementation of 2nd order loop filter would consume a larger area due to higher value of B needed to ensure stability. In order to minimize the area occupied by the loop filter, one is forced to go for an active implementation of loop filter that can minimize the area occupied. Dual-path loop filter is mostly widely used to realize the on-chip loop filter with minimum area [2]-[5]. The continuous-time linear model of a dual-path loop filter proposed in [2]-[5] is as shown in Figure 2 below.
VCTRL= {[ICP/(2*π)]*[1+s*(R*CZ {s*(s*R*CZ*CP +CZ + CP)} ωZ = 1/ [R*(CZ + K*CZ )]
+
K*R*CZ)]} / (9) (10)
From above equation (10) it is clear that the above circuit boosts the zero location by ‘K+1’ times and hence equivalently scales up CZ value. Though the above circuit seems to be highly promising, practical implementation of K*[ICP/2*π] charge pump source shown in Figure 3 is difficult, as the charge needs to be transferred from low voltage node to high voltage node. Figure 2. Continuous-Time linear model of Dual-path loop filter. The equations for control voltage (VCTRL) and the location of zero (ωZ) for the circuit shown in Figure 2, are given by,
An alternate practical implementation of the above concept is as shown in Figure 4 below. Here again we divert a fixed amount of charge from CZ and add the another fixed amount of charge on to CP, so that the effective looking impedances are different.
VCTRL = {[ICP/(2*π)] * [1+s*R*(K*CZ + CP)]} / [s*CZ * (1+s*R*CP)] (7) ωZ = 1/ [R*(K*CZ + CP)]
(8)
Thus, scaling the dual-charge pump currents is equivalent to scaling up the capacitance, CZ, value and thereby the above circuit minimizes the area occupied by the loop filter. Though the dual-path loop filter minimizes the area occupied by the loop filter, it suffers from the disadvantage that it needs extra elements like summer / operational amplifiers (opamps) [2]-[5], which simply mean more area and extra power. In this paper, we propose two new modified dual-path loop filter circuits that need no extra elements (such as summer and opamp) and hence doesn’t consume any extra power / area. Section 2 of the paper discusses the proposed circuits and its implementation details. Section 3 of the paper presents the simulation results obtained. Finally, the paper is concluded in section 4.
2. Proposed Circuit and its Implementation Details One can significantly boost up the zero location by diverting a fixed amount of charge from CZ and adding the diverted charge from CZ to CP, as shown in Figure 3 below.
Figure 4. Continuous-Time linear model of Proposed Modified Dual-path loop filter Assuming 0 < P < 1, we have the equations for control voltage (VCTRL), location of zero (ωZ) and the KPLL for circuit shown in Figure 4 given by, VCTRL = {[ICP/(2*π)]*[(1-P) +s*(R*CZ + K*R*CZ)]} / (11) {s*(s*R*CZ*CP +CZ + CP)} ωZ = (1-P) / [R*(CZ + K*CZ)]
(12)
KPLL = [ICP * R * KVCO * B * (K+1)] / (2 * π * N* (B+1)) (13) Note that when P = 0, the equations for control voltage (VCTRL) and the location of zero (ωZ) is same as that of the circuit shown in Figure 3. However addition of ‘P*[ICP/2*π]’ source provides an additional degree of freedom to the user to appropriately modify the zero location. Note that the two charge pumps shown at the top / bottom of Figure 4 can be merged in to one, thereby avoiding the need for extra charge pumps. The proposed modified dual-loop path loop filter (see Figure 4) boosts the zero location by ‘(K+1) / (1-P)’ times as compared to loop filter (see Figure 1) without the additional circuitry. Further, the proposed modified dual-path loop filter doesn’t need any summer / opamp block and hence saves extra area and power.
Figure 3. Continuous-Time linear model of Proposed Dualpath loop filter The equations for control voltage (VCTRL) and the location of zero (ωZ) for the circuit shown in Figure 3, are given by,
A dual form of the circuit shown in Figure 4, including parasitic capacitance (CA) across resistor (R), is as shown in Figure 5 below. Assuming 0 < P < 1, we have the equations for control voltage (VCTRL), location of zero (ωZ), second pole (ωP2) and the KPLL (neglecting CA) for circuit shown in Figure 5 given by,
Table 2. PLL Loop Parameters
Figure 5. Dual form of circuit shown in Figure 4 with parasitic capacitance (CA) included. VCTRL = {[ICP/(2*π)] *[(1-P)+s*(R*CA – P*R*CA + R*CZ + K*R*CZ)]} / {s*[s*R*CZ*CP + s*R*CA*CP + s*R*CZ*CA + CZ + CP]} (14) ωZ = (1-P) / [R*(CZ + CA – P*CA + K*CZ)]
ωP2= (CZ + CP) / (R*CZ*CP + R*CA*CP + R*CZ *CA)
Type of Loop Filter Circuit
ICP (uA)
Ratios
R (Ω)
CZ (pF)
CP (pF)
Figure 1
160
B=15
700
912
60.8
Figure 4
40
1300
60.8
60.8
Figure 5
40
1300
60.8
60.8
B=1, P=0.5, K=3 B=1, P=0.5, K=3
Figure 6, 7 & 8 below shows the simulated response of the PLL with conventional passive loop filter (see Figure 1) and proposed modified dual path loop filter circuits of Figure 4 & 5.
(15) (16)
KPLL = [ICP * R * KVCO * B * (K+1)] / (2 * π * N* (B+1)) (17)
Note that when P=0 and CA=0, the equations for control voltage (VCTRL) and the location of zero (ωZ) is same as that of the circuit shown in Figure 3. This implies that one has to minimize / keep parasitic capacitance (CA) as small as possible compared to CZ and CP, so as to obtain maximum gains from the above circuit. Otherwise, one will be forced to use a higher ‘K’ value to obtain a desired phase margin. Note that the circuit shown in Figure 5 also doesn’t need any extra summer / opamp, as compared to other dual-path loop filters proposed in literature [2]-[5]. One big advantage of the circuit of Figure 5 over that shown in Figure 4 is that it is relatively easy to match charge-pumps of Figure 5 circuit as compared to the Figure 4 circuit. This is because the dual charge pump current directions are same in case of Figure 5, where as they are opposite in case of Figure 4. Hence the circuit of Figure 5 will suffer from lower mismatch as compared to the circuit shown in Figure 4.
Figure 6. Simulated response of PLL Control Voltage, with conventional passive loop filter (During Power-Up and for a frequency step of 12.5 MHz at 30us, after Power-up). The observed maximum worst-case ripple (across all PVT) on “VCTRL” is less than 0.5 mV.
3. Simulation Results The proposed circuits (Figures 4 & 5) were implemented in 0.25µ CSM Analog Process. The core supply voltage is 1.8V +/10%. The desired output frequency of the PLL is 200MHz and reference input frequency is 50MHz. The phase margin targeted was greater than > 60o. Hence, the (pole2/zero) ratio was chosen to be 16. The open-loop bandwidth of the PLL was chosen to be 1 MHz. The charge pump current budget was fixed to be 160 uA. The simulated VCO conversion gain (KVCO) was found to be 240 MHz/V. The charge-pump structure used is of current steering type with buffer [6]. To have fair comparison, the power budget was kept same for all the simulated cases. The loop parameters for the PLL with conventional passive loop filter (see Figure 1) and for the PLL with proposed modified dual-path loop filter circuits (Figures 4 & 5) are given in table 2 below.
Figure 7. Simulated response of PLL Control Voltage, with loop filter circuit of Figure 4. (During Power-Up and for a frequency step of 12.5 MHz at 30us, after Power-up). The observed maximum worst-case ripple (across all PVT) on “VCTRL” and on “netX” is less than 2 mV.
the conventional passive loop filter circuit. Further the proposed circuit avoids the need for extra elements and thereby saves area and power as compared to existing dual-path loop filters [2]-[5]. The proposed circuits are particularly useful in applications that demand low die area. Simulations confirmed good match between the new proposed circuits and the PLL with conventional passive loop filter circuit (see Figures 6, 7 & 8).
5. ACKNOWLEDGMENTS The authors would like to thank PULSECORE SEMICONDUCTOR (INDIA) PVT LTD for supporting this research work. Figure 8. Simulated response of PLL Control Voltage, with loop filter circuit of Figure 5. (During Power-Up and for a frequency step of 12.5 MHz at 30us, after Power-up). The observed maximum worst-case ripple (across all PVT) on “VCTRL” is less than 3 mV and on “netX” is less than 6 mV. Note that the ripple on “VCTRL” is half of that on “netX”, due to capacitance divider. This means the ripple obtained using above circuit is 50% lower than that obtained in [2], [4]-[5]. From above Figures 6, 7 & 8, one can observe good match between proposed circuits and PLL with passive loop filter circuit. Note that the mismatch in dual charge pumps gives rise to additional ripple on “VCTRL” node. Hence, careful common centroid layout is necessary to ensure good performance for the proposed circuits.
4. Conclusions We proposed two new modified dual-path loop filter circuits (Figures 4 & 5) that can substantially minimize the area taken by the loop filter as compared to the conventional passive loop filter circuit. The proposed circuits were designed in 0.25µ CSM analog process with 1.8V supply. The proposed circuits achieved savings of up to 85% in the overall capacitor area as compared to
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