key parameters, the amount of silicon area and time required to implement a OFT ... Lower bounds on area (A) and time (T) are related to the number of points.
495
Area-Time Complexity for VLSI
C. D. Thompson Carnegie-Mellon University Pittsburgh, Pennsylvania
Abstract The complexity of the Discrete Fourier Transform (OFT) is studied with respect to a new model of computation appropriate to VLSI technology. This model focuses on two key parameters, the amount of silicon area and time required to implement a OFT on a single chip. Lower bounds on area (A) and time (T) are related to the number of points
(N) in the OFT: AT2 > N2/16. This inequality holds for any chip design based on any algorithm, and is nearly tight when T • e N2 /16.
4. Area The total area occupied by a VLSI design is the sum of the areas of its PEs, wires, and nexi. A lower bound on wire and nexus area is derived in this section. Inclusion of PE area can at most affect the result by a constant factor, since there is one nexus per PE, and PEs have area bounded by a constant. Associate with each VLSI design the following graph, G. Each nexus is a vertex. Each wire connecting two nexi is an edge between corresponding vertices. Denote by I the subset of vertices that are nexi of the N "input PEs". Let rv be the minimal bisection width of I in G. Theorem 1: The area occupied by the wires and nexi of a VLSI design that corresponds to a graph of width rv is greater than rv2/4. Proof. Orient the VLSI design in a Cartesian space. Consider lines of the form x • c.
Each
will separate the nexi of the N input PEs into three subsets: those to the left, split by, or to the right of the line. Denote these sets by L, S, and R. Find a value of a for which Ill + lSI 2: N/2 and IRI + lSI 2: N/2 (such an a exists by monotonicity). If lSI - 0 , the line
x=c would define a cutset of I in G, hence it would cut at least w edges.
Otherwise,
split S into two subsets, S 1 and S2, such that Ill + IS 1l • IRI + IS2I • N/2. Remembering that a nexus of degree d occupies a square of side d, each nexus in S 1 may be considered to lie wholly to the left of the line x•a (the wires connecting to the nexus on the right side of x • c may be "continued" right up to the x-c border).
So the
bisecting line still cuts at least rv wires. The line x•a is said to account for the w square units of area of wire and nexus that lie within 1/2 unit distance of it.
ARCHITECTURE SESSION
Ar ea-Time Complexity for VLSI
505
Next, consider "zig-zags" of the form {%•a-1 for y~b, %•a+l for ysb, and y•b for
a-1 S%Sa+l }.
Using the a determined above, vary b to obtain another bisection of the
input nexi. Only two wires may cross the horizontal (y•b) segment, so that its vertical sections must cross at least w-2 wires. This zig-zag accounts for the w-2 square units of wire and nexus that lie within 1/2 unit of its vertical sections. In all, Lw/2J zig - zags may be drawn, each of the form {%•a-le for y~b, %•a+k for ,sb, and y • b for a-lcS%Sa+k}. Each accounts for w-2k area. The total area of wire and nexus is thus
Lw-2k > w2/4. Oskstw/2]
5. Time The speed of a VLSI design may be limited either by the time taken by arithmetic operations or by the time taken to get intermediate results to the proper place.
It is
the latter that generally places the stricter limit on large VLSI designs for the OFT, by the following argument. As noted in section 2, a PE can take at most t units of time to update its word. The information used to perform this update must have taken at least one unit of time to reach the PE. Thus, within at most a factor of t, it is the routing of intermediate re sults rather than the arithmetics performed on them, that limits the timing of VLSI designs. The following theorem places a lower bound on the time required to compute a OFT.
Its proof is based on a consideration of the amount of information that must be transmitted during the course of any computation of a OFT. Theorem 2: Associate a graph with each VLSI design as in Section 4. At least N/(2w) time is required to compute an N point OFT on a VLSI design that corresponds to a graph of width w.
Proof sketch. The theorem is a consequence of the following property of the OFT. View the OFT as
CALTECH CONFERENCE ON VLS I , Jan uary 1979
C. D. Thompson
506
a matrix-vector multiplication ~ • A%
Bisect the N elements of ~ into two equal-sized subsets elements of ~ into a.ny two disjoint subsets ~ 1 and ~ 2 .
y1
and
y2.
Partition the
This decomposes the OFT
problem into two subproblems of the form
~1 • A11%1 + A12%2 Y2- A21%1 + At2%2
It is possible to show that (1)
This follows (non-trivially) from an argument on the number of zeros of a polynomial of degree N/2. Rank( A 1 2 > ~
If k of the elements of %1 are among the first N/2 elements of %, then k. In this case, Rank(A 2 1) ~ N/2 - k.
This property of the OFT holds for any bisection of the elements of ~. In particular, it holds for the bisection of the output PEs that realizes w, the minimum bisection width. Choose %1 to be the set of input PEs that are included with ; 1 in the bisection of the output PEs. The computation of y1 will require k words of information about ~ 2 , if Rank(A 12 > • k. A similar argument holds for
y2, so
that N/2 words of information must
pass over the w wires that separate %1 from ~2·
It takes at least N/(2w) time to pass N/2 words over w wires, hence the theorem.
6. Conclusion Theorems 1 and 2 can be immediately combined to give the main result of the paper. Theorem 3: If a VLSI design with area A computes an N point OFT in time T, then AT2 > N2/16. This
theorem
is
nearly
tight
for
at
least
two cases.
Using
a mesh-type
interconnection pattern, O(N) space and O(N1/2) time is sufficient to compute the OFT. Using a perfect shuffle interconnection, O(N2/Iog l/2N) area and ()(log N) time is sufficient [Pease 68, Thompson 80].
ARCHITECTURE SESSION
507
Area- T ime Complexity fo r VLS I
The following theorem is of interest if a particular cost function is to be minimized. Theorem 4: non-negative x
s
For any VLSI design with area A and time T, and for any 2, ATX - .n(Nl +x/2).
Proof. The area of any VLSI design with N input PEs must be fl(N) since each PE has a nexus of at least unit area. By Theorems 1 and 2, ATx • fl(N + w2/4)
* (N/2w)X
Without loss of generality, let w • Nl/2+•. Then ATx • .n(N1+x/2+•x+ N1+x/2+•(2-x)) Since Osxs2, the second term increases with • while the first term decreases with t. Clearly, . ..o achieves the minimum value, hence the theorem. • From the proof of Theorem 4, it is clear that the optim•l design has w•e(Nl/2), which corresponds to a mesh-type interconnection pattern. A
similar
analysis
multiplication,
Gaussian
may
be
performed
elimination,
for
transitive
other closure,
problems, Including sorting,
and
matrix
permutation
[Thompson 80]. Acknowledgements. James B. Saxe formulated and proved equation 1. Leo J. Guibas and the XEROX Palo Alto Research Center gave guidance 1nd generous support during the early phases of the research that led to this paper. Mere acknowledgement can hardly discharge my debts to my thesis advisor, H. T. Kung.
No one else could have given better hints at crucial moments, and I despair
of ever finding a more selfless researcher.
References [Aho 74)
Aho, Alfred V., Hopcroft, John E. and Utlm1n, Jeffrey D.
The Design. o.ncl An.o.lysis of Compu.t•r Algorithnu. Addison- Wesley, 197 4.
CALTECH CONFERENCE ON VLSI , Janu ary 197 9
508
[Bonneau 73]
C . D. Thompson
Bonneau, Richard J. A Cla.ss of Finite Computation Structures Supporting the Fcut Fouri.er
Transform. Technical Report 31, Massachusetts Institute of Technology Project MAC, March 1973. [Cutler 78]
Cutler, M. and Shiloach, Y. Permutation Layout. Networks 8:253-278, 1978.
(Garey 74]
Garey, M. R., Johnson, D. S., and Stockmeyer, L. Some Simplified Polynomial Complete Problems Proc. 6th Annual ACM Symposium on Theory of Computing, SIGACT, pages 47 - 63, 1974.
[Mead 78]
Mead, Carver and Rem, Mart in. Cost and Performance of VLS/ Computing Structures. Technical Report 1584, California Institute of Technology Computer Science Department, 1978.
[Pease 68]
Pease, Marshall C. An Adaptation of the Fast Fourier Transform for Parallel Processing. journal of the ACM 15(2):252-264, April 1968.
[Savage 77]
Savage, J. E. and Swami, Sowmitri. Space- Time Tradeoffs in the FFT Algorithm. Technical Report TRCS-31, Brown institution, August 1977.
[Sutherland 73]
Sutherland, Ivan E. and Oestreicher, Donald. How Big Should a Printed Circuit Board Be?. IEEETC C- 22:537-542, May 1973.
[Thompson 80]
Thompson, C. D.
A Complexity Theory for VLSI. PhD thesis, Carnegie-Mellon University Computer Science Department, 1980. [von Neumann 66] von Neumann, J.
The Theory of Self-Reproducing Automctc. Univ. of Illinois, Urbana, Ill., 1966.
ARCHI TECTURE SESSION
