Deep Submicron VLSI Floorplanning Algorithm. Patrick Hung and Michael J. Flynn. Computer System Laboratory, Gates Building, Stanford University, CA 94305.
Deep Submicron VLSI Floorplanning Algorithm Patrick Hung and Michael J. Flynn Computer System Laboratory, Gates Building, Stanford University, CA 94305 {hung, flynn}@arith.stanford.edu fax: (650) 725-6949 Abstract In deep submicron VLSI designs, cross capacitance between adjacent wires becomes the dominant factor in determining chip performance and power consumption. Consequently, traditional floorplanning algorithms, which typically optimize for die area and ignore wire congestion, become inadequate in deep submicron era. Based on a stochastic congestion model, we propose a floorplanning algorithm that optimizes for chip power consumption and performance. A floorplanning prototype was built to prove the effectiveness of the algorithm. We have verified the prototype with MCNC benchmarks, and the results are very promising. 1 Introduction Designing with deep submicron feature sizes presents new challenges in complexity, performance, and productivity [3]. In the past, chip performance and power consumption were mostly caused by device parasitic capacitance. However, as feature size continues to shrink, interconnect cross capacitance will displace device capacitance to become the predominant factor in determining chip performance and power dissipation [10]. Most traditional floorplanning algorithms [8] optimizes total chip area but ignore the effects of interconnect capacitance. Using the present floorplanning tools, it becomes increasingly more difficult for IC designers to meet the timing and power specifications. This paper describes a new floorplanning algorithm that takes interconnect congestion into consideration. In Section 2, we introduce a generalized stochastic congestion model, which supports via minimization, routing obstacles, multi-pin nets, and routing among multiple macro blocks. In Section 3, we derive the objective function to minimize total interconnect delay and power dissipation. In Sections 4 and 5, we describe our floorplanning prototype and present some experimental results. 2 Congestion Model In Figure 1, consider a route from point A at (0, 0) to point B at (m, n). For simplicity, assume there is no routing obstacle between A and B. At each grid point, the route can either go horizontally or vertically. The shortest distance between A and B is m+n, which is called the Manhattan distance. If the routing is limited to the Manhattan distance, there are m+nCm different ways to route from A to B. The combination is derived from the fact that m tracks out of the m+n tracks are horizontal. As shown in Figure 1(a), there are 5 C2 or 10 different ways to route from A to B for m = 3 and n = 2. (a)
(b)
Figure 1: Routing between A(0,0) and B(3,2)
2.1 Routing Probabilities and Routing Densities ′ Let Pxy be the routing probability that the route passes through the horizontal track from (x, y) to (x+1, y) and Pxy′′ be the routing probability that the route passes through the vertical track from (x, y) to (x, y+1). There are x+yCx different routes from (0, 0) to (x, y), m-x-1+n-yCn-y different routes from (x+1, y) to (m, n), and m-x+n-y-1Cn-y-1 different routes from (x, y+1) to (m, n). Assume that all routes are equally probable. Thus, we derive the following equations. Pxy′ =
( x + y C x ) ⋅ (m − x −1+ n − y Cn − y ) ;
Pxy′′ =
m + n Cn
( x + y C x ) ⋅ (m − x + n − y −1Cn − y −1 ) m + n Cn
(1)
For example in Figure 1, 6 out of 10 possible routes pass through the horizontal track from (0, 0) to (1, 0). Thus, P00′ is equal to 0.6 and P00′′ is equal to 0.4. The routing probabilities of all the horizontal and vertical tracks are shown in Figure 1(b). Suppose M wires are connected between A and B. The routing densities are the products of the number of wires and the routing probabilities. Let DH (x,y), DV (x,y) be the horizontal and vertical routing densities at (x, y). Hence, we get the following equations. DH ( x, y ) = M ⋅ Pxy′ ; DV ( x, y ) = M ⋅ Pxy′′
(2)
2.2 Some Important Features of the Congestion Model The stochastic congestion model is described in [5] in detail. This model supports via minimization, routing obstacles, multi-pin nets, and routing among macro blocks. It is important to consider via minimization because many routers minimize the number of vias [4]. In general, vias are difficult to fabricate, occupy much space, and can cause substantial interconnect delay. In Figure 1, there are ten possible ways to route from (0, 0) to (3, 2), but most routers today only select the routes with one bend (via). Consequently, ignoring via minimization gives an incorrect estimate of congestion. Similarly, some areas in a chip may be reserved for local routing and cannot be used for global routing, and it is crucial to support routing obstacles in the congestion model. 3 Delay and Power Optimization The stochastic congestion model has several important applications. The model can be used to identify congestion hot spots, and can also be served as a cost function in global and detailed routings. In this section, we describe how to utilize the congestion model to calculate the objective function in the floorplanning stage. The delay between two successive logic stages consists of three components [1]: (a) intrinsic delay of the logic cell, (b) delays to charge up the load capacitance, and (c) interconnect delay. Among the three components, only the last component depends on the interconnect routing. The interconnect delay is proportional to the total interconnect capacitance. W
S
W
S
C20
W
C21
T H
C1 GROUND PLANE
Figure 2: Wiring Capacitances
Most timing driven placement and routing algorithms optimize either the total wire length or the wire length of the critical path [2]. However, the wire capacitance depends on not only the total wire length but also the spacing between adjacent wires. In Figure 2, C1 represents the line-to-ground capacitance, whereas C20 and C21 represent the cross capacitances. Based on Sakurai’s formulas [9], we can derive the following relationship −1.34
S (3) C1 ∝ L ; C20 = C21 ∝ H Assume that the interconnect spacing S is adjusted according to the wire congestion. As defined in Equations (2), DH (m,n) and DV (m,n) are the horizontal and vertical wiring densities. The line-to-ground capacitance C1 is proportional to the total wire length L. On the other hand, L is equal to the sum of all the horizontal and vertical wire segments at all grid points, which in turn is proportional to the sum of routing densities. The total cross capacitance Cc is equal to the sum of C20 and C21, and is therefore proportional to both L and S -1.34. Hence, we get the following equations. C1 ∝ ∑ [DH (m, n) + DV (m, n)] ; m, n
[
Cc ∝ ∑ DH (m, n) 2.34 + DV (m, n) 2.34 m, n
]
(4)
An objective function ΦP to optimize the total delay is shown in Equation (5). In this equation, Area corresponds to the area of the bounding box containing the floorplan. The area is included in the objective function to reduce the layout size. The parameters λ0 and λ1 are used to configure the relative importance of C1 (line-to-ground capacitance) and Cc (cross capacitance). If this objective function is used to minimize power minimization, the number of wires in each net has to be multiplied by the activity factor of the net. = Area ⋅ C1λ ⋅ Cc λ 0
P
1
(5)
4 Implementation and Results The floorplanning prototype was based on sequence-pair structure [7] and uses simulated annealing technique to search for optimal solution. Initially, a sequence pair is created at random. At each simulated annealing step, the algorithm considers one of the following three perturbations: rotation of a random block, "half exchange," or "full exchange" sequence pair move operations [7]. The objective function is defined in Equation (5). The optimizer was implemented in C programming language, and tested with MCNC [11] building block benchmarks (see Table 1). In our experiment, all the modules are hard modules which means that the dimensions of each block are fixed and inflexible. For simplicity, all terminals are assumed to be located at the centers of the blocks. The benchmarks were tested with three different sets of λ0 and λ1. In the first test, λ0 = λ1 = 0 and we only optimize for the total floorplan area. In the second test, λ0 = 1 and λ1 = 0 and we optimize for both area and wire length. In the third test, λ0 = λ1 = 1 and we optimize for area, wire length, and cross capacitance. apte xerox hp ami33 ami49 No. of blocks 9 10 11 33 49 No. of nets 97 203 83 123 408 Table 1: MCNC Building Block Benchmarks The results of the MCNC benchmarks are shown in Table 2. The wire length and cross capacitance estimates are based on Equations (4). In order to compare the results among the different tests, all the results are shown in relative percentages with respect to the first test. The MCNC benchmark results show that area can be used to tradeoff the total power consumption.
Figure 3 shows the floorplan results for ami49. In this example, the total wire length can be reduced by 53% and the cross capacitance can be reduced by 69% by paying 9% penalty in the total area. This is desirable in many applications in order to reduce crosstalks, improve signal integrity, and reduce interconnect delay and power consumption. Optimization Functions Area only
Area + wire length Area + wire length + cross cap.
MCNC Benchmarks Results apte xerox hp ami33 Area 100% 100% 100% 100% Wire length 100% 100% 100% 100% Cross cap. 100% 100% 100% 100% Area 106% 106% 108% 102% Wire length 64% 56% 34% 71% Cross cap. 50% 48% 18% 67% Area 106% 102% 114% 104% Wire length 67% 60% 40% 76% Cross cap. 37% 31% 12% 61% Table 2: MCNC Benchmark Results
(a) λ0 = 0 and λ1 = 0
ami49 100% 100% 100% 103% 59% 53% 109% 47% 31%
(b) λ0 = 1 and λ1 = 0 (c) λ0 = 1 and λ1 = 1 Figure 3: Floorplan Results for ami49
5 Conclusions This paper presents a new floorplanning algorithm that takes both wire length and wire congestion in consideration. Using MCNC test cases as our benchmark, the new algorithm can effectively reduce both wire length and cross capacitance, which are crucial in deep submicron designs. By paying a relatively small penalty in die area, chip performance and power consumption can be drastically improved. References [1]
[2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
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