Assertion-Based Verification of Industrial WLAN System

Assertion-Based Verification of Industrial WLAN System Yuhei

Infall Syafalni† , Nico Surantha‡, Duc Khai Lam‡, Nana Sutisna‡, Katsuhiko Wakasugi†, Yang Tong Xin† , Hiroshi Ochi‡ , and Taadaki Tsuchiya†

Nagao‡,

† Logic

‡ Kyushu

Research Co. Ltd., Japan, Email: {infall, wakasugi, yang, tsuchiya}@logic-research.co.jp Institute of Technology, Japan, Email: {nico, khai, nana, nagao, ochi}@dsp.cse.kyutech.ac.jp

Abstract—For the last decades, the advancement of system on chips complexity and size are driving the verification process of the digital designs to be much more complicated and time consuming. Moreover, nowadays, the verification process takes up to 80% of overall design development time. This paper emphasizes the importance of automatic testbench generator for industrial wireless local area network (iWLAN) for factory automation system (FA). The proposed generated testbench is written in SystemVerilog to represent the functions and to reduce the code size compared to traditional Verilog testbench. It is also supported by assertion-based method to simplify the code and to improve the observability in SoC verification. Experimental results show that our proposed method produces smaller code size and can improve the efficiency of the verification of SoC designs. Moreover, we shows the verified iWLAN system data transfer.

I. I NTRODUCTION As the rapid increasing of the demand of communication devices, system on chip (SoC) development has become one of central attention of researchers and engineers in universities and industries [1]. The advancements of system on chips complexity and size are driving the verification process of the digital designs to be much more complicated and time consuming due to the huge amount of components and scenarios in the components. Nowadays, verification process takes up to 80% of design development time [2]. Thus, an efficient methodology is necessary to help engineers in facing this heavy challenge in integrated circuit fields. Driver

Design Under Test

Response

Assertion-Based Verification

Scoreboard

Fig. 1: Assertion-Based Verification One of powerful methodology in verification is assertionbased verification. SystemVerilog assertions have been used since their featuring in the hardware verification language (HVL) in 2005. Moreover, engineers also suggested the assertion method for all aspect of chip productions [3]. Fig. 1 shows the assertion-based verification methodology. The driver initiates the signals to the design under test (DUT) module. Then, the response module gives feedbacks to the DUT. The outcomes of driver and response modules are analyzed by putting assertions. Finally, the verification performance is evaluated by scoreboard.

There are some of related works in verification of SoC [4]– [6]. In the recent trend of electronics production flow, hardware automatic emulation can be a solution for the growth of the complexity of SoC. The major industries of EDA e.g., Cadence, Synopsys, and Mentor Graphics, have provided such emulator and register-transfer level (RTL) code generations to speed up the time-to-market factor in IC productions. One of the luxury hardware emulation and code generators of SoC development is provided by DesignWare Synopsys [7]. However, the validation environment of these products yet requires high efforts and high costs. In [4], a verification platform is proposed to improve efficiency of SoC HW/SW verification and validation. In this work, the proposal is about the separation of IC design processes that consists of RTL-FPGA, SystemC-FPGA, and in-circuit verification. The separation is expected to ease the verification phase. In another work [6], an automatic testbench generator for SystemC is proposed. In this work, SystemC verification library is used to synthesize the generated testbench. In [5], a checker for AMBA AHB is proposed using classified rules of the IP. However, these methods have lack of flexibility in handling the changes of specification and fast prototyping for the SoC designers and take relatively high costs. In this paper, we propose a novel methodology for industrial WLAN (iWLAN) verification. The key contributions of this work are resumed as follows: 1) An automatic generation of testbench for SoC is addressed, that improves the efficiency of the verification process. 2) SystemVerilog is utilized for reducing the code size of the generated testbench. 3) An assertion-based coding is used, thus it improves the observability and reduces the code size of the testbench. 4) Verification of iWLAN system is shown. The contributions of this work are expected to significantly improve the efficiency of the verification process, and to reduce the time-to-market. This paper is organized as follows: Section II explains the iWLAN system; Section III explains the proposed method: assertion-based testbench generator for SoC; Section IV shows the results; and Section V concludes the paper. II. I NDUSTRIAL WLAN S YSTEM In this section, we explain about industrial wireless application (iWLAN) for factor automation (FA) system. In the recent years, wireless technology has emerged as a prospective alternative to ethernet technology as a transmission medium for factory automation system. The wireless technology promises time and money saving during installation and maintenance. It is also more reliable in mobile scenarios, where the cable

connectivity usually becomes the source of problem. Moreover, the IEEE 802.11 WLAN technology is one of the wireless technology that is potential for factory automation application due to its high data-rate [8] and adequate transmission range for indoor application. Fig. 2 shows our consideration of iWLAN system used for controlling industrial robots (iRBs). Master (MS) CPUs Bus & Peripherals MAC PHY RF

Access (PDMA) transmission. There are still many features from WLAN, e.g., multiple access techniques, transmission protocol, etc, that can be exploited to improve the performance of system. Therefore, the modification and improvement of SoC design will happen very often in the future. In that sense, the automatic testbench generator is very important to enable fast prototyping of the improved design. Considering the large scale design of iWLAN system, the efficiency of the verification platform is also very important. In this paper, we propose the verification platform that can satisfy the above requirement. III. A SSERTION -BASED T ESTBENCH G ENERATOR This section describes the proposed method; an assertionbased testbench generator for SoC, especially for iWLAN.

MAC-PHY

RF

RF

RF

MAC-PHY

iRB 1

iRB 2

MAC-PHY

...

iRB 3

MAC-PHY

RF

iRB N

Fig. 2: iWLAN System The system design of the SoC of iWLAN is illustrated by Fig. 3. It contains two CPUs, an advanced high-performance bus (AHB) of advanced microcontroller bus architecture (AMBA) [9], an ethernet, a SDIO, a DMA and a WLAN modules. Two CPUs and DMA are aimed to speed up the performance of the system by distributing the tasks in the system e.g., a CPU for peripheral transfers data and the another one for WLAN operation.

SPECIFICATION

Master 1

GENERATE TESTBENCH (SYSTEM VERILOG)

CPU 1

Master 2

CONNECT INSTANCE

MODIFY TESTBENCH

Advanced high-performance bus (AMBA AHB 2.0) FIT?

RTL DEBUG

Ethernet

SDIO

DMA

VALIDATION

Master m-1

Master m

Advanced high-performance bus (AMBA AHB 2.0)

CPU 0

A. Verification Methodology In this subsection, we show the proposed methodology in verifying a SoC design. Fig. 4(a) shows the flowchart of the methodology. First, specification is decided by the costumer. In this phase, some parameters of the SoC are decided such as the number of masters, the number of slaves, bus width, address map of the slaves and priority of the masters. Next, we enter the specification parameters to the testbench generator and generate the testbench within a second. After that, we modify the code according to the design and we debug and validate the design.

Slave 1

Slave 2

Slave s-1

Slave s

WLAN PASS?

Fig. 3: System Design of iWLAN Let the system clock frequency be fsys . The estimation of transfer time from a master to the stations (iRBs) is Ttr = ntr × (cs + cb nb )/fsys , where ntr is the number of transfers to the iRBs, cs is the synchronization cycles between the transfers, cb is the burst cycles and nb is the number of bursts. For instance, we have the system clock frequency of 160MHz, the number of transfers is ntr = 4 for 4 iRBs. In each transition, it requires cs = 8 cycles, while the number of burst is nb = 1 and the burst cycles is cb = 4 e.g., 4 words wrap operation. Thus, we have Ttr = 4(8+ 4)/(160 × 106 ) = 0.3µs. In verification, the estimation time is useful for detecting run-time misbehaviors e.g., a deadlock. In [10], we have proposed the fast and safety industrial wireless communication system based on WLAN standard. Our proposal is an advanced round-robin protocol for iWLAN system that improves the transmission throughput significantly due to its ability to utilize multi-user Packet Division Multiple

FINISH

(a) Flowchart

Generated Testbench

(b) Testbench Covering

Fig. 4: Proposed Testbench Generator Fig. 4(b) illustrates the generated testbench that covers all of the IPs on the SoC. In this case, we choose advanced microcontroller bus architecture (AMBA), since it is the most prominent bus architecture produced in the electronics market. One of protocol in AMBA is advanced high-performance bus (AHB) as shown in 4(b). The generated testbench simulates and tests the design by randomization. The random factors are masters orders, selected slaves, burst type, and write/read mode. B. Generator Map Fig. 5 shows the generator map of the proposed method. The generator has several main modules. The first one is interface package which defines the master and the slave interfaces. The strength of this feature is a simplification of instance declarations that removes the redundant codes.

The second module is the threads generation module which consists of masters and slaves generations, masters and slaves initialization, and test patterns generations. In test patterns generations, we use randomization to save time and to achieve the best coverage of the verification. And, the third module is the capture signals which consists of wire generation for verification monitor, scoreboard class, definitions, and functions as well as the routine for the scoreboard. Testbench Generator

Testbench Module Generator

Interfaces Package Build Master Interfaces

Capture Signals

Threads Generation Master & Slave BFM Generation

Specification Data Build Slave Interfaces

Master & Slave Initialization

Threads Generation for SoC Verification

Scoreboard Class and Declarations

Wire Generation for Verification Monitor

where IDLE indicates the bus is not used and BUSY indicates the bus is being used by the operating slave. Finally, we compare the data, when the slave has given the feedback by sending the waitresp signal. D. System Verification We use the verification platform to verify system-IPs. Fig. 6 shows the illustration of an IP verification using the generated testbench and the scoreboard. Moreover, we also use memory to store the early output data from the bus directed to the IP. With this platform, improvement of efficiency in verification of IPs in the SoC can be achieved.

Scoreboard Routine Generator

Scoreboard

Fig. 5: Generator Map C. Assertion Techniques Some assertion techniques are used to optimize and reduce the code size of the generated testbench such as property assertions and sequence assertions. First, let us define αp as a property assertion function. As in AMBA-AHB protocol [9], every master has a grant signal that indicates the corresponding master already allowed to use the bus. However, the grant signal still cannot use the bus if the ready signal of the bus is not active. Thus, we have the wait grant assertion as waitgrant : αp (grant ∧ ready).

Similarly, after the master sends data to a slave, the slave will send back a response that is indicated by OKAY status and the ready signal received by the master. Thus, we have the wait response assertion as waitresp : αp (resp == OKAY ∧ ready).

Next, let us define αs as a sequence assertion function. we use sequence assertions for burst transfer validation. The burst transfer validation is represented as checkburst : αs (c < bs ∧ w[0 : bs − 1])

where αs is the sequence assertion function, c is the counter, bs is the burst size, and w is the signal of address validation for bs clocks, starting from c = 0. It shows 1 for correct address and 0 for wrong address. For instance, the address validation for wrap mode is ! adr − (2 h × (c − 1 )) if c == bs /2 adr = otherwise, adr + 2 h where adr is the address bus, c is the counter, bs is the burst size, and h is the bit width decoder. h is 0, 1 or 2, when 8, 16 or 32 bits of data bus are used, respectively. Moreover, we use assertion property to indicates the capture and compare data in scoreboard class. The scoreboard consists of SystemVerilog class and mailbox [2] that stores the expected values. Here, we define the capture data assertion as capturedata : αp (trans ̸= IDLE ∧ trans ̸= BUSY ∧ ready),

Code Size

Master BFM

Advanced high-performance bus (AMBA AHB 2.0)

Integrated IP

Memory

(#Masters, #Slaves)

Fig. 6: AHB-IP Verification

Fig. 7: Code Sizes

IV. R ESULTS In this section, we evaluate our proposed method. Firstly, we compare our proposed method with the existing methods related to the verification of SoC. Then, we evaluate our testbench by conducting code-size comparison of the testbench. In this case, we perform the bus matrix of iWLAN that utilizes AMBA 2.0 AHB bus. Finally, we verify the iWLAN system by performing uplink-downlink transfer simulations. A. Comparison with Related Methods Table I shows the comparison of verification features with other methods. In [4], system partitions are proposed for HW/SW system by using SystemC-RTL languages. In [5], rules checker is proposed for protocol verification in SoC bus. In contrast, our purposed method has automatic generation testbench feature that eases the designers on designing and updating the circuit quickly. Moreover, we use assertion-based verification (ABV) method to check the behavior of the design and to simplify or to reduce the size of the testbench. TABLE I: Comparison to other methods Ref Method Target Lang. Auto. Gen. ABV [4] Partitions HW/SW SystemC-HDL × × [5] Rules HW HDL × × √ √ Ours Scoreboard HW HDL-SVA

B. Code-Size Comparison First, we generated testbenches using Verilog (V), SystemVerilog without assertions (SV), and the proposed method; SystemVerilog with assertions (ASV). The testbench represents the same functions. In this case, for burst transfers, we achieved more than 90% coverage. As shown in Fig. 7, the ASV represents the smaller code size. Moreover, we use the generator that can produce the code within second.

C. Scoreboard Display Fig. 8 shows the example of scoreboard display in verifying the data transfer from masters to slaves. There are two masters with index 0 and 1, transferring the 32 bits data to slave 5. Status 1 means the data sent and the data received have been validated and are correct, while status 0 is vice-versa.

analog RF part of the MAC layer will be implemented on RF daughterboard. Furthermore, the motherboard can support many SoC peripheral configuration through the built-in peripheral or extension daughter board, e.g., I2C, SPI, UART, Ethernet, USB, DDR3 memory, flash memory, etc.

Fig. 8: Scoreboard Display Feature D. Verification of iWLAN System In this subsection, we present the iWLAN system protocol simulation result. Fig. 9 shows the example of communication between a master (MS) and eight industrial robots (iRB). Firstly, the MS sends a synchronization frame to all iRBs to synchronize the control duration among all iRBs. After the synchronization, MS sends data frame to iRBs 1-4 and iRBs 1-4 reply with acknowledge frame. As shown by Fig. 9, iRBs 5-8 also receive the data frame. However, after checking the destination address of the frame and understand that it does not match with their addresses, they just ignore the data frame and does not reply with acknowledge frame. Finally, MS sends data to iRBs 5-8 and iRBs 5-8 reply with acknowledge frame. This simulation result confirms that our testbench can verify the operation of hardware implementation. In the simulation results, it shows that the hardware implementation operation fulfills our expectation of the proposed transmission protocol.

Fig. 10: FPGA Implementation V. C ONCLUSION This paper have shown the importance of automatic testbench generator for SoC targeted to iWLAN system. The testbench is written in SystemVerilog to represent the functions and to reduce the code size compare to traditional verilog testbench. It is also supported by assertion-based method to improve the observability in SoC verification. Experimental results have shown that our proposed method produces smaller code size and can improve the efficiency of verification process. Moreover, we also have shown the verified iWLAN downlink and uplink data transfer simulations. For future implementation, we are going to do verification on FPGA platform. ACKNOWLEDGMENTS This work is supported by the Adaptable & Seamless Technology Transfer Program through Target-driven R&D (ASTEP) of Japan Science and Technology Agency. R EFERENCES

Fig. 9: iWLAN Uplink-Downlink Verification E. FPGA Verification Platform In order to verify the feasibility and reliability of iWLAN system design, the FPGA prototyping becomes necessary. Fig 10 shows our advanced FPGA verification platform. The motherboard contains Stratix IV 820 FPGA that can support up to 8.2 million gates of ASIC prototype [11]. Moreover, it supports full network layer design for the implementation of IEEE 802.11 WLAN standard based FA system. The MAC layer will be mainly implemented on MPU daughter board. The baseband portion of PHY layer and part of MAC layer will be implemented on main FPGA chip of motherboard, while the

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