ATPG-based preimage computation - IEEE Computer Society

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For preimage computation, even after a solution is found, we must backtrack and search for the next solution. Each decision is considered a node in the Deci-.
ATPG-BASED PREIMAGE COMPUTATION: EFFICIENT SEARCH SPACE PRUNING WITH ZBDD * Kameshwar Chandrasekar, Virginia Tech, Blacksburg, VA ([email protected]) Michael S. Hsiao, Virginia Tech, Blacksburg, VA ([email protected])

Abstract Computing iniagdpreimage is afundaniental step in fornwl verification of hardware systems. Conventional OBDD-based methods for fornial veriJication suffer from spatial explosion, since OBDDs can grow exponentially in large designs. On the other hand, SAT/ATPG based methods are less demunding on memory But the run-time can he huge for these methods, since ihey niusf explore an exponential search space. In order io reduce this reniporal explosion (f SAT/ATPG based niethods, eflcient learning techniques are needed. In this paper, we present a new ZBDD based niethod to conipactly sture and efficiently search previously explored searclz-statesfor ‘ATPGbased preimage coniputation We learn f h m these searchstates and avoid searching their subsets or supersets. Both solution and conflict subspaces are pruned based on simple set operations using ZBDDs. We integrate our techniques into an ATPG engine und denionstrate iheir efficiency on ISCAS ’89 benchmark circuits. Experiniental resulis show that signiJicant search-space pruning for preiniage coniputuiion is achieved, compared to previous method~s. I.

1 Introduction Preimage and Image computations play an important role in VLSI CAD. They are key steps in Sequential Equivalence Checking and Unbounded Model Checking. In this paper, we focus on preimage computation, which is the problem of finding the set of all the previous states that can reach a given set of target states. Symbolic methods have widely been used for preimage and image computation since they can efficiently represent the set of states and Transition Relation for Boolean manipulation. However, OBDD-based methods are limited to small and medium sized circuits due to the memory-explosion problem. Several alternative methods were explored to substitute the OBDD-based methods [1-9]. A Reduced Boolean circuit (RBC) is proposed in [l]to represent the Transition Relation and certain rules for efficient variable quantification are provided for the RBC. In [Z],the authors propose new rules to quantify Boolean Formulas represented as Boolean Expression Diagrams (BED). However, these quantification rules are applicable only for specific formula strnctures. For other formula structnres, naive quantification is performed. The length of these formulas can increase exponentially as well. ‘This research is supported in pan by NSF Grants CCR-0196470 and CCR0305881.

0-7803-8236-6/03/$17~00 0 2003 IEEE

Recently, pure SAT/ATPG based methods are gaining importance in Formal Verification. Structural information added to pure SAT based methods showed improvements for image computation in [ 5 ] . In [6,7], SAT is used as the underlying engine for preimage computation. Efficient learning techniques are proposed to speed-up the SAT solver that forms an integral part of an Unbounded Model Checking Tool. In [9], the authors compare the performance of SAT solvers with ATPG techniques for property verification. They show that ATPG based techniques outperform SAT, especially for large designs. In SAT/ATPG solvers, learning plays a very important role to prune the search space. The knowledge can be in the form of implications [lo], assertions [l I] or conflict clauses [12-14]. Efficient manipulation of knowledge is required to reduce the overhead in storing and using the knowledge base. In [15], ‘Success-driven learning’ efficiently prunes the search-space for ‘ATPG based preimage computation’ by identifying identical solution-subspaces. The Transition Relation is represented by a levelized circuit and the set of states are stored in a free BDD. An ATPG is invoked to find all the solutions, thus performing variable-quantification. After each decision, an internal cut-set of the circuit is identified as a search-state. Equivalent search-siates, which lead to the same solution subspace, are identified to prune the search-space. The Decision Tree, obtained during solution-search, is pruned and stored as a free BDD that represents the complete preimage set. As solution subspaces heavily overlap during preimage computation, considerable additional savings may be obtained in terms of time and memory by noting these overlaps. In other words, the search states no longer have to be exactly equivalent for the learning purposes. The contribution of this paper is three-fold: 1. We identify partially-equivalent seach-states as soon as possible during the search process and assign necessary additional input values to quickly reach the equivalent search-state. 2. As a dual of pruning solution subspaces, we employ search-stute conflict driven learning to prune the conflict subspaces. 3. A Novel ZBDD based method is proposed for compact storage of search-states and to manipulate them for efficient search-space pruning. Experimental results showed that significant search-space pruning for preimage computation is achieved compared to previous methods.

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The rest of the paper is organized as follows. We introduce preliminary concepts and terms in Section 2. The basic idea is explained in Section 3. An overview of our algorithm and the concepts are introduced in Section 4. Section 5 presents the experimental results and the last section concludes the paper.

context. However, please note that ZBDD nudes and Decision Tree nodes are diffelent, and should be distinguished based on the context of discussion. A few other terms used are: 1. solutiodconjlict branch - A branch in the Decision Tree that has at least-one/no solution below it. 2. soluriodconpict cut-set A cut-set for the search-state in the solutiodconjlict branch.

2 Preliminaries

~

An ATPG algorithm implicitly explores the entire search-

space to generate a solution. For preimage computation, even after a solution is found, we must backtrack and search for the next solution. Each decision is considered a node in the Decision Tree and the entire search-space is explored incrementally, to find all solutions. The internal state of the circuit, after each decision, is considered a search-state for the Decision Tree.

2.1 Cut-setfor search-state Each search-state can be uniquely represented by a cut-set of the circuit. After each decision, a multiple backtrace from the ATPG objective can identify this cut-set [lS]. Essentially, the first frontier of specified nodes encountered during backtrace is the cut-set for search-state.

3 . solutiodconjlict subspace - A search subspace below a solution /conjlict branch.

3 BasicIdea Figure 2(A) shows a portion of the Decision Tree for one of ISCAS '89 benchmark circuits obtained by a conventional PODEM algorithm [17], without leaning. The nodes represent the decisions taken by backtracing from the objective during ATPG. In the Figure 2(A), let SSx, SSa, SSz, SSy, SSb represent the cut-sets at the corresponding branches in the Decision Tree explored in the order: SSx < SSa < SSz < SSy < SSb. The solution subspaces below SSx and SSy are identical and the corresponding cutsets are equivalent. When SSy is reached, we learn that SSy SSx and link the current branch to the solution subspace of SSx [lS]. This avoids searching the same solution subspace again. It is seen that, although we are on a path to an equivalent search-state, we have to wait for an exact equivalence. However, it is possible to identify partially equivalent cut-sefs and justify the remaining gates to obtain an exact equivalence, based on the following observation. Consider SSz as the current cut-set. It may be seen that SSz is a subset of SSx. The decisions made in between SSz and SSy justify the gates in the difference of cut-sets (SSx - SSz) i.e. {g5 = O,g6 = 0) justify {g5 = 0,glO = 0). In Figure 2(B), it is observed in the circuit that the inputs in the difference of cones (Cone9Sx - ConeSSz) can justify the gates in the differenceof cut-sets (SSx SSz). When SSz is reached, we can assign multiple-inputs (x5=0, x6=0) to obtain an equivalent cut-set, SSx.By forcing multiple input assignments, the ATPG also makes use of previously encountered solution subspaces. A path to equivalent solution cut-sets in the Decision Tree is identified earlier. Multiple-input assignment reduces the iterations for backtrace(J [17] in ATPG. This effectively speeds up preimage computation. It should be noted that we learn for a specific assignment of the multiple-inputs. The other branches of the multiple-inputs, i.e. 95 = l , g 6 = 1, still need to be searched for potential solutions in order to maintain the completeness of the approach. We call this approach, augmented success-driven learning. Since only solution subspaces were targeted in [lS], we would like to extend our method to tackle conjict subspaces as well. As a dual of pruning solution subspaces, the cut-sets in the conflict branches of the decision tree can be similarly stored to prune the conflict subspaces. Figure 2(A) shows that the subspace below SSa is a conflict subspace. In the corresponding circuit in Figure 2(C), it can be argued that all possible input assignments, after cut-set SSa is reached, will lead to a conflict. When an equivalent or a superset of the cut-set

=

( A p a r c h State Rspre~sntauve

( 0 )DeclslOn Tree

IC)ZBDD

Figure 1. Cut sets in the search-space For a circuit in Figure 1(A), a Decision Tree is shown in Figure KB). The sets along the branches (eg. {g} and {g, f,6} are cut-sets for the corresponding search-states. For last branch (b=O), cut-set {g, f,6} is denoted by dotted line in Figure l(A). It may be noted that equivalent cut-sets will always lead to the same search subspace in the Decision Tree.

2.2 Set Manipulation using ZBDD ZBDDs were introduced in [16] to efficiently represent sets, as well as for performing set operations. A I-edge from a node denotes the presence of the element in the set and a 0-edge denotes its absence. The number of paths from the root to TERMINAL-1 denotes the number of sets stored in the ZBDD. A set can be added to the ZBDD by a simple union operation based on the algorithm presented in [16]. The reader is referred to [16] for a detailed introduction to ZBDD. In [16], it is emphasized that ZBDDs are suitable to store sparse combinations of elements in a set. Since the cut-sets represent sparse combinations of different gates in the circuit, we use ZBDDs to store the cut-sets, as shown in Figure 1(C). Set operations are performed on ZBDDs to prune the search-space. A node in the ZBDD represents an element in the cut-set. Because each cut-set is made of circuit node values, each element is also a gate in the circuit. These terms are used interchangeably in this paper, when the meaning is clear from the

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-

h

A

conflict subspace

-

current cutset

0solution subspace __.._ stored cutset

I

I

(6) Circuit: SSx is superset of SSy

.......'.

I I (C) Circuil: SSa is subset of SSb

(A) Partial Decision Tree

Figure 2. RelationshipAmong Cut Sets is encountered, we can backtrack. The search-subspace below the superset branch is guaranteed to be a conflict subspace. For instance, it can be verified in the Decision Tree that SSb is a superset of SSa and leads to a conflict subspace. Considering SSb as the current cut-set, we learn that a subset of the current cut-set, SSa, previously lead to a conflict. This approach helps to identify conflict subspaces earlier and prune them, which reduces the number of backtracks in ATPG. We call this approach, search-state bused conjict-driven learning. In the previous work [15], hash-tables were used to index and find equivalent solution search-states. However, they are not suitable to identify subsets and supersets. In our approach, ZBDDs are used as they allow for compact storage of cut-sets and for efficient identificationof subsets and supersets. We call this approach Search Stare Doniinance analysis. The theory of Search State Dominance has been proposed in 1181. However, their algorithm is not suitable for identifying subsets and supersets since Hash-tables cannot be used for this particular purpose. Other differences include:

in the ZBDD corresponds to a cut-set. Two distinct features of our contribution are in Step 2. In Step 2a, we search the conflict-ZBDD database for equivalent or subset of current search-state. Likewise, Step 2b searches the solution-ZBDD database for equivalent or superset of current search-state. unction . OreimaeeO [. I/ step I. T-nal Conditions if (cbjecIivesatisfied0) ( u&te_salution BUDO:

updare_solution_BDD(); update_success_cwnterO: return:) I/ step 3. gel new decision node decisionpode = baekmccO:

preimageo; /I step 4. explore other branch

flip_decision(decisiood~);

preimage0; //step 5. store seareh ~tate > 0) if (s"eeess~co""le~)

updak_rZBDDO:

1. In [IS], the theory to learn from solution subspace is presented only for sensirizedfaults. 2. We show that the order of input-assignment affects the performance of ATPG, which is not relevant in [IS].

i", rnin_ga,e_te1ow:

)ZBUD_CNODE: 1B) C o d i c l ZBUD Node

3. We use a ZBDD based method to manipulate the cut-sets.

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Figure 3. Overall Algorithm

4 The Algorithm The basic idea is incorporated into a PODEM algorithm [I71 as shown in Figure 3(A). Cutsets in the solution branches are stored in a solution-ZBDD (sZBDD) and those in the conflict branches are stored in a conflict-ZBDD (cZBDD). Each ZBDD node represents an element in a cut-set and each path

-

4.1 ZBDD conflict cut-sets A conflict ZBDD node is defined, as shown in Figure 3(B). The first member in the node refers to a gate in the cut-set. The

second and the thud members are links to the two children of the node. The last member identifies the 'minimum number

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of included nodes' below that node, of all paths that lead to TERMWAL-1 in the ZBDD. Each conflict cut-set is added to the ZBDD by a simple union operation as proposed in [161. We propose a simple traversal algorithm, as shown in Figure 4, to determine if a subset exists or not. The members of ZBDD nodes and current cut-set facilitate early identification of the subset. The following facts are incorporated in the algorithm to identify a subset: The ZBDD is ordered and we can search for the elements in the cut-set one by one via traversal.

If a node does not exist in the current cut-set, only the 0branch of the node needs to be searched. If a node exists in the current cut-set, both branches of the node needs to be traversed. The 1-branch of the node is traversed first. If we reach TERMlNAL-1 during traversal, it means that a subset exists and we return SUCCESS. If the 'minimum number of specified nodes' below the current node is greater than the remaining elements in the current cut-set, no subset exists below the current node. This helps to avoid a large number of cut-sets.

4.3 Multiple Input Assignment When a superset of the current cut-set exists in the solutionZBDD, searchsZBDD() traverses the smallest possible superset and returns the link to the solution subspace. The inputs required to justify the gates in the difference of cut-sets need to be identified. We know that the superset is justified by the decisions above the corresponding search-space in the Decision Tree. An upward traversal in the Decision Tree can identify these inputs. However, some of these inputs lie inside the cutset cone of the current branch. These inputs are blocked by the current cut-set and may potentially justify a few gates in the current cut-set. It was shown in Section 2.1 that cut-sets are identified using a multiple backtrace from the objective. Simultaneously, the unassigned inputs outside the cut-set cone are marked in the circuit. During upward traversal, only the marked inputs are chosen for multiple-assignment. These inputs justify the gates in the difference of two cnt-sets and lead to the equivalent search-state. The chosen inputs lie in the difference of the two cutset-cones. For the situation in Figure 2, multiple-inputs are chosen as follows: Current Cutset: SSz Marked inputs: search-sZBDDO:

'The ZBDD and the c ~ t s c are t in the Same order 'cs - cutset unction subSetExists-in_cZBDD(cun-cs)( cs&d=0, num-csNodes=length(curr_cs); 11 step 1. Discard unnecessary gates while (currcs[++c-ind] < rmt->gate-id);

Upward Traversal from SSx: 7, 2. 6, 5, 3 Multiple inputs: 5, 6

Order of Multiple-input assignment For Multiple-Input Assignment in Figure 2(A) at SSz, (xS=O and x6=0) need to be assigned. Figure 5 shows the Decision Tree fragments for the two possible assignment-orders. It is seen that the number of backtracks and number of nodes depend on the order of input assignments. This is analogous to the size of a BDD depending on the order of its variables. In most cases, multiple input-assignment in the same order as before gives good results, since it was previously determined by PODEM. 4.4

// step 2. Search the ZBDD

return (search-cZBDD(mr. cs-ind));) unction search-cZBDD(cun_ncde. cs-ind) ( /I step 1. Terminal conditions return tme: if (cun-ode ='EFMINAL-I) refurn false; if (cum-node =TERMINAL-0) if (cun-node->min~ates-~low > num-csNodes-cs-ind) return false; /I step 2. Traversal for subset if (cur-node->gate-id =currcs[csindl)( 11 This node exists in the cutset temp-in&s_ind; temp-~~t=cun_node->highNodePU; while (cun-cs[++cs-ind] < temp-rmt->gate_id); if (search-cZBDD(temp_root, cs-ind)) return m e ; cs-ind=temp-ind; temp_rmtswT_node->lowNodePtr; while (curr-cs[++cs-indl< temp_mt->gateid); if (searchrZBDD(temp-mL cs-ind)) return m e ; cs-ind = temp-ind; )else I/ This node is absent in the cutset return (searchrZBDD(curr_no->lowNodePrr, cs-ind)), 1

Figure 5. Order of Multiple-Input Assignment

Figure 4. Search conflict-ZBDD database

-

... 5 , 6 ... SSx is a superset

4.5

4.2 MT-ZBDD solution cut-sets The solution cut-sets are stored in a Multi-Terminal ZBDD. The l i s to the solution subspaces are stored as the Terminal Nodes. The solution ZBDD-node is similar to conflict-ZBDD node, except for the last member. It indicates the 'maximum number of included nodes' below that node, of all paths that lead to a NON-ZERO terminal. A traversal algorithm is used to find supersets, which is dual to that of conflict-ZBDD.

Choice of Parents The Decision Tree becomes a Directed Acyclic Graph (DAG) due to sharing of equivalent solution subspaces. All parents of a node that share the same solution subspace have equivalent cut-sets. During upward traversal of the Decision Tree, we can traverse any one of the parents, to find multiple inputs. It is sufficient to store any one parent in each node. On the other hand, it is desirable to choose a parent that leads to fewer number of input assignments during upward traversal. This will help to reach the equivalent search-state faster than

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Success-Driven [ 151 #'solutions #backtracks time($ 37K 1.90 5l3M 204 43 0.05 1IO 0.08 5 38K 2.70 96K Abolr 1M 94.68

ckt s1423 s1488

SI494 s5378 s9234

Note:

80

0.04

77K None

1.2K

0.13

580

0.16

tium 4 PC with 512MB RAM,running the Linux Operating System. We conducted a set of experiments to compute I-cycle preimages, for random sets of target states (conjectures of 10 to 15 flip-flops) of ISCAS benchmark circuits. We compare the results of our (augmented success + conflict driven) learning with success-driven learning alone. Both the techniques were integrated into a PODEM based ATPG engine. A backtrack limit of 1,000,000was set for both ATPG engines.

ssc

SSb

r l Figure 6. Choice of Parents Consider the Decision Tree in Figure 6. Let the searchstates SSa, SSb, SSc be explored in the order SSc < SSb < SSa and SSb 5 SSc. Our current state is at SSa and we obtained a superset match with SSb and SSc. It is seen that S S a has more Decision Tree nodes in common with SSb than SSc. If we choose SSh over SSc, then only a few inputs need to he assigned, since a major upper part of the Decision Tree is common for SSb and SSa. Since this situation is more likely to occur, we store only the recent parent in the each Decision Tree Node for upward traversal.

5

5

As the representation of all solutions is not unique, different ATPG heurisrics mqv xsult in different solution cubes

any other parent. In the current branch, the most recent parent of the solution subspace is most likely to have maximum nnmber of decisions common with the current search-state, due to the nature of branching. Consequently, this may lead to a minimal number of ntulriple-inputs during upward-traversal. Based on this fact, only the most recent parent is stored in each of the Decision Tree nodes.

P$

44

Ours #backtracks time(s) 0.42 7.7K 154 0.02

#solutions 494M

Experimental Results

The above techniques were implemented in 6000 lines of C++ code. Experiments were conducted on a 1.8 GHz Pen-

The experimental results for a number of large ISCAS 89 benchmark circuits are reported in Table 1. For each circuit, the total number of solutions, backtracks, and execution time for success-driven learning alone are reported in columns 2-5. Columns 6-8 report the same statistics by our proposed technique. Note that since the representation for the set of all solutions is not unique, different ATPG techniques can result in different number of solutions, as shown in the table. A significant improvement in time is observed for the target states in circuits - ~5378,~9234,~15850.1and ~38417.For the targets in s9234 and ~38417,our technique quickly identifies that no preimage states exist in 0.16s and 0.56s. With success-driven leaming, the ATPG engine aborts after 94.68s for s9234 and takes 48.54s for ~38417.The significance of our technique to prune the search space is demonstrated by the reductions in backtracks from > l M to only 580 for s9234 and 26K to 141 for ~38417.The significant improvement in this case is due to the pruning of the conflict subspaces in the search-space. For circuits s5378 and ~15850.1 the complete preimage set is identified by both the techniques. However, the number of backtracks is reduced from 38K to 1.2K and 71.5K to 2.5K. The reduction in the number of backtracks also results in corresponding reductions in the time taken to compute the complete preimage set. However, it may be noted that the number of backtracks may occasionally be increased in our technique due to the inappropriate order of multiple-input assignment. This is seen in the target state for circuits 15850. However the increase is insignificant as compared to the total number of backtracks. We further conducted a set of experiments for ten random targets of ~5378.The results are reported in Table 2. We can

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II

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Success-Driven [15]

ours

heuristics mny result in different solution cubes observe that our technique computes the preimage faster and achieves significant search-space pruning for target state sets 3, 8,9 and 10. For a few targets, the stored search-states were not useful during the search and hence no search-space pruning was possible. However, the overhead in using the proposed techniques was generally low, as evidenced in target state 5. The order of multiple-input assignment can affect the perfor-

mance of the proposed technique, where an increased number of backtracks may result, as explained in Section 4.4.

6 Conclusion We presented an efficient ZBDD based method to prune the search-space for ATF’G-based preimage computation. Both solution and conflict search-states are stored in a ZBDD, and an efficient algorithm is presented to identify a conjicr subser or solution superser for a current search-state. Because many

151 A. Gupta, A. Gupta, 2. Yang and P. Ashar, “Dynamic Detection

and Removal of Inactive Clauses in SAT with Application in Image Computation”, Pmc. DAC, 2001, pp. 536541. [6] K.L. McMillan, “Applying SAT methods in unbounded symbolic model checking”, Proc. CAV, 2002, pp. 250-264. [7] H.J. Kang, I.C. Park, ”SAT-Based Unbounded Symbolic Model Checking”, Pmc. DAC, 2003, pp. 840-843. 181 G. Partbasarathy, C. Huang and K. T. Cheng, “An Analysis of ATPG and SAT algorithms for Formal Verification”, Proc. H L D U , 2001, pp. 177-182 191 D. G.Saab, J. A. Abraham, V. M. Vedula, “Formal Verification Using Bounded Model Checking: SAT Versus Sequential ATPG Engines”, Proc. V U 1Design, 2003, pp. 243-248. [IO] M. H. Schulz, E. Trischler and T. M. Sarfert, “SOCRATES: A Highly Efficient Automatic Test Pattern Generation System”, IEEE Trans. CAD, Vo1.7, No.1, 1988. pp. 126-137. [ I I] I. P. Marques-Silva and K. A. Sakallah, “Dynamic Search-Space Pruning Techniques in Path Sensitization”, Pmc. DAC, 1994, pp.

solutions overlap in the solution-space, the proposed method

quickly identifies potential solution subspacesby searching for supersets in the solution ZBDD.As a dual, conflict subsets are identified to quickly backtrack from conflict subspaces. Experimental results demonstrate that the proposed method can significantly reduce the number of backtracks and speed up preimage computation. To extend this work, an intelligent way to identify useful search-states before-hand could improve the performance of ATPG. T h i s will reduce the time spent and memory used for irrelevant cut-sets and will lead to better search-state based learning.

705-711.

[ 121 I. P. Marques-Silva and K. A. Sakallah, “GRASP: A Search Algorithm for Propositional Satisfiability”, IEEE Trans. Computers, Vol. 48, No. 5, 1999, pp. 506-521. 1131 L. Zhang, C. E Madigan, M. H. Moskewicz and S. Malik, “Effi-

cient Conflict Driven Learning in a Boolean Satisfiability Solver”, Proc. ICCAD, 2001, pp. 279-285.

1141 C. Wang, S.M.Reddy, I. Pomeranz, L. Xiang and J. Rajski, “Conflict driven techniques for improving deterministic test pattern generation”, Proc. ICCAD, 2002, pp. 87-93. [IS] S. Sheng and M. S. Hsiao, “Efficient PreImage Comp. Using a Novel Success-DrivenATPG”, Proc. DATE 2003, pp. 822-827. [I61 S. Minato, ‘‘Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems”, Proc. DAC, 1993, pp. 272-277. References I171 M. Abramovici, M. A. Breuer and A. D. Friedman. “Digital Systems Testing and Testable Design”, IEEE Press, NI, 1990. 111 P. A. Abdulla. P. Bjesse and N. €en, “Symbolic Reachability Analysis based on SAT-Solvers ”, Proc. TACAS, 2000, pp. 41 1- 1181 T. Fujino and H. Fujiwara, “An Efficient Test Generation Algorithm Based on Search StateDominance”, Fault Tolerant Comput425. ing, 1992, pp. 246-253. 121 P. F. Williams, A. Biere, E.M. Clarke and A. Gupta, ‘Combin1191 I. Hamzaoglu and I. H. Patel, “New Techniques for Determinising Decision Diagramsand procedures for Symbolic tic Test Pattern Generation”, Proc. VTS, 1998, pp. 446-452. Model Checking”, Proc. CAV, 2000, pp. 124-138. 1201 J. Giraldi and M. L. Bushnell, “EST The New Frontier in Auto131 A. Biere, A: Cimatti, E.M. Clarke and Y.Zhu, “Symbolic Model matic Test-pattern G ~ ~ : proc. ’ , DAC, 1990,pp. 667.672. Checking without BDDs”, Proc. TACAS, 1999, pp. 193.207. L211 M.K. Iyer, G.Panhasanthy, L. -C. Wang and K. T. -Cheng, “On 141 A, Biere, A, cimatti, E,M, Clarke, M, ~ ~and y,zhu, j i -sym. ~ ~ the Development of an ATF’G based Satisfiability Checker”, Pmc. MTV, 2002. bolic Model Checking using SAT procedures instead of BDDs”, Proc. DAC, 1999. pp. 317-320.

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