Automatic behavioral model generation suite for mobile ... - CiteSeerX

Automatic behavioral model generation suite for mobile phone system analysis Yasunori Miyahara, John Moore*, Taichi Ikedo and Lars Andersen* Matsushita Communication Industrial Co., Ltd. * Agilent Technologies, Inc.

1. Abstract Current wireless RF Large Scale Integrated (RF LSI) circuit designs continue to become larger, more complex, and encompass more functionality. It is difficult to analyze a full RF LSI circuit’s functionality using a transistor-level representation with the modulation signal. Instead, current mobile systems are only specified by system-level specifications such as bit error rate or error vector magnitude at the output terminal. However, even after the individual blocks are designed and they meet their specifications, the designer still has to verify the full circuit performance. An automatic model generation process has been developed to analyze the full system functionality. This technique has achieved both accurate and efficient verification. 2. RF LSI Design Flow Traditional design methodologies focus on the topdown design from an architecture or system to a circuit or layout [1]. In contrast to the success of the VHDL language for digital design, there are no reliable analog RF compilers to construct a circuit realization from the system design. Instead, RF designers manually design with the aid of specialized RF simulators. As a consequence of this process, the performance of the resulting circuit design is strongly dependent on the skill of the designer. To complicate matters, current RF circuit or system simulators are not up to the task of analyzing a complete RF LSI circuit. RF LSI circuits for a mobile terminal incorporate increasingly complex functionality requiring an increasing number of transistors. Simulation of such circuits requires more memory and increased CPU power. As a result, current simulation technologies are unable to perform a simulation of a complete transistor level circuit, including complex modulation signals, within a reasonable time. To address this performance bottleneck, a new automatic Verification Model Extractor [2] was developed to support the verification stage of the design flow. Figure 1 shows the RF LSI design flow for a mobile terminal RF LSI circuit. After the top-down circuit design is finished, and the system specifications are met on each block, verification behavioral models are generated for each system block. Using these verification behavioral models, a complete system-level simulation can be performed with a high degree of accuracy. This enables the circuit designer to check the overall system behavior. If the system

specifications are not met, the designer can trade off the performance of each block at the system level. Architecture ArchitectureDesign Design

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Fig. 1 RF LSI Design Flow 3. Verification Behavioral Models Traditional (top-down) behavioral models are efficient enough to perform a complete system-level simulation within a reasonable time frame. These models are well suited during the top-down specification stage of the RF LSI design flow. However, such a simulation rarely provides the accurate prediction of the full system specifications required during the bottom-up verification stage of the RF LSI design flow. Indeed, if they did provide sufficient accuracy, then there would be no need to verify the complete system behavior after the system specifications are met at each block. In order to support the verification stage of the design flow, verification behavioral models need to differ from traditional behavioral models in two important ways. First, verification models must be generated based on the behaviors of an actual circuit. Additionally, verification behavioral models typically need to represent a more complete behavioral description of the circuit in question than is typically required by top-down behavioral models. Ideally, each RF circuit block will exceed their block specifications. However, this is not always achievable which requires making trade-offs of block specifications at the block level. Therefore, the first requirement of a verification behavioral model is to represent the true behavior of a circuit as it is realized within an actual design. One approach to this requirement would be to

feed the realized specifications of each circuit block back to the system behavioral models. This requires a mechanism to determine the system specifications for each circuit block. An automated approach to this process is depicted in Figure 2. After the RF circuit block is designed with the aid of an RF simulator, it is connected to a Verification Model Extractor. This extractor performs a final RF simulation of the circuit, which extracts the pertinent system behaviors of the circuit under test and stores them in a results file. When the verification behavioral model is used as a systemlevel model in the verification simulation, the data in the extracted results file are used to reconstruct the equivalent behaviors of the full transistor-level circuit block. DUT

Verification Behavioral Model

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Fig. 2 Verification Model Extraction Process Since the extracted behaviors are stored in a file, it is possible to extract more information about the system level behaviors than is encapsulated in a few, systemlevel specifications. This allows the verification behavioral models to represent the system-level behaviors more accurately than traditional top-down behavioral models. For example, the classic behavioral model of an amplifier is a third-order polynomial whose linear coefficient is set by the amplifier’s linear gain, and whose third order coefficient is set by the amplifier’s Third Order Intercept. This produces a model that can identically reproduce these two behaviors, but such a model is unable to reproduce other system behaviors such as gain expansion or saturation. A very simple verification behavioral model that establishes a look-up table for the amplifier’s RF output power versus input power will be a more accurate representation when these additional behaviors are important. Because the Verification Model Extractor only extracts the dominant system-level behaviors of the circuit block, the verification behavioral model can present a more compact representation to the circuit simulator than would the full transistor-level circuit representation. This translates to computational savings – both in terms

of required memory and simulation time – for large transistor-level circuits. This computational advantage comes at the expense of flexibility and accuracy. The model extraction processes only a subset of all the circuit’s behaviors. The behaviors not explicitly extracted will not be accurately reproduced in the verification behavioral model. To automatically identify the pertinent behaviors of a general non-linear circuit block with no a priori knowledge of the circuit’s intended functionality or operating ranges is a daunting task. In order to simplify this task, the verification model extraction package consists of a number of distinct verification behavioral models, each paired with their own verification model extractor. This allows each model extractor to concentrate on the extraction of a very specific set of behaviors that represent the unique dominant behaviors of their associated verification behavioral model. For example, the extractor for a mixer needs to excite a circuit-under-test with two inputs (RF and LO) at distinct frequencies, and extract the response at the output (IF) over a set of frequencies. In contrast, the extractor for an amplifier need only excite a single input and extract at a single output. The separation of the extracted verification behavioral model from the model extractor is a reflection of how the RF VSI design flow is executed in many organizations. Because of the specialized nature of the RF circuit design process, the RF circuit design team is usually separate from the overall system design team. The extracted behavioral models provide a convenient package that can be handed from the RF circuit design team to the system design team. Additionally, the extracted verification behavioral models only contain information about the external behaviors of the transistor-level circuit. This provides an inherent protection of the intellectual property that is contained within the transistor-level circuit representation. 4. Generation of the Behavioral Model

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Fig. 3 WCDMA Transmitter Block Diagram Figure 3 shows the block diagram of transmitter stage for a W-CDMA LSI circuit. This system consists of a baseband filter, a modulator, an IF Gain Controlled Amplifier (GCA), a 1st mixer, an RF GCA and a driver amplifier. The driver amplifier is then connected to the power amplifier. The output signal’s level is control by a

driver amplifier. These results show a very accurate modeling of the distortion performance.

baseband LSI circuit. The maximum output signal power is +24dBm at the power amplifier. For this transmitter stage, we will show an example of the verification behavior model generation process with discussions about the accuracy of the process. Figure 4 shows the driver amplifier circuit and Figure 5 shows the RF CGA circuit. These circuits operate at 2GHz and their primary behavior of concern is distortion of the modulated signal. The driver amplifier is implemented in a commonemitter amplifier configuration, where transistor Q1 drives the Power Amplifier. Input and output matching is achieved with external components. The RF GCA consists of two differential amplifiers. The amplifier gain is controlled by tail current. The differential output signal is transformed to single ended by a load tank circuit. Verification model extractors are used to extract verification behavioral models for these amplifiers. The primary system-level behaviors extracted for these amplifiers are the frequency response, distortion performance, and the gain control performance of the GCA.

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Figure 6 shows the distortion performance of the verification behavioral model compared to the transistorlevel simulation of a cascade of the RF GCA and the

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5. Transmitter Block Full Simulation Based on the success of the verification behavioral models to reproduce the distortion performance of the RF GCA and driver amplifier combination, the next step is to examine the validity of using verification behavioral models to predict the ACLR specification (which is the primary performance indicator in W-CDMA) of the complete transmitter stage. A W-CDMA modulation signal is applied at the I/Q terminals with an input level of 300mVp-p. The desired ACLR specification for this W-CDMA is –45 dBc at an output level of +6 dBm. Verification behavioral models were extracted for the modulator, IF GCA, 1st mixer, RF GCA and driver amplifier blocks of the transmitter stage as shown in Figure 3. The verification model extractions were performed with a gain step of 5 dB, with an assumption of 50 Ohm input and output loading impedances. A full system-level simulation was performed with these verification behavioral models. In this simulation, the 1st and 2nd local oscillators were modeled as ideal circuit blocks. The external RF filter was also modeled with an ideal circuit block. In addition, a reference transistor-level simulation was performed on the entire transmitter stage. However, the full transistor-level circuit needed to be simplified in order to circumvent convergence problems as well as memory limitations. Reductions were made to the bias circuitry, the reference current circuit, as well as some of the control circuitry. Figure 7 shows the computed ACLR results at the driver output terminal for the transistor-level simulation. Figure 8 shows the ACLR results from the verification behavioral model simulation results for the same environment. The transistor-level simulation predicted an ACLR of 47 dBc with a simulation time of 9328 sec on Sun Blade1000 900MHz with 5Gbyte memory. The verification behavioral model simulation predicted an ACLR of 44 dBc with a simulation time of 218 sec on the same machine.

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Fig. 7 Transistor-level ACLR Simulation Result

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Fig. 8 Behavioral Model ACLR Simulation Result The use of verification behavioral models produced reasonably accurate results – within 3 dB of the measured ACLR – with a significant reduction of simulation time compared to the full transistor-level simulation. In addition to the simplifications to the full transistor-level circuit representation, the major discrepancies between the transistor-level simulation results and the verification behavioral model results are due to the assumed 50 Ohm environments during the model extraction process. However, within the LSI circuit, such an environment is not consistently maintained, particularly at the 1st mixer output and the RF GCA input. This produces an internal mismatch gain that is not properly modeled in the behavioral model system simulation. 6. Conclusion Using verification model extractors, it is possible to analyze the full system for a mobile RF LSI circuit. After the individual circuit blocks are designed, the system specification can be checked with these tools. This achieves a critical verification that the desired system performance can be achieved by the transistor-level circuitry. If a circuit designer uses these tools, fewer RF LSI development iterations are required and the overall design time can be reduced. References [1] Yasunori Miyahara et al., “Design Methodology for Analog High Frequency ICs” 33rd Design Automation Conference Session 32.3, June 1996. [2] ADS Users’ Manual, Release 2002, Agilent Technologies, Westlake Village, CA, 2001.