Mar 30, 2000 - Distributed Embedded Systems Based on. Schedulability Analysis. Paul Pop, Petru Eles, Zebo Peng. Department of Computer and Information ...
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis
Paul Pop, Petru Eles, Zebo Peng Department of Computer and Information Science Linköping University Sweden
1 of 16 March 30, 2000
Outline
n Motivation n System Architecture n Schedulability Analysis n Communication Synthesis n Experimental Results n Conclusions
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
2 of 16 March 30, 2000
Motivation and Characteristics n Embedded System Design. Scheduling, Communication, Bus Access.
n Characteristics: - Heterogeneous system architecture. - Fixed priority preemptive scheduling for processes. - Communications using the time-triggered protocol (TPP). H. Kopetz, G. Grünsteidl. TTP-A Protocol for Fault-Tolerant Real-Time Systems. IEEE Computer ‘94
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
3 of 16 March 30, 2000
Contributions and Message
n Contributions: - Proposed a schedulability analysis for distributed hard-real time systems that use the time-triggered protocol. - Developed optimization strategies for the communication synthesis problem. n Message: - By optimizing the buss access scheme the “degree of schedulability” of the system can be significantly improved.
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
4 of 16 March 30, 2000
Event-Triggered vs. Time-Triggered n Event-triggered: activation of processes and transmission of messages is done at the occurrence of significant events. n Time-triggered: activation of processes and transmission of messages is done at predefined points in time. processes messages event-triggered time-triggered
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
5 of 16 March 30, 2000
Hardware Architecture I/O Interface
n Hard real-time distributed systems.
RAM
n Nodes interconnected by a broadcast communication channel.
ROM
CPU
ASIC
n Nodes consisting of: TTP controller, CPU, RAM, ROM, I/O interface, (maybe) ASIC.
TTP Controller
n Communication between nodes is based on the time-triggered protocol.
Node
S0 S1 Slot
S2
S3
S0 S1
TDMA Round Cycle of two rounds
S2
S3
n Bus access scheme: time-division multiple-access (TDMA). n Schedule table located in each TTP controller: message descriptor list (MEDL).
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
6 of 16 March 30, 2000
Software Architecture n Real-Time Kernel running on the CPU in each node. n The worst case administrative overheads are known. n Fixed priority preemptive scheduling. n Tick scheduler in each kernel. N1 CPU
N0 CPU m1
T
Out
m2
P2
P3
m1
m2
RTK
RTK
Out
P1
m2
m2
D
event-triggered
MBI
MBI
TTP Controller
TTP Controller
S1
S0
S1
time-triggered
Round2 Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
7 of 16 March 30, 2000
Problem Formulation Input n An application modelled as a set of processes. n Each process has an execution time, a period, a deadline, and a priority. n The system architecture and mapping of processes to nodes are given. n Each message has a known size.
Output n A schedulability analysis (response time analysis) for hard real-time systems that use the time-triggered protocol for communications. n The MEDL for the TTP controllers so that the process set is schedulable on an as cheap (slow) as possible processor set.
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
8 of 16 March 30, 2000
Scheduling of Messages over TTP messages are dynamically produced by the processes frames are statically determined by the MEDL m1 S0
m2 Round 1
S1
m3
m4 Round 2
m5 Round 3
1. Single message per frame, allocated statically: Static Single Message Allocation (SM) 2. Several messages per frame, allocated statically: Static Multiple Message Allocation (MM) 3. Several messages per frame, allocated dynamically: Dynamic Message Allocation (DM) 4. Several messages per frame, split into packets, allocated dynamically Dynamic Packets Allocation (DP) Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
9 of 16 March 30, 2000
Schedulability Analysis n Starting point: schedulability analysis for distributed hard real-time systems with communication based on a simple TDMA protocol. K Tindell, J. Clark. Holistic Schedulability Analysis for Distributed Hard Real-Time Systems. Micro’94
n Schedulability test: response time r i ≤ deadline D i for each process. n The response time r i depends on the communication delay between sending and receiving a message. n The communication delay is calculated differently for each of the four approaches to message scheduling over TTP (SM, MM, DM, DP):
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
10 of 16 March 30, 2000
Schedulability Analysis (Continued) n The communication delay for a message m depends on: 1. Static Single Message Allocation (SM): Tmmax 2. Static Multiple Message Allocation (MM): Tmmax Tmmax m S0
S1
m’ S0
S1
Xm m
S0
S1
3. Dynamic Message Allocation (DM): slot sizes in a TDMA round. 4. Dynamic Packets Allocation (DP): slot sizes in a TDMA round, packet size.
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
11 of 16 March 30, 2000
Optimizing Buss Access (SM and DM) p1 p2 p3
Process P2 misses its deadline!
m1
m2
p1 p2 p3
Swapping m1 with m 2: all processes meet their deadlines. m2
p1 p2 p3
m1 Putting m1 and m2 in the same slot: all processes meet their deadline, the communication delays are reduced.
m1 m2 Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
12 of 16 March 30, 2000
Optimization Strategy n The synthesis of the MEDL is performed off-line: optimization process. n Comparison of the four messages scheduling approaches: fair only for near-optimal results. n Optimization strategies based on Greedy Approaches and Simulated Annealing. n Cost function: degree of schedulablity.
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
13 of 16 March 30, 2000
Experimental Results Average percentage deviation from the best among the four message scheduling approaches:
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
14 of 16 March 30, 2000
Experimental Results (Continued) Average percentage deviations [%]
The quality of the greedy optimization heuristics: 2
1.5 OptimizeSM OptimizeMM OptimizeDM OptimizeDP
1
0.5
0 80
160
240
320
400
Number of processes
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
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Conclusions
n Static priority preemptive process scheduling. Communications based on a time-triggered protocol. n Four different message scheduling policies over TTP: - analysis of the communication delays and - optimization strategies for the buss access scheme. n Approaches compared using extensive experiments: - guidelines for designers. n Optimizing the buss access scheme the “degree of schedulability” of the system can be significantly improved.
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis Paul Pop, Petru Eles, Zebo Peng
16 of 16 March 30, 2000
