A minimum output load of fan-out of four inverters (FO4) is used for power and delay measurements. [3]. 3-1) Test bench (1). The parameters for TSMC 180nm ...
Calculating Output Capacitance of a Full Adder Testbench 1) MOSFET model
2) Inverter Model
3) Calculating of output capacitance at full adder testbenches A minimum output load of fan-out of four inverters (FO4) is used for power and delay measurements [3].
3-1) Test bench (1)
The parameters for TSMC 180nm CMOS process are as follows: 𝜀𝑜𝑥 = 𝜀𝑆𝑖𝑂2 ∗ 𝜀0 = 3.9 ∗ 8.8542 ∗ 10−12
𝐹 𝑚
= 34.5314 ∗ 10−12
𝐹 𝑚
𝑡𝑜𝑥 = 4.1 𝑛𝑚 𝐶′𝑜𝑥 =
𝜀𝑜𝑥 = 8.42 𝑚𝐹 𝑡𝑜𝑥
Lmin = 180nm for a small inverter we assume that: Ln = Lp = 180nm, Wn = 180nm, Wp = 450nm 𝐶𝑖𝑛_𝑖𝑛𝑣 =
3 ′ 𝐶 (𝑊𝑝. 𝐿𝑝 + 𝑊𝑛. 𝐿𝑛) = 1.43 𝑓𝐹 2 𝑜𝑥
𝐶𝐿𝑜𝑎𝑑 = 4 ∗ 𝐶𝑖𝑛_𝑖𝑛𝑣 = 5.72 fF The calculated parameters in Ref [3] are: 𝐶𝑖𝑛_𝑖𝑛𝑣 = 1.4 𝑓𝐹 𝑎𝑛𝑑 𝐶𝐿𝑜𝑎𝑑 = 5.6 𝑓𝐹
3-2) Test bench (2)
The size of output inverter in Ref [4] is as the same. Therefore, by changing CL in test bench (2), loading conditions won’t change. If you want to test a full adder cell under different loading conditions you can: 1) Change the output capacitance at test bench (1) Or 2) Change the size of output inverters in test bench (2) (Consider the minimum possible amount for width of a MOSFET in any technology).
References: [1] J. Baker, CMOS Circuit Design, Layout, and Simulation, third edition, Chapter 6. [2] J. Baker, CMOS Circuit Design, Layout, and Simulation, third edition, Chapter 10. [3] S. Goel, A. Kumar, and M. Bayoumi, “Design of robust, Energy-Efficient full Adders for DeepSubmicrometer design using Hybrid-CMOS logic style,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, pp. 1309-1321, December 2006. [4] M. Aguirre and M. Linares, “CMOS full-adders for energy-efficient arithmetic applications IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, pp. 718-721, April 2011.
