Capacitor Multiplier with Wide Dynamic Range and

1

Capacitor Multiplier with Wide Dynamic Range and Large Multiplication Factor for Filter Applications Ivan Padilla-Cantoya, Member, IEEE  Abstract—A capacitor multiplier realization based on currentvoltage conversion with a high performance voltage follower is presented. The architecture has a large multiplication factor of up to 10 k or larger compared to current-mode multipliers, and wide dynamic range compared to voltage-mode capacitor multipliers. It offers higher accuracy than voltage-mode multipliers as the design is based on passive devices, eliminating the variations of the drain-source output resistance of a transistor. The structure offers a very low ESR and it proved to be useful for low-voltage applications. Experimental results of a test chip in 0.5μm CMOS technology implemented in a low- and a band-pass filters that validate the operation are presented. Index Terms—Analog Integrated multiplier, low-voltage analog circuits

Circuits,

capacitor

I. INTRODUCTION

C

ONSIDERING that portability has become an important requirement for electronic systems, circuit design has had the tendency to integrate every module of a system in a single silicon die as technology continues to scale down, enhancing features such as speed, minimum supply voltage and power consumption. Applications such as analog filters have benefited from this tendency. These implementations typically include capacitors which have been part of circuit integration as well. Unfortunately integrated capacitors occupy significant space compared to other devices. For these reason designers have recently explored a wide diversity of techniques to magnify the capacitive effect in order to reduce silicon area without compromising performance. Some schemes offer very good accuracy but limited multiplication factor, decreased effective bandwidth, increased power consumption, and silicon area [1]-[3]; others have a large multiplication factor and

Manuscript received February 28th, 2012; revised October 19th, 2012. This work was supported in part by the Mexican Consejo Nacional de Ciencia y Tecnologia (CONACYT) under Grant 134886. I. Padilla-Cantoya is with the Instituto Tecnologico y de Estudios Superiores de Occidente (ITESO), Tlaquepaque Jalisco. 45604, Mexico (phone: +52 (33) 3669 3434 x3131; e-mail: [email protected]). Copyright (c) 2013 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending an email to [email protected] Digital Object Identifier 10.1109/TCSII.2013.2240814

effective bandwidth, although they have no accuracy and very limited dynamic range [4]. In this paper a capacitor multiplier with large output swing, large multiplication factor, high accuracy and reduced silicon area is presented. II. PROPOSED CIRCUIT A. Capacitor Multipliers The types of capacitor multipliers can be split into two categories, current- and voltage-mode multipliers. The first type is based on current scaling; Fig. 1a shows the concept of operation, where an equivalent current is magnified by a multiplication factor. If a voltage is applied to capacitor C a current ic is induced, sensed by a dependent current source, and magnified by a factor k. Therefore, a current kic is then sourced from the output terminal, resulting in a total current of itot = ic(1+k), thus offering an equivalent capacitance of Ceq = C(1+k), and a multiplication factor of 1+k. The typical implementation is shown in Fig. 1b, where the current ic is sensed by the diode-connected transistor M1; consequently, the gate-source voltage of M1, vgs1, is induced and copied to transistor M2. If M2 is upsized with respect to M1 by a factor k, then the total current results in itot = ic(1+k) as described previously. The advantage of this structure relies on the fact that transistors M1 and M2 can be physically matched using proper layout techniques, which increases the accuracy of the multiplication factor, although it has significant disadvantages. The silicon area and the static power dissipation increase proportionally to the multiplication factor, which represents a considerable drawback. This restricts the multiplication factor to no more than a few tens for low-power and reduced silicon area applications. Even if the circuit can be grown, the physical proximity of the edges of M2 is compromised with respect to M1, increasing the mismatch between these transistors, and the error in the multiplication factor is also affected. In addition, the equivalent series resistance (ESR) defined as 1/gm1, where gm1 is the transconductance gain of M1, represents a moderately low resistance of a few thousands of ohms that limits the effective bandwidth. The second category, the voltage-mode capacitor multipliers, is based on the well-known Miller effect. The conceptual operation is shown in Fig. 1c, where a capacitor C is connected to two nodes and can be conceptually reduced to

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2 equivalent capacitances at each node referenced to ground. Miller theory shows that these capacitances result in Ceq1 ≈ (V2/V1)C = AvC and Ceq2 ≈ C. Fig. 1d shows a two-stage differential amplifier, a typical implementation of this scheme, generally referred to as Miller capacitor. The equivalent capacitance at node 1, as a result of Miller effect, is defined as Ceq1 = Av2C, where Av2 = gm2ro2 is the low-frequency gain of the second stage, and gm2 and ro2 are the transconductance gain and the output resistance of the amplifying stage respectively. This creates a large capacitance at node 1 and hence, proper location of poles is required to ensure frequency stability [5]. Zeq

itot ic

kic

itot

Zeq

C

C

ic

IB

kic M2

itot = ic(1+k) Zeq = Cc(1+k)

-

+ + vgs vgs

(a)

Zeq V1 Ceq1

V2

Ceq2

Ceq1 ≈ (V2/V1)C = |AvC| Ceq2 ≈ C

+ -gm1

-

FVF

C

Zeq

(c)

-

(b)

C

-Av

M1

B. Proposed Capacitor Multiplier The operation of the proposed circuit is based on setting an output voltage according to the current sensed at that node, scaled by a multiplication factor. This is achieved by means of a voltage follower and a current sensing block that performs a scaled current-voltage conversion according to the capacitor to be multiplied. Fig. 2a shows the block diagram of the proposed circuit. The voltage follower is formed by M1, M2, and the current source shown in the dashed square, which is defined as Flipped Voltage Follower (FVF) [6]. Note that transistor M2 has a constant biasing current IB, producing a constant dc voltage VGS2, reflecting variations at the gate of M2 at node o, level shifted by VGS2. In addition, M1 can sink large currents, offering a very low resistance at this node of approximately 1/(gm1gm2ro2), which has a value of a few tens of ohms. Observe that the output swing is limited to Voswing = VGS1 – VDS2sat –VDS1sat = VT1 – VDS2sat, which is reduced to 200-300 mV in newer technologies; however, this limitation is addressed in the practical implementation. vgs1 = id1/gm1 Vo = Vc – VGS2

IB V1 1

-gm2

ro1 Ceq1

x

V2 2

ro2

Ceq2

Zo

CFVF

o

io

M1

-

Currentvoltage capacitance realization

+ vgs1

2IB

(d)

Fig. 1. Current-mode capacitor multipliers showing a) concept of operation and b) practical implementation; voltage-mode capacitor multipliers showing c) concept of operation and d) practical implementation.

The advantage of this structure is that typical values for the drain-source resistance of a transistor in 0.5μm technology, ro, range between 50-200 kΩ, and the gain Av, which depends on this parameter, results in large values of around 100-10k V/V; thus the equivalent capacitance Ceq1 is rather large, although this methodology presents significant disadvantages. The term ro strongly depends on the channel-length modulation factor λ, which may vary significantly with fabrication process, temperature and drain-source voltage, thus, the multiplication factor may also suffer considerable variations, hence, it is not suitable for applications where a precise value is required. For that reason this scheme is typically used in negative feedback so as to control the overall gain by means of passive devices, where a minimum value for the equivalent capacitance is required rather than an exact value. Additionally, the dynamic range is affected as well. Normally, the gain factor of the second gain stage, defined as Av = V2/V1, is typically large to provide a significant multiplication factor. However, the swing of V2 must be kept within its operational range to avoid distortion due to saturation and maintain the integrity of the signal; hence, the maximum swing at node 1 is limited to V2/Av, which is reduced to a few millivolts. Moreover, the dc voltage level at node 1 is restricted to the biasing voltage of the second stage, given the fact that for some applications this node is required to have a specific reference voltage such as ground, to avoid static power consumption.

M2

Vo

CL

Cc

x M3

Zo

M1

y

+

Rk -1

ic V BN

vgs1 -

IB

-

(a)

C

ic

o

io

Vc

VCP

M2

Vo

+

Ceq

+

-

vc

+

IB +

-vc

Cc (b)

Signal ground

-

VBN

MB

Fig. 2. Proposed capacitor multiplier showing a) block diagram and b) practical implementation.

Assuming a small signal current io is applied, voltage vgs1 = io/gm1 is induced. The current-voltage capacitance realization block converts the signal -vgs1 into a scaled current, which is then passed through a capacitor to produce a voltage Vc. This is then connected to the input of the FVF, setting the output voltage Vo to Vc level shifted by VGS2. Fig. 2b shows the practical implementation of the proposed structure. The FVF is replaced by the denominated Cascoded FVF (CFVF) [7], which is a modification of the follower that offers wide output swing. Transistor M3 and an extra biasing current source are added. M3 enhances the output resistance to approximately 1/gm1gm2ro2gm3ro3, with typical values of less than 1 Ω. In addition, the output swing is increased to Vdd – VDSIBsat – VDS2sat – VDS1sat – Vss ≈ Vdd – Vss – 3VDSsat as described in [7], where the voltages with the sub index DSsat refer to the drain-source saturation voltage of the corresponding transistor. Note that this swing depends on the voltage rails, which can be increased as required, contrary to the case of the conventional FVF.

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3 The current-voltage capacitance realization block is formed by a conventional operational transconductance amplifier (OTA) with a cascoded output stage, an input resistor Rk and a feedback capacitor C. Observe that this structure is similar to that of an integrating configuration. The unity-gain negative buffer to achieve negative feedback is formed by a transistor in common-source configuration with a diode-connected transistor as load, both cascoded (voltage at the non-inverting input of the OTA must be set accordingly). Note that the current io sensed by M1 produces the voltage vgs1 = io / gm1 inducing a current in Rk defined as ic = -vgs1 / Rk. This current is a scaled replica of io, and is passed through the capacitor C, resulting in the voltage vc = -ic / Zc, which is then reflected at the output by the CFVF. Thus, considering a transfer function of 1/sRC for the integrating configuration, the voltage-current ratio corresponds to v v 1  s 2 Rk Cc C / g m 2  . (1) Zo  o  c  io io sgm1 Rk C 1  sCc / g m1  Where the term gm1Rk is the multiplication factor, and Rk is designed as a scaled factor of 1/gm1. The biasing voltage VBN was used at the non-inverting input of the OTA, due to the fact that the quiescent gate-source voltage of M1, VGS1, corresponds to that biasing voltage. This results in zerovoltage drop across Rk, and thus, no current under static conditions. Additionally, at very low frequencies the capacitor C represents a very large impedance so that the conventional integrating configuration operates as if no feedback element was present, thus a dc voltage level is not defined. For this reason a large-value resistor is normally included in parallel with the capacitor. In the case of the proposed circuit this resistor is not required, as the overall feedback adjusts the dc voltage level to provide zero current, reducing the silicon area. C. Frequency Analysis Fig. 3a shows the small-signal equivalent diagram of the proposed circuit. The conventional FVF in Fig. 2a was considered for simplicity. Note that this cell has a negative shunt feedback loop; hence a compensating capacitor Cc is included at node y to ensure frequency stability of this block. As depicted in [6], the condition Cc > 4Co/(gm1ro1) must be satisfied to avoid oscillation, where Co is the load capacitance at node o. Observe in Fig. 3a that no current flows from node x through the block H(s) due to the buffer, thus, the current iCc = sCcvgs1 flows through M2 from node o. Considering that id1 >> iro1, we may define an expression for the output current using the Kirchhoff’s current law (KCL) at node o as io ≈ iCc + id1 = vgs1(sCc + gm1); hence, the induced voltage vgs1 results in io . (2) v gs1 s   g m1  sCc Additionally, applying the KCL at node x, we get iro2 = iCc + id2; deducting from M2 the expressions iro2ro2 = vo – vgs1, and id2 = gm2vgs2 = -gm2(vgs1H(s)+vo) we may derive 1  sCc ro 2  g m 2 ro 2 H s  . (3) vo  vgs1   1  g m 2 ro 2  

Where H(s) represents the transfer function of the integrating configuration H(s). The small-signal equivalent circuit of this block is shown in Fig. 3b, where gm4 and ro4 are the transconductance gain and the output resistance of the OTA respectively. Capacitance C is reduced to the equivalent capacitances C1 and C2 due to Miller effect. Thus, the relation Av = V2/V1 can be defined as  gm4 r sC  g m 4  (4) V Av  2   g m 4 Z 2   o4 V1 1  sCro 4  V  1  sC1  1  ro 4 V 2   Note that C1 forms a voltage divider with Rk, resulting in V1/Vi = 1/(1+sRkC(1-Av)). Therefore, the transfer function, H(s), is described by:

H s  

V2 V1 Av r sC  g m 4  . (5)    o4 V1 Vi 1  sRk C 1  Av  1  sCRk g m 4 ro 4

By substituting the results from (2) and (5) in (3) we obtain the expression for the output impedance 1  sCc ro 2 1  sCRk g m4 ro 4   g m2 ro 2 ro 4 sC  g m4  . (6) Zo  g m1  sCc 1  g m2 ro 2 1  sCRk g m4 ro 4  If very high frequency effects are neglected, a zero and two poles can be defined as: g m 2 g m 4 ro 2  g m1 . (7) 1 z  ;  p1  ;  p2  C g m 2 ro 2  Rk g m 4  CRk g m 4 ro 4 Cc Where poles ωp1 and ωp2 define the first and second frequency corners that delimit the frequency operational range of the structure. iCc +

c

vgs2

H(s) -1

iCc

-

x

o

+

vgs1

Cc

-

(a)

C

iro2

id2

-

vro2

ro2 + vo id1 ro1

Vi

Rk

1

V1

-gm4

io

V2

2

ro4 C1

C2 (b)

Fig. 3. Small signal diagram of a) the proposed circuit, and b) the currentvoltage capacitive realization with transfer function H(s).

Additionally, the overall negative feedback loop suggests that frequency stability is required. Assuming the loop is opened at the gate of M2, an input current io induces a voltage vgs1 = io / (sCc+gm1), which combined with the buffer and the transfer function H(s) an expression for the output voltage and input current vc/io may be obtained; although another aspect should be considered. The impedance in (6) represents a current-voltage conversion; however, and for analysis purposes, in a negative feedback system where the output and input signals are subtracted, the same units are required. Thus, the resulting current subtracted from the input io is that induced in M1 as a result of vc at the input of the FVF. Small signal analysis reveals that id1 = vc/ro1, hence the open-loop output current id1 as a result of an input current io is described as i v ro 4 g m 4  sC  (8) Ai  d 1  c  io io ro1 ro1 sCc  g m1 1  sCRk g m 4 ro 4  Note that the integrating configuration in Fig. 3b is similar to the conventional two-stage amplifier. Following the same

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4 design procedure the dominant pole is found at node 1 due to the resulting large capacitance by means of Miller effect. It corresponds to the bandwidth BW = 1/CRk(gm4ro4), assuming that Rk is significantly greater than the output resistance of the buffer. Also, from (8), the next root is found at ωzc = gm4/C, the RHP zero created by C at the output of the OTA (if gm4/C > gm1/Cc).

multiplier permits. Again, for the case of the two-stage amplifier in Fig. 1d, the condition ωp2 > 2GB gives sufficient phase margin to ensure stability, considering that ωp2 is the only root shifting the phase.

Fig. 6. Simulated open-loop frequency response of the proposed circuit using different values for the multiplication factor K.

Fig. 4. Microphotograph of the fabricated circuit (232 μm x 269 μm).

Additionally, the dc gain from (8) is defined as AiOL = gm4ro4/gm1ro1. Hence, the gain bandwidth product is given by GB = AiOLBW = 1/(gm1ro1CRk). Considering that the condition ωzc > 2GB is typically used as a practical condition to ensure sufficient phase margin for frequency stability, then the expression gm4 > 2/(gm1ro1Rk) must be met.

The case of the Butterworth filter includes three poles at ωo, thus, its phase shifts three times more rapidly; also, an additional phase shift due to ωp1 is introduced. Therefore, the condition 2(3∙2ωp1) < ωo is used to ensure the multiplier encompasses the transfer function of the filter, leading to the expression 12/CRkgm4ro4 < fo. This results in gm4ro4 > 37.5; if values gm4 = 1 mS and ro4 = 5 MΩ are chosen, the required condition 5000 > 37.5 is met and the OTA provides a large dc gain so as to enhance the linearity of the system. Additionally, assuming gm4/C > gm1/Cc and ro1 = 100 kΩ, the expression to ensure stability due to the negative feedback loop is gm4 > 2/(gm1ro1Rk) which results in 1 < 10k.

Fig. 5. Simulated impedance of circuits in [1], [3], and the proposed circuit; and transfer characteristic G(s) of their implementation in a third-order Butterworth filter using a Cauer topology.

Design Example: assume the design of a third-order Butterworth filter using a Cauer topology is desired, consisting of a cutoff frequency fo = 100 kHz, with input and load resistances of 1 kΩ and a minimum output swing of 1 Vpp. Given these parameters the topology requires two inductors of value L1 = L2 = 1.6 mH and a capacitor Ceq = 3.2 nF to be implemented using the proposed structure. Assuming gm1,2 = 1 mS and Rk = 200 kΩ are chosen, a capacitor C = 16 pF is required to satisfy the expression Ceq = C(gm1Rk) = 3.2 nF. The design must ensure that the frequency operational range of the proposed multiplier (delimited by poles ωp1 and ωp2) encompasses the transfer characteristic of the filter G(s). Thus, pole ωp1 must be located before the cutoff frequency, ωo, whereas the zero ωp2 is to provide as much attenuation as the

Fig. 7. Measured impedance of the proposed circuit for different values of the multiplication factor K, split into magnitude and phase.

III. SIMULATION AND EXPERIMENTAL RESULTS A prototype circuit was simulated in spectre and fabricated in On-Semiconductor 0.5μm double-poly three-metal CMOS technology through MOSIS. Fig. 4 shows the microphotograph of the circuit. The nominal threshold voltages are VTHN = 0.7 V and VTHP = -0.9 V and the transistor sizes are 54/1.2 and 157/1.2 μm/μm for NMOS and PMOS respectively. The

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5 circuit was tested with a supply voltage of Vdd -Vss = 3 V and a biasing current IB = 100 μA, resulting in VDSsat = 0.2 V. The values for the capacitors are C = 10 pF and Cc = 2pF. Fig. 5 shows the simulation results of the proposed circuit compared to the structures reported in [1] and [3] implemented in the filter described in the Design example section.

Fig. 8b shows the frequency response of an LC second-order band-pass filter formed by Ceq in parallel with an inductor L = 180 mH, in series with a load resistor RL = 10 kΩ, both split into magnitude and phase. The resistor and inductor are offchip devices. Table II shows a comparison of experimentally measured parameters between circuits in Figs. 1b, 1d and the proposed circuit in Fig. 2b in an RC LPF configuration. All were implemented on the same die for characterization purposes. An off-chip resistor R = 10 kΩ was used; in the case of circuit in Fig. 1d a large resistor RFB = 1 MΩ was used in parallel with C to define the dc output voltage. Note that circuit in Fig. 1b has a small multiplication factor, and circuit in Fig. 1d has small output swing, whereas the proposed circuit overcomes both limitations. TABLE II EXPERIMENTALLY MEASURED PARAMETERS BETWEEN CONVENTIONAL AND THE PROPOSED CIRCUITS Parameter

Fig. 8. Frequency response of a) an RC low-pass filter using a resistor of 10 kΩ and b) an RLC second-order band-pass filter with a series resistor of 10 kΩ, an inductor L = 180 mH, both with the capacitor multiplier for different values of K, split into magnitude and phase.

The upper part of Table I shows the results of the circuits simulated in 0.5μm technology. Observe that the multiplication factor requires significantly large silicon area and power consumption for the two conventional circuits, and the effective bandwidth is also reduced with respect to the proposed structure. Fig. 6 shows the open-loop frequency response simulation of the proposed circuit for K = 10, 100, 1 k and 10 k. TABLE I COMPARISON OF SIMULATION PARAMETERS BETWEEN CIRCUITS IN [1], [3], AND PROPOSED CIRCUIT IN FIG. 2B Parameter Minimum supply voltage [V] Maximum output swing [V] (Vdd - Vss = 3 V and zero load) Power consumption [mW] Effective BW [Hz] THD [%] (Vi = 0.5Vpp @ 1kHz) Silicon area [mm2]

2

1.6

Proposed circuit (Fig. 2b) 1.6

1.4

1.6

1.4

30.3 327 0.85 0.928

32.1 470 0.065 0.556

1.8 1.3 M 0.105 0.067

Circuit in [1] (2006)

Circuit in [3] (2009)

Base capacitance [pF] Multiplication factor Minimum supply voltage [V] Maximum output swing [V] (Vdd - Vss = 3 V and zero load) Power consumption [mW] Effective BW [Hz] ESR [Ω] THD [%] (Vi = 0.5Vpp @ 1kHz) Silicon area [mm2]

10k 1k 100 10

Lower limit [dBΩ] 65.1 65.1 65.1 58.3

fp1 [Hz]

fz [Hz]

Ceq [F]

5.2 42.8 433 2.43 k

750 8k 116 k 1.26 M

99.73 n 9.89 n 903 p 114.8 p

To test the multiplication factor, the values of 10 kΩ, 100 kΩ, 1 MΩ, and 10 MΩ were used for Rk. This, in combination with the transconductance gain of M1, gm1 ≈ 1 mS, results in equivalent capacitances of values 100 pF, 1 nF, 10 nF and 100 nF respectively. Fig. 7 shows the measured impedance of the proposed circuit. The lower part of Table I shows the numerical measurements. Fig. 8a shows the frequency response of an RC low-pass filter (LPF) using an off-chip resistor of 10 kΩ and load capacitor implemented using Ceq.

Proposed circuit (Fig. 2b) 10 100 1.6

1.2625

27.25m

1.6

3.33 5.7 M 502.7 0.0943

0.996 244 k 1k 0.82

0.0395

0.0328

1.815 1.513 M 218.46 0.076 0.042 (for Rk = 100kΩ)

The design and operation of a capacitor multiplier realization based on current-voltage conversion with a high performance voltage follower was discussed. The architecture proved to have a wide dynamic range due to the voltage follower, with a large multiplication factor of up to 10 k or higher. Experimental results implementing the circuit on a low- and a band-pass filter validate the proposed operation. REFERENCES [1] [2]

Upper limit [dBΩ] 113.5 113.5 113.5 113.5

Voltagemode (Fig. 1d) 10 ~100 1.4

IV. CONCLUSION

MEASURED IMPEDANCE OF CIRCUIT IN FIG. 7 Gain factor K

Currentmode (Fig. 1b) 10 10 2

[3]

[4]

[5] [6]

[7]

I. C. Hwang, “Area-efficient and self-biased capacitor multiplier for onchip loop filter,” IET Elec. Let, vol. 42, no. 24, pp. 1392-93, Nov 2006. S. Solis-Bustos, J. Silva-Martinez, F. Maloberti, and E. SanchezSinencio, “A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 12, pp. 1391–1398, Dec 2000. J. Aguado-Ruiz, et. al., “Programmable capacitance scaling scheme based on operational transconductance amplifiers.” IET Electronics Letters, vol. 45, no. 3, pp. 159-161, Jan 2009. G.A. Rincon-Mora , “Active capacitor multiplier in Miller-compensated circuits,” IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 2632, Jan 2000. B. Razavi, Design of Analog CMOS Integrated Circuits, 2001 Mc Graw Hill, section 10, pp. 345. R. G. Carvajal, J. Ramírez-Angulo, A. López-Martin, A. Torralba, J. Galán, A. Carlosena, and F. Muñoz, “The flipped voltage follower: A useful cell for low-voltage low-power circuit design,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1276–1291, Jul. 2005. J. Ramírez-Angulo, et. al. “Comparison of conventional and new flipped voltage structures with increased input/output signal swing and current sourcing/sinking capabilities.” IEEE Mid. Symp. Circ. and Syst. 2005, MWSCAS’05, vol. 2, pp. 1151-1154, Aug 2005, Cincinnati, OH.

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