A Wide Dynamic Range CMOS Image Sensor With Dual Capture Using Floating Diffusion Capacitor Dongsoo Kim, Dongmyoung Lee, Youngcheol Chae, and Gunhee Han Department of Electrical and Electronic Engineering Yonsei University, 134, Sinchon-dong, Seodaemun-gu, Seoul, Korea Phone:+82-2-2123-7710, Fax:+82-2-312-4584 Email:
[email protected] Abstract—A wide dynamic range CMOS image sensor with dual capture using floating diffusion capacitor is proposed. The proposed structure performs dual capture without on-chip frame memories and the dynamic range of the proposed image sensor is controllable with dual electronic rolling shutter. The chip includes 320 (H) × 240 (V) effective pixels. Each pixel has 33% fill factor in an area of 5.6 × 5.6 µm2. The measurement results show that the dynamic range can be maximally expanded by 48 dB and the leakage voltage of the floating diffusion is 27% of the conventional contact metallization. The core area is 3000×2700 µm2 and total power consumption of the system is 12 mW with 3.3-V analog and 1.8-V digital supply voltages.
I.
This paper proposes a wide dynamic range CMOS image sensor with dual capture which does not need on-chip frame memories. The proposed dual capture structure stores the integrated signal of different exposure time in the floating diffusion (FD) capacitor instead of digital frame memory. The removal of the contact metallization between FD and source follower gate reduces the leakage current of FD capacitor and increases pixel fill factor. The dynamic range of the proposed image sensor can be controllable with dual electronic rolling shutter. In Section II, we present the pixel structure for dual capture. Section III describes the proposed system of wide dynamic range image sensor and dual electronic rolling shutter. In Section IV, the experimental results is presented. Lastly, we conclude in Section V.
INTRODUCTION
A wide dynamic range CMOS image sensor that is capable of capturing natural scenes without black level saturation and white crushing is a requisite for many applications such as automobile cameras, security cameras and consumer products. Numerous methods to expand the dynamic range of CMOS image sensor were reported in the literatures. The one of the well known techniques is using nonlinear response of the pixel devices or circuits. The use of logarithmic response [1], the combination of logarithmic and linear response [2], and photodiode capacitance adjusting [3] are well known. However, these approaches are disadvantageous in low signal-to-noise ratio (SNR) and large fixed pattern noise (FPN) [1-3]. The most common technique for wide dynamic range is the dual (multiple) capture technique with different exposure [4-7]. The conventional dual capturing techniques require large size onchip digital frame memories [4-6] or in-pixel overflow integration capacitor which considerably decreases the pixel fill factor [7]. In dual capture method, the dynamic range is decided by the ratio of short integration time (TS) to long integration time (TL) as blow DR = 20 log
Qmax TL Qmin TS
II.
PIXEL STRUCTURE FOR DUAL CAPTURE
Fig. 1 shows the schematic, the operation flow and the timing diagrams of the proposed pixel for dual capture. The pixel is composed of a pinned photodiode, a parasitic FD capacitor CFD, a floating gate capacitor CFG, and readout circuits such as a reset transistor, a transfer transistor, a source follower, and a selection transistor. The connection between FD node and source follower gate is made with a contact metallization in the conventional 4transistors/pixel structure. The contact metallization causes leakage current by the carrier trap in interface between silicon and contact and occupies large pixel area due to process design constraints of contact and metal. In the proposed pixel structure, as FD node and source follower gate is connected with not the contact metallization but poly-to-diffusion capacitor CFG, the leakage current of FD capacitor is decreased and the pixel fill factor is increased. CFG is overlap and fringe capacitances between source follower gate and FD as shown in Fig. 1 (a). The operation procedure is as follows. The photodiode generates electronic charge of an amount corresponding to the incident light intensity during short exposure time (b). The FD is reset by pulsing RST (c) and the integrated signal VSIG,S of short exposure time (TS) is transferred and stored in CFD (d). Then the photodiode is started to generate again the integrated signal VSIG,L of long exposure time (TL) before the readout turn
(1)
where Qmax is the maximum signal charge that can be handled in the pixel and Qmin is the minimum signal charge determined by the noise level and exposure time.
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(a) Proposed pixel schematic
Figure 2. Block diagram of the proposed wide dynamic CMOS image sensor
(b)
(c) (d) (e)
TS
(f)
(g)
(h)
TL
SEL TX
Figure 3. Block diagram of dual electronic rolling shutter
RST sig
VSIG,S VRST VSIG,L
nth row readout
VSIG,S VRST VSIG,L
III.
(n+1)th row readout
THE PROPOSED WIDE DYNAMIC IMAGE SENSOR AND DUAL ELECTRONIC ROLLING SHUTTER
(i) Timing diagram of the proposed pixel The proposed wide dynamic CMOS image sensor is composed of 320×240 pixel array, dual electronic rolling shutter, column readout circuits including single-slope ADC and SRAM array, readout control and 10bit counters as shown in Fig. 2. Readout circuits are located in even and odd column and the stored 10-bit data is outputted though MUX. Dual electronic rolling shutter is required to capture dual images having different exposure times in a frame readout timing as presented in Fig. 3. Dual electronic rolling shutter is composed of two rolling control units. One is for resetting FD and transferring VSIG,S from photodiode to CFD by pulsing RST and TX as shown in Fig.1 (c) and (d). The other is for outputting pixel signals (VSIG,S, VRST and VSIG,L) to column readout circuit by
Figure 1. Schematic, operation flow and timing diagram of the proposed wide dynamic range image pixel of the pixel comes (e). When the pixel transfers the pixel signals to column readout circuit, VSIG,S of CFD is transferred to column readout circuit by turning on the selection transistor (f). Next, the FD reset signal, VRST and the integrated signal, VSIG,L of TL are transferred sequentially to column readout circuit by pulsing RST (g) and TX (h). The VRST is used to eliminate the offset, switch charge injection, and noises including kT/C noise and low frequency noise using digital correlated double sampling (DCDS) by performing (VRST -VSIG,S) and (VRST -VSIG,L) [9].
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10b counter & driver
Readout circuits and SRAM
RST
10b counter & driver
Pinned photodiode (p+/n-/p-sub)
5.6 m
sig Pixel array 320*240
Mux
Dual rolling shutter
TX
(a) Readout circuits and SRAM
SEL
(b)
5.6 m
Figure 4. Microphotograph of the fabricated image sensor and layout of the wide dynamic pixel turning on RST, TX, and SEL as shown in Fig. 1 (f), (g) and (h). The two row control units revolve independently with a time interval. The time interval decides the short and the long exposure times, TS and TL. Therefore, the minimum TS is a column readout time and maximum TL is the (n-1) times of TS when n is the number of row. The dynamic range can be extended maximally by 20log(n-1). The transferred pixel signal, VSIG,S, VRST and VSIG,L are converted to digital data and stored in SRAMS, SRAMR, and SRAML, respectively. IV.
(c) Figure 5. The captured sample images from the fabricated chip at (a) short exposure time (b) long exposure time (c) synthesized wide dynamic range image
EXPERIMENTAL RESULTS
The proposed CIS system was designed and fabricated by 0.35-µm 2-poly 3-metal CMOS process. The microphotograph of the prototype image sensor and layout of the wide dynamic pixel are shown in Fig. 4. The proposed image sensor is integrated with QVGA (320×240) pixels and the pixel size is 5.6 µm × 5.6 µm. The photodiode is p+/n-/p-substrate pinned structure and fill factor is 33%. The core area is 3000×2700 µm2 and total power consumption of the system is 12 mW with 3.3V analog and 1.5-V digital supply voltages. The measured column FPN is 0.0073% of full code. Fig. 5 shows the captured sample images from the fabricated image sensors. The black level saturation at short exposure time and white crushing at long exposure time are occurred in normal image sensor mode as shown in Fig. 5 (a) and (b). However, the synthesized wide dynamic range image from dual captured images of the proposed image sensor does not have the white crushing around the light bulb or the black level saturation around the resolution chart in Fig. 5(c) The integrated signal of short integration is stored in the FD capacitor during long integration time and gives information about the highly illuminated region. The low leakage current is
Figure 6. Measured leakage voltage comparison of FD in contact metallization and proposed contactless floating gate a prerequisite for dual capture using FD capacitor. Fig.6 presents the leakage voltage comparison of FD node in the conventional contact metallization method and the proposed floating gate method. The measurement results indicate that the leakage voltage of the proposed contactless floating gate method is 27% of the conventional contact metallization method.
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TABLE I PERFORMANCE SUMMARY Process
0.35-µm CMOS 2-poly 3-metal
Core area
3 mmⅹ2.7 mm
Array format
320ⅹ240
Pixel size / Fill factor
5.6 µmⅹ5.6 µm / 33 %
ADC
Column-wise single-slope ADC
Dynamic range enhancement
Controllable with TS/TL (47 dB is increased maximally)
Video output
10 bit digital
Shutter
Dual electronic rolling shutter
Column FPN
0.0073 % of full code
Power supply
3.3 V (analog) / 1.8V (digital)
Power consumption
12 mW
[2] K. Hara, H. Kubo, M. Kimura, F. Murao, and S. Komori, “A linearlogarithmic CMOS sensor with offset calibration using an injected charge signal,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 354-355. [3] Y. Chae, K. Choe, B. Kim, and G. Han, "Sensitivity Controllable CMOS Image Sensor Pixel Using Control Gate Overlaid on Photodiode", IEEE Electron Device Lett., Jun. 2007. [4] M. Mase, S. Kawahito, M. Sasaki, S. Wakamori, "A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2787-2795, Dec. 2005. [5] M. Sasaki, M. Mase, S. Kawahito, Y. Tadokoro, "A Wide Dynamic Range CMOS Image Sensor with Multiple Short-Time Exposures," in Proc. IEEE Sensors, Vlenna, Oct. 2004. pp. 967-972. [6] O. Yadid-Pecht, E. R. Fossum, ”Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling,” IEEE Trans. Electron Devices , vol. 44, no. 10, pp. 1721–1723, Oct. 1997. [7] S. Sugawa, N. Akahane, S. Adachi, K. Mori, T. Ishiuchi, K. Mizobuchi, “A 100 dB dynamic range CMOS image sensor using a lateral overflow integration capacitor, in IEEE Int. SolidState Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 352- 353. [8] D. Kim, J. Kim, B. Hwang, D. Cho, K. Kim, S. Kim, J. Hong, J. Park, M. Lee, “Borderless contact leakage induced standby current failure onsub-0.15 µm CMOS device,” in Proc. The 8th Int. Symp. Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 2001, pp. 165-168. [9] S. Yoshihara, M. Kikuchi, Y. Ito, Y. Inada, S. Kuramochi, H. Wakabayashi, M. Okano, K. Koseki, H. Kuriyama, J. Inutsuka, A. Tajima, T. Nakajima, Y. Kudoh, F. Koga, Y. Kasagi, S. Watanabe, and T. Nomoto, "A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS image sensor with seamless mode change," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2006, pp. 492–493
Design specifications and performances of the proposed wide dynamic range CMOS image sensor are summarized in Table I. V.
CONCLUSION
This paper proposed a wide dynamic range CMOS image sensor with dual capture using floating diffusion capacitor. The proposed wide image sensor can capture dual image with different exposure times in one frame. The dynamic range is expanded maximally by 48 dB. The dual electronic rolling shutter can easily control the dynamic range with the time interval between the rolling control units. The experimental results show that the contactless source follower gate decreases the leakage current of 27% compared to the conventional contact metallization. The influence of the fixed charge in the floating gate capacitor can be eliminated by correlated double sampling. ACKNOWLEDGMENT This work was supported in part by the Ministry of Information Technology Research Center Support Program, and in part by Samsung Electronics Co. Ltd. REFERENCES [1] S. Decker, R. Mc Grath, K. Brehmer, and C. Sodini, “A 256 _ 256 CMOS imaging array with wide dynamic range pixels and columnparallel digital output,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 1998, pp. 176–177.
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