Centralized Adaptive Routing for NoCs - CiteSeerX

IEEE Computer Architecture Letters

Centralized Adaptive Routing for NoCs Ran Manevich1, Israel Cidon2, Avinoam Kolodny2 and, Isask'har Walter1 Electrical Engineering Department, Technion – Israel Institute of Technology, Israel 1 {ranman,zigi}@tx.technion.ac.il 2{cidon,kolodny}@ee.technion.ac.il Abstract— As the number of applications and programmable units in CMPs and MPSoCs increases, the Network-on-Chip (NoC) encounters diverse and time dependent traffic loads. This trend motivates the introduction of NoC load-balanced, adaptive routing mechanisms that achieve higher throughput as compared with traditional oblivious routing schemes that are perceived better suited for hardware implementations. However, an efficient adaptive routing scheme should base its decisions on the global state of the system rather than on local or regional congestion signals as is common in current adaptive routing schemes. In this paper we introduce a novel paradigm of NoC centralized adaptive routing, and a specific design for mesh topology. Our scheme continuously monitors the global traffic load in the network and modifies the routing of packets to improve load balancing accordingly. In our specific mesh-based design, XY or YX routes are adaptively selected for each sourcedestination pair. We show that while our implementation is scalable and lightweight in hardware costs, it outperforms distributed adaptive routing schemes in terms of load balancing and throughput. Index Terms— Network-on-Chip, routing algorithms, adaptive routing, load balancing.

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1 INTRODUCTION

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IEEE Computer Letters MANEVICHArchitecture ET AL.: CENTRALIZED ADAPTIVE ROUTING FOR NOCS



Fig. 2. Route selection circuit architecture for an 8X8 2D mesh. For every source-destination pair, the XY and YX path multiplexers select cells that belong to XY or YX paths respectively (up to 15 cells per path). Then, the sums of the load values over each path are compared and a bit is produced as a result. In the TLM above, modules (1,1) and (8,1) transmit to module (6,5) with a throughput of 1 and 2, taking the XY path. For both cases, the path selection circuit will produce “0”which indicates that YX path is less congested.

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