Chap. IV –CMOS Operational Amplifiers

Chap. IV –CMOS Operational Amplifiers n IV.1 Introduction n IV.2 Performance parameters n IV.3 OTA (single-stage op amp) n IV.4 Cascode and folded-cascode amplifiers n IV.5 Cascade amplifiers n IV.6 Fully-differential amplifiers and common-mode

feedback

EEL 6713 - Analog Integrated Circuit Design

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IV.1 Introduction The ideal op amp +

A→∞ RS=0

+ RS

vi

+ Avi -

-

-

+

+

vi -

+ vo -

Gm=AGS Gmvi

GS

+ vo -

EEL 6713 - Analog Integrated Circuit Design

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IV.1 Introduction Applications of op amps - 1 Inverting amplifier

R2 + vi -

R1

+ vo -

+

-

+ vi -

+

1 R ≅− 2 R1 1 R  1 + 1 + 2  A R1 

Noninverting amplifier

R2 R1

vo R =− 2 vi R1

+ vo -

vo  R2  R 1 = 1 +  ≅ 1+ 2 vi  R1  R1 1 R  1 + 1 + 2  A R1 

EEL 6713 - Analog Integrated Circuit Design

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IV.1 Introduction Applications of op amps - 2 Transimpedance amplifier

R2

i

+

+ vo -

vo A  1 = − R2 ≅ − R2  1 −  ≅ − R2 1+ A i  A

- Continuous-time filters - SC filters - D/A & A/D converters - Sensor signal conditioning - Voltage & current references - Comparators - Nonlinear analog functions, - ....... EEL 6713 - Analog Integrated Circuit Design

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IV.1 Introduction Op amp requirements: •Technology; •Supply voltage; •Gain, GBW, output swing, noise, offset voltage, PSRR, ICMR, ....

Op amp design: •Choice of architecture; •Bias currents & Transistors dimensions; •Compensation; •Simulation; •Layout; •Post-layout simulation

P. Allen and D. Holberg – CMOS Analog Circuit Design, 2nd. Ed., Oxford, New York, 2002. EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 1

Gate channel capacitances are used for compensation capacitors.

W.-C. S. Wu et al., Digital-Compatible HighPerformance Operational Amplifier with Railto-Rail Input and Output Ranges, IEEE JSSC, vol. 29, no. 1, pp. 63-66, Jan. 1994. EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 2

Op Amp fabricated by MOSIS service in 2-µm, n-well CMOS, DPDM L. Moldovan and H. H. Li, A Rail-to-Rail, Constant Gain, Buffered Op-Amp for Real Time Video Applications, IEEE JSSC, vol. 32, no. 2, pp. 169-176, Feb. 1997 EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 3

J. F. Duque-Carrillo et al., 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology, IEEE JSSC, vol. 35, no. 1, pp. 33-44, Jan. 1990 EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 4 Offset voltage Vod(V)

VOS

Vid(mV)

Systematic offset – results from circuit design and is present even when all supposedly identical devices are matched (usually can be set to a low value). Random offset – results from mismatches in supposedly identical pairs of devices (depends on area and bias). P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design – A Tutorial Overview, IEEE JSSC, vo. 17, n0. 6, pp. 969-982, Dec. 1982. EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 5 Differential voltage gain Ad

dB

Extrapolated unitygain frequency

0 dB

− p1

P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design – A Tutorial Overview, IEEE JSSC, vo. 17, n0. 6, pp. 969-982, Dec. 1982. EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 6 Settling time

P. Allen and D. Holberg – CMOS Analog Circuit Design, 2nd. Ed., Oxford, New York, 2002. EEL 6713 - Analog Integrated Circuit Design

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IV.2 Performance parameters - 7 CMRR, PSRR, Slew rate, Noise, Common-Mode Input Range, Output Swing, Power, Silicon Real State, .... Dynamic Range (DR)

Distortion (within acceptable level: application-dependent).

 vin ,max DR = 20 log  v  in ,min

  

Noise (distinguish between signal and noise) EEL 6713 - Analog Integrated Circuit Design

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IV.3 OTA (single-stage op amp) - 1 Or current-mirror op amp (Johns & Martin) /symmetric OTA (Laker & Sansen)

1:B CM

1:B CM I1 I2

BI1

+ vG1 -

M1

M2

+ vG2 -

IT VSS

BI1

BI2 Io= B(I2-I1) CL

1:1 CM EEL 6713 - Analog Integrated Circuit Design

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IV.3 OTA (single-stage op amp) - 2 Bias circuitry

Low-gain diff. amp.

Cascode output

Fig. AP6-1

K. Laker and W. Sansen: Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994

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IV.3 OTA (single-stage op amp) - 3

D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.

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IV.3 OTA (single-stage op amp) - 4 1:B CM

1:B CM

Input common-mode range: see diff. amp.

I1 I2 BI1

+ vG1 -

M1

M2

BI2

+ vG2 -

Io= B(I2-I1)

IT asymmetry

CL

BI1

VSS

SR =

BIT ( CL + CP )

Bg m1 Ro Ad ( s ) = 1 + sRo ( CL + CP )

GBW ( Hz ) =

1:1 CM

Bg m1 1 2π ( CL + CP )

CM delays were neglected −Bgm1vid

Ro

CL+CP

+ vo

vid = v g1 − vg 2 EEL 6713 - Analog Integrated Circuit Design

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IV.4 Cascode & folded-cascode amplifiers - 1 - Reduced output swing; -Doublet ! - Not applicable to low supply voltage.

Telescopic diff. amp. with self-biased cascode CM

Telescopic diff. amp. with high-swing cascode CM EEL 6713 - Analog Integrated Circuit Design

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IV.4 Cascode & folded-cascode amplifiers - 2

Low-gain diff. amp. D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.

High-gain diff. amp.

EEL 6713 - Analog Integrated Circuit Design

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IV.4 Cascode & folded-cascode amplifiers - 3

P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

EEL 6713 - Analog Integrated Circuit Design

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IV.4 Cascode & folded-cascode amplifiers - 4 Folded-cascode amplifier - 1 Can be changed to increase positive output swing

IT ∆i IT/2 IT/2

IT/2

IT/2

∆i ∆i

∆i IT

P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

2∆i

∆i

IT

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IV.4 Cascode & folded-cascode amplifiers - 5 Folded-cascode amplifier - 2 ICMR : Exercise Output swing : Exercise Note: The output swing can be around -VSS+2VDSsatp to VDD-2VSDsatp for high-

Ro

swing current mirror and optimized bias.

IT CL Ad 0 Ad ≅ 1 + sCL R0 SR ± = ±

High-swing current mirror P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

& doublet

Gm = g m1 Ad 0 = Gm Ro g 1 Go = = g ds 4 ds 4 A Ro g ms 4 A + ( g ds12 + g ds 2 )

EEL 6713 - Analog Integrated Circuit Design

g ds 2 A g ms 2 A 21

IV.4 Cascode & folded-cascode amplifiers - 6 The gain-boost technique - 1  g + g ds 2  g mg 2  n + Add + ds1   g mg 2   1 ≅ Add g mg 2 1 Ro = g ds 2 g ds1 g ds 2 g ds1

Stacked devices reduce output swing. Cascade amplifiers: stability?

K. Bult & G.J.G.M. Geelen, A fast-settling CMOS op amp for SC circuits with 90-dB DC gain, IEEE JSSC, no.6, pp. 1379-1384, Dec. 1990. EEL 6713 - Analog Integrated Circuit Design

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IV.4 Cascode & folded-cascode amplifiers - 7 The gain-boost technique - 2

P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

EEL 6713 - Analog Integrated Circuit Design

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IV.4 Cascode & folded-cascode amplifiers - 8 The gain-boost technique - 3

P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 1 VDD 1:1

ICMR: see diff. amp. 1:2B

M3

Output swing:

M6

M4

VDD − VDSsat 4 > Vo > VSS + VDSsat 5 vo CL

CC inv

IT

+ vi -

noninv

M1

M2

Low-voltage gain:

1:2B

M8 1:1

For systematic offset → 0. “Early” effect at the output

M5

M7

Ado =

1:B

vo vi

=− LF

g m1 g m6 g ds 2 + g ds 2 g ds 6 + g ds 7

VSS EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 2 CC

+ vi -

vx

GmI

Io2 -AdII

Io1

d ( vo − vx ) dvo dvo IT I o1 = CC ≅ CC → = dt dt dt CC Io2

dvo dvo I o2 − I o1 = I o1 + C L → = dt dt CL

The output node can be the SR limiting node*

vo CL

IT SR = ± CC I 6max − ( B + 1) I B + SRext ≅ > SR + CL ( B − 1) IT − SRext = − CL ±

*For a discussion, see Laker & Sansen, pp. 510-512 EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 3 Amplitude x frequency limitation due to SR

dvo ≤ SR; dt

vo = A sin ω0t ;

dvo dt

= Aω0 ≤ SR max

Amplitude limitation

SR-limited slope

J. Dostál, Operational Amplifiers, 2nd. Ed., Butterworth-Heinemann, Boston, 1993.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 4

A( s) Vo s = ( ) Vin 1 + A ( s) F ( s ) Determines the poles of the closed-loop system Allen & Holberg, 1st ed.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 5 The op amp design must take into account both load and feedback loop

jω

s-plane x

p2

x

1 − RII CII

x

1 − RI CI

Allen & Holberg, 1st ed.

x

p1

σ

φM EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 6 Response of second order system with various phase margins

Allen & Holberg, 1st ed.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 7 Equivalent differential circuit

CC

vin

+

+

+ CI

RI

gmIvin

RII

gmIIvI

CII

g mI = g m1

vo -

-

-

RI = ( g ds 2 + g ds 4 )

vI

If CC→0, then −1

CI = Cdb 2 + Cdb 4 + Cgb 6 + Cgs 6

g mII = g m 6 RII = ( g ds 6 + g ds 7 )

Vo g mI g mII RI RII (s) ≅ − Vin (1 + sRI CI )(1 + sRII CII ) Poles relatively close → phase margin can be low or even negative !!!

−1

CII = Cdb 6 + Cdb 7 + CL

Exercise: Derive the transfer function Ad(s) of the compensated operational amplifier EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 8 Compensated operational amplifier

Ad 0 (1 − s z ) Vo s = − ( ) Ad 0 = g mI g mII RI RII Vin (1 − s / p1 )(1 − s / p2 ) 1 1 p1 ≅ − ≅− RI ( CI + CC ) + RII ( CII + CC ) + g mII RI RII Cc g mII RI RII Cc

Ad ( s ) =

p2 ≅ −

g mII Cc g ≅ − mII CI CII + CC ( CI + CII ) CII

jω

z=

g mII Cc

s plane

pole splitting x

p2 Note:

x

1 − RII CII

x

1 − RI CI

2π GBW = Ad 0 p1 = g mI / CC SR = IT / CC

x z=

p1

SR = ( IT / g mI ) = nφt 2π GBW

EEL 6713 - Analog Integrated Circuit Design

σ

g mII Cc

(

)

1+ if +1

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IV.5 Cascade amplifiers Two-stage amplifiers - 9 s-plane

σ z=

x

p1

x

p2

g mII Cc

2π GBW ≅

g m1 CC

jω

To avoid low phase margin, choose p2 , z > 2π GBW φM ≅

 2π GBW π − tan −1  2  − p2

 −1  2π GBW   − tan   z   

 g m1 (CI CII / CC + C I + CII )    g C m 6 C  

 g m1    g m 6   EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 10 Simplified model for noise analysis (input-referred noise current source not accounted for)

2 enII

2 oI

vo

2 nI

v 2 e = Ad ∆f ∆f

2 2 voII 2 enII = AvII ∆f ∆f

enI2 compensation

Ad is the op amp voltage gain AvII is the voltage gain relative to the second noise source. For the calculation, account for the output impedance of the first stage and compensation network) Laker & Sansen’s book

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 11

1st stage

Ad

AvII

2nd stage

Open-loop output noise of a Miller OTA K. Laker and W. Sansen: Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994

NOTE: white noise only EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 12 This connection reduces the feedforward current through C when comparing to connecting C to node Y

Two-stage CMOS op amp with a cascode current mirror load in the input stage P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 13

CMOS two-stage op amp using nulling resistor compensation P. Allen and D. Holberg – CMOS Analog Circuit Design, 2nd. Ed., Oxford, New York, 2002.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifiers - 14 CMOS two-stage op amp using nulling resistor compensation

p1 ≅ −

1 g mII RI RII Cc

g mII Cc g p2 ≅ − ≅ − mII CI CII + CC ( CI + CII ) CII

p3 = −

1 Rz CI

z=−

1 Cc ( Rz − 1/ g m 6 )

High-frequency pole

Placing z on top of p2:

Rz =

1  Cc + CII  g m 6  Cc

 1  Cc + CL  ≅    g C m6  c  

Determined by source/drain and gate voltages, and W/L P. Allen and D. Holberg – CMOS Analog Circuit Design, 2nd. Ed., Oxford, New York, 2002.

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifier: design equations - 1 VDD

1:1

SR = IT / CC

1:2B

M3

M6

M4

2π GBW = Ad 0 p1 = g mI / CC vo CL

CC inv

IT

+ vi -

M8 1:1

z=

noninv

M1

M2

M5 VSS

p2 ≅ −

g mII Cc g ≅ − mII CI CII + CC ( CI + CII ) CII

g mII Cc

Ad 0 = Ad 1 Ad 2 M7 1:B

g m1 Ad 1 = g ds 2 + g ds 4 gm6 Ad 2 = g ds 6 + g ds 7

EEL 6713 - Analog Integrated Circuit Design

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IV.5 Cascade amplifiers Two-stage amplifier: design equations - 2 VDD

1:1

VICM max =

1:2B

M3

VICM min =

M6

M4

See diff. amp.

vo −VSS + VDSsat 7 < Vo < VDD − VDSsat 7 CL

CC inv

IT

+ vi -

noninv

M1

M8 1:1

M2

M5

CMRR, noise (white & 1/f), PSRR±, (random) offset voltage, M7 1:B

VSS EEL 6713 - Analog Integrated Circuit Design

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