Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~
2010, John Wiley. 9-1. Chapter 9: Sequential Logic. Modules. Department of ...
Chapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin
Department of Electronic Engineering National Taiwan University of Science and Technology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
9-1
Chapter 9: Sequential Logic Modules
Syllabus
Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
9-2
Chapter 9: Sequential Logic Modules
Objectives After completing this chapter, you will be able to: Describe how to model asynchronous and synchronous D-type flip-flops Describe how to model registers (data register, register file, and synchronous RAM) Describe how to model shift registers Describe how to model counters (ripple/synchronous counters and modulo r counters) Describe how to model sequence generators Describe how to model timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
9-3
Chapter 9: Sequential Logic Modules
Syllabus
Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley