Chapter 9: Sequential Logic Modules - Wiley

Chapter 9: Sequential Logic Modules

Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin

Department of Electronic Engineering National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Syllabus ™ ™ ™ ™ ™ ™ ™ ™

Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Objectives After completing this chapter, you will be able to: ™ Describe how to model asynchronous and synchronous D-type flip-flops ™ Describe how to model registers (data register, register file, and synchronous RAM) ™ Describe how to model shift registers ™ Describe how to model counters (ripple/synchronous counters and modulo r counters) ™ Describe how to model sequence generators ™ Describe how to model timing generators Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Syllabus ™ ™ ™ ™ ™ ™ ™ ™

Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Basic Sequential Logic Modules ™ ™ ™ ™ ™ ™ ™ ™ ™ ™ ™

Synchronizer Finite state machine Sequence detector Data register Shift register CRC generator Register file Counters (binary, BCD, Johnson) Timing generator Clock generator Pulse generator

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Options for Modeling Sequential Logic ™ ™ ™ ™ ™

Behavioral statement Task with delay or event control Sequential UDP Instantiated library register cell Instantiated modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Syllabus ™ ™ ™ ™ ™ ™ ™ ™

Objectives Fundamentals of sequential logic modules Flip-flops Memory elements Shift registers Counters Sequence generators Timing generators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley

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Chapter 9: Sequential Logic Modules

Asynchronous Reset D-Type Flip-Flops // asynchronous reset D-type flip-flop module DFF_async_reset (clk, reset_n, d, q); … output reg q; always @(posedge clk or negedge reset_n) if (!reset_n) q