CIC Filter Theory in DDC and Implementation by ...

WUJNS

Vol . 9 No. 6 2004 899-903

Wuhan University Journal of Natural Sciences

Article ID : 1007-1202(2004) 06-0899-05

CIC Filter Theory in DDC and Implementation by Using FPGA

◆ MA Zhi-gang , WEN Bi-yang , ZHOU Hao , BAI Li-yun School of Electronic Information, Wuhan University , Wuhan 430072, Hubei , China

Abstract :Cascade Integrator Comb(CIC)filter is the main part of the next generation High Frequency (HF)radar .This paper describes the key points of CIC theory in the Digital Down Conversion (DDC)module of a radar receiver , and takes advantage of the high flexibility and high density feature of Field Programmable Gate Array (FPGA)for putting forth to design the CIC filter by using FPGA .This paper provides particular insight into design by FPGA , which has advantages in high speed operation and simply structure .Some important and practical applications are given in this paper .The simulation result proves the validity and veracity . Because we can adjust the parameters freely according to our need, the CIC filter can be adapted to the next generation HF radar . Key words :FPGA ;DDC ;CIC filter ;HF radar CLC number : TN 47

0　Introduction s data converters become faster and faster , the application of CIC filter is becoming more and more important[ 1] .The CIC filters are ideal for many of the building blocks of digital communications , and are multirate filters used for realizing large sample rate in digital system . CIC filters are multiplier-free structures, consisting of only adders , subtracters and registers .They are typically employed in applications that have a large excess sample rate .That is , the system sample rate is much larger than the bandwidth occupied by the signal . CIC filters are frequently used in DDC and Digital up Conversion ( DUC).Because applying the software radio technique to design a universal hard platform is the main scheme of next generation HF radar[ 2 , 3] , CIC filter has been a key precondition in our DDC module design of radar receiver .In order to make the DDC module suit with our HF fadar system , we must design the CIC filter by ourselves according to our need . In order to adjust the parameters freely , we make use of the [ 4] highly flexible and highly integrated FPGA to realize our design . In this paper , we sum up the theory key points and try to realize the design by FPGA[ 5] .Also , the simulation result proves the validity .

A

1　Theory of Operation Received date :2004-06-10 Foundation item :Support ed by the 863 High Technology Project of China (2001AA631050) Biography:MA Zhi-gang (1978-), male , Ph . D candidat e, research direction :software radio and EDA design. E-mai l : ad-xmg@263. net To whom correspondence should be addressed .E-mai l :bywen @whu . edu . cn

Wuhan University Journal of Natural Sci ences 　Vol . 9　No. 6　2004

The two basic building blocks of a CIC filter are an integrator [ 6] and a comb .The integrator is simply a single-pole infinite impulse response (IIR)filter with a unity feedback coefficient , it can be described by the following equation : y(n)=y(n -1)+x(n) ( 1)

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　　In the Eq .( 1), x(n)is the input , and y(n)is the output .The output delayed by one unit of time is y(n -1). This system is also known as an accumulator .The transfer function for an integrator on the z-plane is : HI (z)=

1 1 -z -1

( 2)

　　The comb filter is a symmetric finite impulse response ( FIR)filter described by Eq .(3): y(n)= x(n)-x(n -RM)

( 3)

　　In Eq .(3), M is design parameter and is called the differential delay .M can be any positive integer , but it is

Fig. 1 　CIC filter frequency response for D =100

usually limited to 1 or 2 . And R is decimating parameter and is called the order of CIC filter .The corresponding transfer is Hc (z)=1 -z

-RM

( 4)

[ 7]

the single stage CIC filter is about 13 . 46 dB

.So , the

stopband droop is worse .In order to resolve this situation , we

　　If M is defined to 1 , the R is not only the decimation

can increase the stage number of CIC filter .With the stage of

gene , but also is the order of CIC filter , we can use D to de-

the CIC filter increasing , the stopband droop will also in-

fine it .Hence the system transfer function for the composite

crease .So the system transfer function of N stage CIC filters

CIC filter is :

is :

H 1(z)=

N

N

N

H(z)= H 1 (z)= HI (z)Hc (z)

1 (1 -z -D )=HI (z)Hc (z) ( 5) 1 -z -1

(1 -z -RM)N -1 N = (1 -z )

　　CIC filter has a lowpass frequency characteristic .The

D -1

∑z

-K N

( 7)

k =0

frequency response is obtained by evaluating Eq .( 5)at z =

　　And the frequency characteristics of N stage CIC filter

e jw , so the total frequency response is :

are :

H 1( e j w)=HI (e jw)Hc(ej w) =sin(w D/ 2)· sin-1(w/2) -1

=DSa (w D/2)S ( a w/ 2)

-1

jw

H( e )=[ sin(w D/ 2)· sin (w/2) ] =D NSNa (w D/2)NS a -Nw/ 2

N

( 8)

( 6)

　　When we build a N stages CIC filter , we cascade , or

sin(x) 　　In the Eq .( 6), S a(x)= is sample function . x Fig . 1 shows the frequency characteristics of CIC filter .

chain output to input , N stages integrator sections together

　　From the Eq .( 6), we can see the stopband droop of

with N stages comb sections .Fig . 2 shows N stages decimation CIC filter :

Fig. 2　N stages decimation CIC filter structure

　　From Fig . 2 , we can see there is a rate change switch between the two filter sections .The decimation subsamples

fore , a CIC filter also has a linear phase response and constant group delay .

the output of the last integrator stage , reducing the sample rate from fs to f s/ D . Eq .( 7)shows that even though CIC filter has integrators in itseff , which have an infinite impulse response by

2 　CIC Filter Implementation by FPGA

themselves, it is equivalent to N stages FIR filters , each

This section presents design considerations for CIC filters by using FPGA .Everybody has his or her own favorite way of

having a rectangular impulse response .Since all of the coefficients of these FIR filters are unity and symmetric , there-

designing[ 8, 9] .Now we will simulate the filters in Matlab . After we had simulated the filter in Matlab , we can realize it by

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MA Zhi-gang et al :CIC Filter Theory i n DDC and Implement…

Hardware Design Language ( HDL).The filter port definitions

delay of the integrator section is RESULT_DELAY cycles .If

are provided in Table 1.

there is a new input to the integrator section (ND is asserted), a new result is calculated , and stored in the result array

Table 1 　CIC filter ports and definitions

to be delayed by RESULT_DELAY cycles .The valid array records if a valid value is stored in the corresponding position

Signal name

Direction

Description

CLK

Input

CLOCK master clock (active rising edge)

DIN

Input

DATA INPUT B-bit wide filter input port .

Input

NEW DATA (active high)When this signal is asserted the data sample presented on the DIN port is loaded into the filter .

STAGES cascaded subtractors .Each subtractor subtracts a

Output

FILTER OUTPUT SAMPLE W-bit wide filter output sample bus.

layed 1 or 2 cycles .The total delay of the comb section is

Output

FILTER OUTPUT SAMPLE READY (active high) indicates that a new filter output sample is available on the DOUT port .

section ( ND is asserted), a new result is calculated , and

Output

READY FOR DATA-(active high) indicate when the filter can accept a new input sample .

ND

DOUT

RDY

RFD

Now , we can define the interface , control and timing of CIC filter . ND ( New Data), RFD(Ready for Data)and RDY (Ready)are used to coordinate I/O operations .The filter

of the result array .In every clock cycle , the resultptr is updated to check if a result is now available to be output from the integrator section .The comb section consists of C_ delayed input from its current input .The input may be deRESULT_DELAY cycles .If there is a new input to the comb stored in the result array to be delayed by RESULT_DELAY cycles .The valid array records if a valid value is stored in the corresponding position of the result array .In every clock cycle, the resultptr is updated to check if a result is now available to be output from the comb section .For the downsample , the first data input ( when ND is asserted)is passed

output status signal RFD signals to the system that the filter is ready for data .RFD is active high .Asserting ND high indi-

to data out , and RDY is asserted .The next C_SAMPLE_

cates to the filter the availability of a new input sample on the DIN port .ND is very similar in functionality to the clock en-

asserted .According to the method what we have said above ,

able signal found on many very large scale integrated-circuit ( VLSI)devices .The RDY output signal indicates that a new filter output samples is available on the DOUT port .The interface signals will typically be used in the following manner . Our system will first wait for RFD =1 , this signals that a new input sample can be written to the filter .The new input sample will be placed on the DIN port and ND will be placed in the active state ( ND =1)for a single clock cycle .Asserting ND indicates to the filter that it should sample the DIN port . The filter will sample DIN on the rising edge of the clock ( CLK)qualified with ND =1 . A filter read operation can occur when the filter asserts RDY =1 .RDY will be used as a clock enable signal for down-stream processing block which is consuming the filter output samples . Then, we will show the design method .In the DDC , each kind of CIC filter consists of three parts . The decimating filter is made up of an integrator , a down sample and a comb . Hook these sections together , with the output of one section becoming the input to the next section .The output of the last section is the output of the filter .The integrator section consists of C_STAGES cascaded accumulators .The total Wuhan University Journal of Natural Sci ences 　Vol . 9　No. 6　2004

RATE_CHANGE-1 inputs are ignored , and RDY remains dewe can easily implement the system by using FPGA easily .

3　Design Examples and Simulation Result When we finish the design , there are several parameters we can adjust , which are R( decimate gene), M( differential delay)and N( the stage number of CIC filter). So we can adjust these parameters according to our need in order to meet the design request .All of these can improve the functional agility of CIC filter in different design . Fig . 3 shows the top structure of CIC filter , one can see the symbol of CIC filter ;there are several interfaces we have defined as above . 　　In order to validate the design , we first input an integer series which is from 1 to 100, then we set parameters .Firstly , we set the R =8, M =1, N =1, we can check up the result from simulation result .For the single stage decimation , we can

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Now we get a chirp signal , whose sample rate fs is 500 kHz , sweep width B is 20 kHz .In order to validate our design , we should send this signal to our designed system .One can set different parameters in our system .Here , we set R =3 , M =1 , N =5 in CIC filter , and then get data from output and deal with it by Matlab . Fig. 3　The top structure of CIC filter

calculate the sum of the input integer series and export the result according to the decimation gene . So the CIC filter can finish the decimation and filter .Fig .4 shows the simulate result of this example . 　　Then , we can set R =4 , M =1 , N =2 , also ,we can check the simulation result .For the two stages decimation , we can calculate the filter coefficient as below : h(0)=h(6) =1 ;h(1)=h( 5)=2 ;h( 2)=h( 4)=3 ;h( 3)=4 .Then we can calculate the output result .Fig . 5 shows the simulate result of this example . 　　In our HF radar system , the input signal is chirp signal , so we use a chirp signal as our simulate signal .

　　From the Fig . 6 and Fig . 7 , we can see the signal frequency spectrum has no change , but expands in frequency domain , which is caused by decimation[ 10] .The expansion may cause aliasing in frequency domain , so we should design an anti-aliasing filter before decimation , which is the purpose for us to design CIC filter too .We should adjust R , M and N to avoid aliasing . In any filter design , the most significant bit ( MSB)of these filters is considered as a function of the overall register growth . For CIC decimations, the CIC datapath undergoes internal register growth that is a function of all the design parameters: N ,

D,

in

addition

to

the

input

precision B i n .So if B in is the number of input bits , the

Fig. 4　The simulate result of CIC filter for R =8, M =1, N =1

Fig. 5 　The simulation result of CIC filter for R =4, M =1 , N=2

Fig. 6　Input chirp signal

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Fig. 7　Output chirp signal from CIC filter

MA Zhi-gang et al :CIC Filter Theory i n DDC and Implement…

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most significant bit B max at the filter output is defined by Eq . ( 9) B max =[ Nlog2 D +B in -1]

( 9)

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◆

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