Circuits for Low Power Digital Signal Processing - CiteSeerX

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Circuits for Low Power Digital Signal Processing Simone Gambini, Melinda Ler,Marghoob Mohiyuddin

Abstract It is predicted that at the 90nm technology node, leakage power will exceed dynamic power. This poses several challenges to high-speed circuit designers. By the same token, the complexity of low power, low operating frequency designs is threatened more and more by static power dissipation concerns. It has been recently shown [1][2] that if energy per operation (EOP) is used as an optimization metric, then for a given microarchitecture, an optimal choice of Vdd exists. However, throughput constraints are considered in this design only a-posteriori, and are not included in the optimization problem. In this project, we aim to extend these results, bringing architectural considerations in to the game. The design and implementation of a digital filter, running at frequencies in the 1-10 MHz range, to be used as a decimator in a sigma-delta modulator, will be used a case study. Different architectural solutions (FIR, IIR, serial) will be compared from the point of view of the optimal-EOP V dd point, the goal being to design a filter architecture that can run at the optimal EOP point, while at the same time meeting the required throughput constraints. In addition, we will also investigate scalability of such attempt as we increase the operating frequency beyond the 1-10Mhz range. Designs obtained through this process will also be compared to the designs synthesized using a convex-optimization based tool.

P ROJECT O UTLINE Broadly speaking, the project will have the following steps: 1) Library characterization of the Vdd –tp curves of inverters, 2 and 3 input NAND gates (to consider the effect of stacking), EOP-optimal point in a multi-threshold technology, temperature and process corner dependency of the EOP-optimal point. 2) Architecture modeling: Estimating the complexity and clock frequency requirements of different architectures, pipelining/parallelization effect. 3) Architecture level EOP-optimal design. 4) Comparison with fully automated synthesis. 5) Physical design. R EFERENCES [1] A.Wang,A.Chandrakashan A 180mV FFT Processor Using Subthreshold Circuit Techniques in Proc.ISSCC 2004 [2] B.Calhoun and A.Chandrakashan Ultra-Dynamic Voltage Scaling using subthreshold operation and local voltage dithering in 90nm CMOS in Proc.ISSCC 2005 [3] D.Markovic Methods for True Energy-Performance Optimization JSSC August 2004 [4] E.Vittoz Subthreshold Logic for ultimate-low power design in Low-Power Electronics Edited By C.Piguet CRC Press,Nov.2004