CM-iGT Reference Guide. 5. Table 1 Revision Notes. Date. Description. February
2013. First release. Please check for a newer revision of this manual at ...
CM-iGT CoM Reference Guide
Introduction
© 20133 CompuLab Ltd. All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means whether, electronic, mechanical, or otherwise without the prior written permission of CompuLab Ltd.. No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by CompuLab Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. CompuLab Ltd. reserves the right to change details in this publication without notice. Product and company names herein may be the trademarks of their respective owners. CompuLab Ltd. Ha-Yetzira 17, Yokneam Ilit 26290, Israel Tel: +972 (4) 8290100 http://www.compulab.co.il Fax: +972 (4) 8325251
Revised February 2013
CM-iGT Reference Guide
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Table of Contents
Table of Contents 1
INTRODUCTION .............................................................................................................. 6 1.1 1.2 1.3
2
OVERVIEW ........................................................................................................................ 7 2.1 2.2 2.3
3
About This Document ...................................................................................................... 6 CM-iGT Part Number Legend ......................................................................................... 6 Related Documents .......................................................................................................... 6
Highlights ......................................................................................................................... 7 Block Diagram ................................................................................................................. 8 CM-iGT Features ............................................................................................................. 9
CORE SYSTEM COMPONENTS .................................................................................. 11 3.1 AMD Embedded G-Series APU .................................................................................... 11 3.1.1 CPU Core .............................................................................................................. 11 3.1.2 GPU Core .............................................................................................................. 11 3.2 DRAM ............................................................................................................................ 11 3.3 SPI Flash or Boot ROM ................................................................................................. 11 3.4 iSSD ............................................................................................................................... 12
4
PERIPHERAL INTERFACES ....................................................................................... 13 4.1 Display Interface ............................................................................................................ 14 4.2 Gigabit Ethernet ............................................................................................................. 15 4.2.1 Primary Gigabit Ethernet ...................................................................................... 15 4.2.2 Secondary Gigabit Ethernet .................................................................................. 16 4.3 PCI Express .................................................................................................................... 17 4.4 SATA ............................................................................................................................. 18 4.5 USB ................................................................................................................................ 19 4.6 CAN Bus ........................................................................................................................ 19 4.7 Audio .............................................................................................................................. 20 4.7.1 Analog and Digital Audio ..................................................................................... 20 4.7.2 High Definition Audio Interface ........................................................................... 20 4.8 LPC - Low Pin Count Interface ..................................................................................... 20 4.9 Serial Ports ..................................................................................................................... 21 4.9.1 UART .................................................................................................................... 21 4.9.2 RS232 .................................................................................................................... 21 4.10 GPIO and GEVENT .................................................................................................. 22 4.11 SMBUS ..................................................................................................................... 23
5
SYSTEM LOGIC .............................................................................................................. 24 5.1 Power Management........................................................................................................ 24 5.1.1 Power Rails ........................................................................................................... 24 5.1.2 System Signals and Power Sequence .................................................................... 24
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Table of Contents
5.2 5.3 5.4 6
BASEBOARD INTERFACE ........................................................................................... 26 6.1 6.2 6.3 6.4
7
Connector Pin-out .......................................................................................................... 26 Connector Type .............................................................................................................. 28 Mechanical Drawings..................................................................................................... 29 Standoffs ........................................................................................................................ 30
OPERATIONAL CHARACTERISTICS ....................................................................... 31 7.1 7.2 7.3 7.4 7.5 7.6 7.7
8
Unconnected Pins ........................................................................................................... 25 System Boot Options ..................................................................................................... 25 TPM ............................................................................................................................... 25
Absolute Maximum Ratings .......................................................................................... 31 Recommended Operating Conditions ............................................................................ 31 DC Electrical Characteristics ......................................................................................... 31 Power Consumption ....................................................................................................... 31 ESD Performance ........................................................................................................... 31 Thermal Characteristics ................................................................................................. 31 Operating Temperature Ranges...................................................................................... 32
APPLICATION NOTES .................................................................................................. 33 8.1 Baseboard Design Guidelines ........................................................................................ 33 8.2 Baseboard Troubleshooting ........................................................................................... 33 8.3 Ethernet Magnetics Implementation .............................................................................. 34 8.3.1 Magnetics Selection .............................................................................................. 34 8.3.2 Magnetics Connection .......................................................................................... 34 8.4 Heat-plate Integration..................................................................................................... 34
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Revision Information
Table 1
Revision Notes
Date February 2013
Description First release
Please check for a newer revision of this manual at CompuLab web site – http://www.compulab.co.il/. Compare the revision notes of the updated manual from the web site to those of the printed or electronic version you have.
Revised February 2013
CM-iGT Reference Guide
5
Introduction
1
INTRODUCTION
1.1
About This Document This document is part of a set of reference documents providing information necessary to operate and program CompuLab CM-iGT Computer-on-Module.
1.2
CM-iGT Part Number Legend For CM-iGT part number legend, please refer to the ‘Pricing and Ordering Info’ section at CompuLab website: https://compulab.co.il/products/computer-on-modules/cm-igt/#ordering .
1.3
Related Documents For additional information, refer to the documents listed in Table 2. Table 2
Related Documents Document
CM-iGT Developer Resources
Revised February 2013
Location https://compulab.co.il/products/computer-onmodules/cm-igt/#devres
CM-iGT Reference Guide
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Overview
2
OVERVIEW
2.1
Highlights · · · · · · · · · · ·
Revised February 2013
AMD G-Series Fusion dual-core 64 bit x86 CPU, up to 1.65GHz Up to 4GB DDR3 Up to 32GB on-board SSD storage AMD Radeon HD 6250 GPU Universal Video Decoder, 1080p Blu-Ray playback support Graphics controller with dual-head support. Up to 1920x1200 at 60 Hz resolution HDMI, DisplayPort, LVDS and VGA interfaces GbE x 2, PCIe x 6, SATA x 5, USB x 9, RS232, UART, CAN, GPIO x 29, SMBus x 2, LPC Linux, Windows Embedded 7 Miniature size: 75 x 65 x 8 mm SB-iGT carrier board turns the CM-iGT module into SBC-iGT - a single board computer
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Overview
2.2
Block Diagram Figure 1
CM-iGT Block Diagram
5V DC
PMU
AMD Radeon HD 6xxx
DP / HDMI / LVDS
DP / HDMI
x86 CPU cores
Memory Ctrl.
64 bit
DDR3 2GB - 4GB
AMD G-Series T16R / T40E Display Ctrl. x2
VGA
PCIe x4
PCIe UMI
BootROM iSSD 8GB - 32GB
UMI
SPI
SPI
SATA-III USB2.0 x8 SATA x5
USB Hudson A55E Controller Hub
PCIe x2
GbE
GbE
GbE Ctrl. RTL8111
USB2 to CAN GPIO
GPIO x25
SMBus
SMBus x2
CAN
PCIe
GbE Ctrl. RTL8111
TPM LPC
Stereo out
UART
Stereo in
Audio S/PDIF out codec
HDA
LPC
SIO SMSC
GPIOs
S/PDIF in RS232
HDA
Revised February 2013
CM-iGT Reference Guide
RS232
8
Overview
2.3
CM-iGT Features The "Option" column specifies the configuration code required for a particular feature. "+" means that the feature is always available. Table 3
System and Graphics
Feature
Specifications
CPU RAM Storage Video Processing Unit
AMD G-Series Processor: G-T16R single-core 600MHz / G-T40E dual-core 1GHz / G-T56N dualcore 1.65GHz* 2GB - 4GB DDR3-1066, 64-bit On-board BIOS flash, 1MB, reprogrammable On-board SSD, up to 32GB, through SATA interface UVD 3 engine with native H.264, VC-1, MPEG2, and DivX 1080p Blu-Ray playback support
Option C D + ND +
* The G-T56N CPU option requires an extended cooling solution, which is not provided by CompuLab.
Table 4
I/O
Feature
Specifications Two configurable display interfaces support simultaneous operation with the following configurations: • Up to two DisplayPort interfaces, up to 1920x1200 at 60Hz • Up to two HDMI 1.4 interfaces, stereo-3D support, up to 1920x1200 at 60Hz • Up to one LVDS interface • Up to one VGA interface Up to 6 PCI Express Gen 2.0 ports Up to 9 USB2.0 high-speed host ports, 3 EHCI/OHCI USB2 high/fullspeed hubs USB2.0 full-speed port, OHCI full speed hub
Display
PCI Express USB SATA Serial Ports CAN bus Gigabit Ethernet Audio
LPC Bus I2C/SMBus TPM General Purpose I/O General Event Inputs
Table 5
+
+ +
Up to 5 SATA III ports, 6.0 Gbps, integrated controller and PHY
+
COM1 - RS-232, rx/tx & flow control, RS-232 levels, up to 460 Kbps UART2 - UART, rx/tx, or IrDA v1.2, 3.3V levels, up to 4 Mbps
S S
CAN bus interface (CAN V2.0B at 1 Mb/s), 3.3V levels
Y
Up to two 1000Base-T Ethernet ports. Implemented with Realtek RT8111F 802.3 compliant controllers Onboard audio codec with analog stereo output, stereo input and stereo microphone support S/PDIF input / output HDMI audio Azalia HD audio compliant interface Host, 33 MHz, Intel LPC v1.0 compatible Up to 2 I2C buses, up to 400Kbps Trusted Platform Manager ver 1.2 of TCG by Atmel AT97SC3204 Up to 21 GPIO’s implemented with the FCH chipset Up to 8 GPIO’s implemented with SuperIO Up to 3 software programmable general purpose input signals
E A A + + + + J + S +
Electrical, Mechanical and Environmental Specifications
Supply Voltage Active power consumption Standby/Sleep consumption Dimensions Weight MTBF Operation temperature (case) Storage temperature
Revised February 2013
Option
Single 5V DC TBD TBD 75 x 65 x 8 mm 37 gram > 100,000 hours Commercial: 0o to 70o C Extended: -20o to 70o C Industrial: -40o to 85o C o o -40 to 85 C
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Overview
Relative humidity Shock Vibration Connectors Connector insertion / removal
Revised February 2013
10% to 90% (operation) 05% to 95% (storage) 50G / 20 ms 20G / 0 - 600 Hz 2 x 140 pin, 0.6 mm 50 cycles
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Core system components
3
CORE SYSTEM COMPONENTS
3.1
AMD Embedded G-Series APU
3.1.1
CPU Core The AMD embedded G-Series APU x86 core supports the following key features:
· · · · · · · 3.1.2
Single or dual x86 Processor AMD64 64-bit ISA Advanced Branch Prediction Out-of-Order Instruction Execution 64-bit floating-point unit SSE1,2,3, SSSE3 ISA, SSE4A, MMX AMD Virtualization technology
GPU Core The AMD embedded G-Series APU integrated GPU core supports the following key features:
· · ·
·
3.2
Dedicated graphics memory controller · High efficiency ring bus memory controller · Direct connection to memory 2D Acceleration · Highly-optimized 128-bit engine, capable of processing multiple pixels per clock 3D Acceleration · Full DirectX 11 support, including full speed 32-bit floating point per component operations · Shader Model 5 · OpenCL 1.1 support · OpenGL 4.0 support Motion Video Acceleration · Dedicated hardware (UVD 3) for H.264, VC-1 and MPEG2 decode · HD HQV and SD HQV support: noise removal, detail enhancement, color enhancement, cadence detection, sharpness, and advanced de-interlacing · Super up-conversion for SD to HD resolutions
DRAM CM-iGT incorporates 2GB - 4GB of DDR3. The DRAM interface is 64-bits wide and runs with a 533MHz clock.
3.3
SPI Flash or Boot ROM CM-iGT features 16 Mbits of SPI flash used for BIOS.
Revised February 2013
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Core system components
3.4
iSSD CM-iGT features up to 32GB of on-board iSSD storage.
Revised February 2013
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Peripheral Interfaces
4
PERIPHERAL INTERFACES CM-iGT implements a number of peripheral interfaces through the interface connectors (P1 and P18). The following notes apply to those interfaces:
· · ·
Some interfaces/signals are available only with/without certain configuration options. Each signal’s availability is noted in the “Signal description” table of each interface. Certain interface pins can be configured as one of several signals. For pin multiplexing characteristics, please refer to “Signal description” in the table of each interface. All of the CM-iGT digital interfaces operate at 3.3V CMOS voltage levels, unless otherwise noted.
The signals for each interface are described in the “Signal description” tables. The following notes summarize the column headers for these tables:
· · · · ·
“Signal name” – The symbolic name of each signal. “Pin#” – The pin number on the interface connector. “Type” – Signal type. “Description” – Signal description. “Availability” – Certain signals are not available with/without certain configuration options. This column summarizes configuration requirements for each signal.
Each interface signal can be one of the following types. Signal type is noted in the “Signal description” tables for each signal
· · · · · · · · · ·
Revised February 2013
“O” – Digital output “I” – Digital input “IO” – Digital Input/Output “AO” – Analog Output “AI” – Analog Input “OD” – Open Drain Signal, not pulled up on the CM-iGT “ODP” – Open Drain Signal, pulled up on the CM-iGT “IPU” – Open Drain Input Signal, pulled up on the CM-iGT “IPD” – Open Drain Input Signal, pulled down on the CM-iGT “P” – Power signal
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Peripheral Interfaces
4.1
Display Interface The CM-iGT display sub-system is based on the display controller of the APU. The display sub-system incorporates two independent display controllers supporting dual-head operation and features three separate display interfaces:
· · ·
DP0 – configurable as DisplayPort, eDP, HDMI, single link DVI, single link LVDS DP1 – configurable as DisplayPort, eDP, HDMI, single link DVI Analog VGA, cloned with DP1.
When DP0 is configured for Display Port / eDP / single link DVI operating modes, maximal resolution is 1920x1200@60Hz. When DP0 is configured as single link LVDS maximal resolution is 1024x600@60Hz. In dual-head operation mode, maximal resolution for DP1 is 1920x1200@60Hz. Table 6
Display interface signals
Signal Name
Pin #
Type
Description
Availability
Display Port#0 DP0_TX0_P DP0_TX0_N DP0_TX1_P DP0_TX1_N DP0_TX2_P DP0_TX2_N DP0_TX3_P DP0_TX3_N DP0_AUX_P DP0_AUX_N
P1-60 P1-58 P1-53 P1-51 P1-54 P1-52 P1-65 P1-63 P1-47 P1-49
O O O O O O O O IO IO
DP0_HPD
P1-44
I
DP0 - Lane#0 DP0 - Lane#1 DP0 - Lane#2 DP0 - Lane#3 DP0 - Auxiliary lane, Used as DDC lines for HDMI/DVI/LVDS DP0 - Hot plug detection. 100K PD on Base is needed
LVDS Support Signals LVDS_AUX_EN# LVDS_VARY_BL LVDS_BLON
P1-46 P1-48 P1-56
O O O
DP1_TX0_P DP1_TX0_N DP1_TX1_P DP1_TX1_N DP1_TX2_P DP1_TX2_N DP1_TX3_P DP1_TX3_N DP1_AUX_P DP1_AUX_N
P1-29 P1-27 P1-35 P1-33 P1-42 P1-40 P1-30 P1-28 P1-23 P1-21
O O O O O O O O IO IO
DP1_HPD
P1-32
I
Control to Power LCD Logic Circuits LCD Backlight Intensity LCD Backlight Inverter ON
Display Port#1 DP1 - Lane#0
Always available
DP1 - Lane#1 DP1 - Lane#2 DP1 - Lane#3 DP1 - Auxiliary lane, Used as DDC lines for HDMI/DVI DP1 - Hot plug detection. 100K PD on Base is needed VGA
VGA_R VGA_G VGA_B VGA_VSYNC VGA_HSYNC VGA_SDA VGA_SCL
Revised February 2013
P1-93 P1-101 P1-105 P1-107 P1-109 P1-99 P1-95
AO AO AO O O IO O
Red video signal Green video signal Blue video signal Vertical synchronization Horizontal synchronization EDID Data Line EDID Clock Line
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Peripheral Interfaces
4.2
Gigabit Ethernet CM-iGT incorporates up to two full-featured Gigabit Ethernet interfaces.
4.2.1
Primary Gigabit Ethernet CM-iGT primary Gigabit Ethernet interface is implemented with the RTL8111F Gigabit Ethernet controller with integrated PHY. The interface supports the following main features:
· · · · · · ·
Fully compliant with IEEE 802.3 standard 1000 Mbps operation – full duplex 10 / 100 Mbps operation – half and full duplex Crossover Detection and Auto-Correction, Polarity Correction Auto-negotiation, adaptive equalization, cross-talk and echo cancellation Timing recovery and Error correction Activity and speed indicator LED controls
Table 7
Primary Gigabit Ethernet interface signals
Signal Name LAN0_MDIP0 LAN0_MDIN0 LAN0_MDIP1 LAN0_MDIN1 LAN0_MDIP2 LAN0_MDIN2 LAN0_MDIP3 LAN0_MDIN3 LAN0_EESK_L1 LAN0_EEDI_L2 LAN0_TXLED#
Pin # P1-2 P1-4 P1-1 P1-3 P1-10 P1-12 P1-9 P1-11 P1-6 P1-5 P1-13
Type IO IO IO IO IO IO IO IO O O O
Description First pair in 1000Base-T / transmit pair in 10Base-T and 100Base-T Second pair in 1000Base-T / receive pair in 10Base-T and 100Base-T Third pair in 1000Base-T Forth pair in 1000Base-T
Availability
Only available with either ‘E1’ or ‘E2’ configuration options
Activity LED output. Active low 10 / 100 / 1000 LED output 10 / 100 / 1000 + activity LED output
NOTE: For magnetics selection recommendations, please refer to section 8.3 of this document.
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Peripheral Interfaces
4.2.2
Secondary Gigabit Ethernet CM-iGT secondary Gigabit Ethernet interface is implemented with the RTL8111F Gigabit Ethernet controller with integrated PHY. The interface supports the following main features:
· · · · · · ·
Fully compliant with IEEE 802.3 standard 1000 Mbps operation – full duplex 10 / 100 Mbps operation – half and full duplex Crossover Detection and Auto-Correction, Polarity Correction Auto-negotiation, adaptive equalization, cross-talk and echo cancellation Timing recovery and Error correction Activity and speed indicator LED controls
Table 8
Secondary Gigabit Ethernet interface signals
Signal Name LAN1_MDIP0 LAN1_MDIN0 LAN1_MDIP1 LAN1_MDIN1 LAN1_MDIP2 LAN1_MDIN2 LAN1_MDIP3 LAN1_MDIN3 LAN1_EESK_L1 LAN1_EEDI_L2 LAN1_TXLED#
Pin # P18-2 P18-4 P18-1 P18-3 P18-10 P18-12 P18-9 P18-11 P18-6 P18-5 P18-13
Type IO IO IO IO IO IO IO IO O O O
Description First pair in 1000Base-T / transmit pair in 10Base-T and 100Base-T Second pair in 1000Base-T / receive pair in 10Base-T and 100Base-T Third pair in 1000Base-T Forth pair in 1000Base-T
Availability
Only available with either ‘E2’ configuration options
Activity LED output. Active low 10 / 100 / 1000 LED output 10 / 100 / 1000 + activity LED output
NOTE: For magnetics selection recommendations, please refer to section 8.3 of this document.
Revised February 2013
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Peripheral Interfaces
4.3
PCI Express CM-iGT features up to six PCI Express Gen2 ports. Two ports are implemented with the Fusion Controller Hub (FCH) and additional four ports with the APU. PCIe interface derived from the APU can be configured as 4 x PCIe-single lane or 2 x PCIe-x2 lane or 1 x PCIe-x4 lane. Table 9
PCI Express interface signals
Signal Name
Pin #
Type
Description
Availability
PCIE Interface APU PCIE_APU_RX0_N PCIE_APU_RX0_P PCIE_APU_TX0_N PCIE_APU_TX0_P PCIE_APU_RX1_N PCIE_APU_RX1_P PCIE_APU_TX1_N PCIE_APU_TX1_P PCIE_APU_RX2_N PCIE_APU_RX2_P PCIE_APU_TX2_N PCIE_APU_TX2_P PCIE_APU_RX3_N PCIE_APU_RX3_P PCIE_APU_TX3_N PCIE_APU_TX3_P
P1-34 P1-36 P1-78 P1-76 P1-39 P1-41 P1-84 P1-82 P1-83 P1-81 P1-90 P1-88 P1-89 P1-87 P1-96 P1-94
I I O O I I O O I I O O I I O O
PCIE_FCH_RX2_N PCIE_FCH_RX2_P PCIE_FCH_TX2_N PCIE_FCH_TX2_P PCIE_FCH_RX3_N PCIE_FCH_RX3_P PCIE_FCH_TX3_N PCIE_FCH_TX3_P
P18-106 P18-108 P18-112 P18-114 P18-105 P18-107 P18-111 P18-113
I I O O I I O O
receive data pair Lane#0 transmit data pair Lane#0 receive data pair Lane#1 transmit data pair Lane#1 Always available receive data pair Lane#2 transmit data pair Lane#2 receive data pair Lane#3 transmit data pair Lane#3 PCIE Interface FCH receive data pair transmit data pair Always available receive data pair transmit data pair
PCIE reference clock and misc. signals XA_PCIE_CLK_N XA_PCIE_CLK_P XA_PCIe_CLKREQ# XB_PCIE_CLK_N XB_PCIE_CLK_P XB_PCIe_CLKREQ# PCIE_WAKE_UP#
Revised February 2013
P18-81 P18-83 P18-17 P18-99 P18-101 P18-15 P18-109
O O IPU IO O IPU IPU
clock pair A clock request input clock pair B
Always available
clock request input PCIE wake-up input
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Peripheral Interfaces
4.4
SATA CM-iGT incorporates five SATA-III ports implemented with the FCH. The interface supports the following main features:
· · ·
Backward compatible with Second and First generation devices Complies with SATA 2.6 specification Supports two modes of operation: (a) IDE emulation mode ; (b) AHCI mode (compliant with AHCI specification revision 1.2)
· · ·
Device or Host Initiated Power Management (DIPM /HIPM) support Hot plug support Native Command Queuing (NCQ)
Table 10
SATA interface signals
Signal Name
Pin #
SB_SATA_RX0_N SB_SATA_RX0_P SB_SATA_TX0_N SB_SATA_TX0_P SB_SATA_RX1_N SB_SATA_RX1_P SB_SATA_TX1_N SB_SATA_TX1_P eSATA_RX0_N eSATA_RX0_P eSATA_TX0_N eSATA_TX0_P eSATA_RX1_N eSATA_RX1_P eSATA_TX1_N eSATA_TX1_P eSATA_RX2_N eSATA_RX2_P eSATA_TX2_N eSATA_TX2_P HDD_ACT#
P18-118 P18-120 P18-124 P18-126 P18-100 P18-102 P18-93 P18-95 P1-118 P1-120 P1-102 P1-100 P18-58 P18-60 P18-56 P18-54 P18-82 P18-84 P18-78 P18-76 P18-128
Revised February 2013
Type I I O O I I O O I I O O I I O O I I O O OD
Description
Availability
receive data pair#1 transmit data pair#1 receive data pair#2 transmit data pair#2 receive data pair#3 transmit data pair#3
Always available
receive data pair#4 transmit data pair#4 receive data pair#5 transmit data pair#5 HDD activity indicator
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Peripheral Interfaces
4.5
USB CM-iGT provides up to 9 USB 2.0 ports and one USB1.0 implemented with the FCH. USB 2.0 interface provides the following features:
· · ·
Complies with EHCI (high-speed host controller) Complies with OHCI (low-speed/full-speed host controller) Complies with the USB 2.0 standard for high-speed (480M bit/s) functions
Table 11
USB interface signals
Signal Name
Pin #
USB_FS1_N USB_FS1_P USB_HS0_N USB_HS0_P USB_HS1_N USB_HS1_P USB_HS3_N USB_HS3_P USB_HS4_N USB_HS4_P USB_HS5_N USB_HS5_P USB_HS7_N USB_HS7_P USB_HS8_N USB_HS8_P USB_HS12_N USB_HS12_P USB_HS13_N USB_HS13_P USBOC2# USBOC6# USBOC3#
4.6
Type
P1-77 P1-75 P1-59 P1-57 P18-41 P18-39 P18-75 P18-77 P1-130 P1-132 P18-138 P18-140 P1-129 P1-131 P1-135 P1-137 P1-136 P1-138 P18-130 P18-132 P1-128 P18-136 P1-133
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IPU IPU IPU
Description
Availability
HUB
USB Full speed pair#0
OHCI3
USB High Speed pair#0 USB High Speed pair#1 USB High Speed pair#3 USB High Speed pair#4 USB High Speed pair#5
Always available.
USB High Speed pair#7 USB High Speed pair#8 USB High Speed pair#12 USB High Speed pair#13
OHCI0 EHCI0 OHCI0 EHCI0 OHCI0 EHCI0 OHCI0 EHCI0 OHCI1 EHCI1 OHCI1 EHCI1 OHCI1 EHCI1 OHCI2 EHCI2 OHCI2 EHCI2
USB Over Current indicator #2 USB Over Current indicator #6 USB Over Current indicator #3
CAN Bus CM-iGT incorporates CAN bus interface implemented with the Microchip MCP2515 IC. The CAN bus implements the CAN specification, version 2.0B. It is capable of transmitting and receiving both standard and extended data and remote frames. It features two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host processor overhead. Table 12
CAN BUS
Signal Name CAN_RX CAN_TX
Revised February 2013
Pin #
Type
P18-69 P18-65
I O
Description CAN BUS Receive signal 3.3V level CAN BUS Transmit signal 3.3V level
CM-iGT Reference Guide
Availability Only available with the ‘Y’ configuration option
19
Peripheral Interfaces
4.7
Audio
4.7.1
Analog and Digital Audio The CM-iGT analog audio subsystem is implemented with the Realtek ALC886-GR audio codec. The audio sub-system supports the following features:
· · ·
Single ended stereo-line output Single ended stereo-line input Digital input and output (S/PDIF)
Table 13
Audio signals
Signal Name LIN1_L LIN1_R LOUT_L LOUT_R MIN1_L MIN1_R SPDIFI SPDIFO AUD_SENSA SPKR
4.7.2
Pin #
Type
P18-133 P18-131 P18-139 P18-137 P18-129 P1-24 P1-20 P1-18 P1-22 P18-22
AI AI AO AO AI AI I O I AO
Description Left stereo line input Right stereo line input Left stereo line output Right stereo line output Left stereo microphone input Right stereo microphone input Audio digital Input Audio digital Output Jack detection pin, see SB-iGT manual Computer speaker output
Availability
Only available with the ‘A’ configuration option
Always available
High Definition Audio Interface The CM-iGT High Definition Audio (HDA) interface is implemented with the FCH Azalia controller compliant with HD Audio 1.0 specification. Table 14
HDA signals
Signal Name
4.8
Pin #
Type
Description
Availability
AZ_BITCLK AZ_RST# AZ_SYNC AZ_SDOUT
P18-119 P18-121 P18-125 P18-123
O O O O
HDA clock HDA reset HDA sync HDA digital output
Always available
AZ_SDATA_IN0
P18-117
I
HDA digital input #0
Only available without the ‘A’ configuration option
AZ_SI2_GPIO169 AZ_SI3_GPIO170
P18-73 P18-85
IO IO
HDA digital input #2 HDA digital input #3
Always available
LPC - Low Pin Count Interface CM-iGT features an LPC Interface compliant with the LPC 1.1 specification. The LPC bus provides a functional replacement for interfacing legacy ISA functions. Table 15
LPC signals
Signal Name PCI_CLK3 LPC_CLK0 LAD0 LAD1 LAD2 LAD3 SERIRQ_GPIO48 LFRAME# FCH_PCIE_RST#
Revised February 2013
Pin #
Type
P18-72 P18-88 P18-90 P18-92 P18-94 P18-96 P18-89 P18-87 P18-104
O O IO IO IO IO OD O ODP
Description
Availability
LPC clock#1 (33 Mhz) LPC clock#2 (33 Mhz) LPC Multiplexed command, address, data
Always available
Serial Interrupt Request LPC Frame LPC Device reset (active low)
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Peripheral Interfaces
4.9
Serial Ports
4.9.1
UART CM-iGT provides one general purpose UART interface implemented with the SMSC SIO1007 SuperIO. The UART interface supports the following features:
· ·
High Speed 16C550A compatible with Send/Receive 16 byte FIFO Supports 50 to 460.8K baud rates with programmable baud rate generator
Table 16
UART Signals
Signal Name SIO_IR_RXD SIO_IR_TXD
4.9.2
Pin # P1-112 P1-114
Type I O
Description Serial Data In Serial Data Out
Availability Only available with the ‘S’ configuration option
RS232 CM-iGT incorporates one RS232 port implemented with the SMSC SIO1007 SuperIO. The following features are supported:
· · ·
High Speed 16C550A compatible with Send/Receive 16 byte FIFO Programmable baud rate of up to 250 Kbps Full modem control circuitry
Table 17
UART/RS232 Signals
Signal Name COM1_CTS COM1_DCD COM1_DSR COM1_DTR COM1_RI COM1_RTS COM1_RX COM1_TX
Revised February 2013
Pin # P1-123 P1-113 P1-111 P1-125 P1-124 P1-121 P1-117 P1-119
Type I I I O I O I O
Description Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicate Request To Send Serial Data In Serial Data Out
CM-iGT Reference Guide
Availability
Only available with the ‘S’ configuration option
21
Peripheral Interfaces
4.10
GPIO and GEVENT CM-iGT provides 26 general purpose I/O pins (GPIO) and 3 general event inputs (GEVET). Table 18
GPIO signals
Signal Name
Pin #
Type
Description
Availability
GPIO by Super IO SIO_GPIO16 SIO_GPIO17 SIO_GPIO30 SIO_GPIO31 SIO_GPIO32 SIO_GPIO33 SIO_GPIO34 SIO_GPIO35
P1-64 P1-66 P1-68 P1-70 P1-72 P1-69 P1-71 P1-73
IO IO IO IO IO IO IO IO
GPIO202_FCS# GPIO205_FCK FCH_GPIO13 FCH_GPIO11 FN2PWM_GPIO54 FNTH1_GPIO57 FNTH2_GPIO58 TIN2_GPIO173 TMR0_GPIO197 TMR1_GPIO198 FNTH_GPIO56
P18-42 P18-44 P18-57 P1-17 P18-16 P18-80 P18-29 P1-85 P18-28 P18-30 P1-104
IO IO IO IO IO IO IO IO IO IO IO
FCH_GPIOD145 FCH_GPIOD146 FCH_GPIOD147 FCH_GPIOD147 FCH_GPIOD149
P1-45 P1-92 P1-108 P1-116 P1-97
IO IO IO IO IO
FCH_GPIO201_S5 FCH_GPIO204_S5
P18-18 P18-46
Each SIO_GPIOxx corresponds to the GPIOxx of SIO1007 SuperIO chip
Available with S option
Regular GPIO by FCH
Each GPIOxx corresponds to the GPIOxx of FCH. Active in S0 power state
Always available
Open Drain GPIO by FCH Each GPIOxx corresponds to the Open Drain GPIOxx of FCH. Active in S0 power state
Always available
Regular GPIO by FCH available in Stand-by / Hibernate modes
Table 19
GPIO201/204 by FCH Active in S0 and S5 power states.
Always available
GEVENT signals
Signal Name IRRX0_GEVENT16# IRRX1_GEVENT20# IRTX0_GEVENT17#
Revised February 2013
IO IO
Pin # P18-59 P18-37 P18-61
Type I I I
CM-iGT Reference Guide
Description
Availability Always available
22
Peripheral Interfaces
4.11
SMBUS CM-iGT features up to two SMBUS interfaces with Alert Input. One of the interfaces is available in Sleep/Hibernate modes. This interface is compatible with I2C devices. SMBus supports operating frequencies of 10-100 kHz. Table 20
SMBUS signals
Signal Name SCLK0 SDATA0 SCLK2 SDATA2 SMBALERT#
Revised February 2013
Pin # P18-21 P18-23 P18-27 P18-25 P18-24
Type ODP ODP ODP ODP IPU
Description SMBUS#0 CLK and Data, active in S0 power state SMBUS#1 CLK and Data, active in S3/S5 power state SMBUS Alert
CM-iGT Reference Guide
Availability
Always Available
23
System Logic
5
SYSTEM LOGIC
5.1
Power Management
5.1.1
Power Rails CM-iGT is powered with 5V_S0 and 5V_S5 power rails:
·
5V_S0 - Main power supply. Typical voltage – 5V. Current consumption requirements: 3A for C600 and C1000D configuration options and 5A for C1650D configuration option.
·
5V_S5 - Sleep/Hibernate power supply. Typical voltage – 5V. Always present. Current consumption requirements: 2A for C600 and C1000D configuration options and 3A for C1650D configuration option.
·
A_VBAT - RTC back-up battery power input. A_VBAT should always be present for proper RTC operation. It is recommended to connect this rail to a 3V coin-cell lithium battery.
· 5.1.2
GND - Common ground.
System Signals and Power Sequence CM-iGT features an automatic power-on function that turns on the device immediately after the power is applied and internal circuits are stabilized. The power-up sequence should be as follows:
· ·
Apply 5V_S5 FCH initiates SLP_S3B5V low to enable 5V_S0 rail.
The power down/standby sequence:
· · ·
Apply PWRBTN#_HW (short pulse for standby / more than 4sec for power down) FCH initiates SLP_S3B5V high that disables the 5V_S0 rail Shut down 5V_S5 (or leave it connected and use PWRBTN# signal for next power up).
Table 21
System signals
Signal Name SLP_S3B5V SYS_RST# SB_PG FCH_PCIE_RST# INTRUDER_ALERT# PROCHOT# PWRBTN#_HW
Pin #
Type
Description
P1-15 P18-33 P1-16 P18-20 P18-63 P1-106 P18-35
OD IPU IPU ODP IPU ODP IPD
Go to (high)/Exit Off (low) standby/hibernate signal System reset Carrier board Power Good Devices reset Intruder detection APU is overheated and going to shut-down Power Button signal
Availability
Always available
SYS_RST# signal is the main system reset (should be asserted for at least 50msec) that invokes a global reset that affects every functional module on CM-iGT. FCH_PCIE_RST# signal should be used to reset peripheral devices on CM-iGT and on the carrier board.
Revised February 2013
CM-iGT Reference Guide
24
System Logic
5.2
Unconnected Pins The pins listed below are reserved for future use and must be left unconnected. Table 22
Reserved Signals
Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
5.3
Pin #
Type
P18-40 P18-68 P18-36 P18-34 P18-70 P18-64 P18-66 P18-32 P18-49 P18-47 P18-53 P18-48 P18-50 P18-45
Description
Leave unconnected
Availability
Unavailable
System Boot Options Following devices can serve as a bootable device for operating system:
· · ·
Onboard iSSD External hard drive connected to the SATA interface USB storage device
The boot order is determined by BIOS setup menu.
5.4
TPM CM-iGT features an optional TMP module implemented with Atmel AT97SC3204.
Revised February 2013
CM-iGT Reference Guide
25
Baseboard Interface
6
BASEBOARD INTERFACE CM-iGT connects to the carrier board through P1 and P18 - 0.6 mm pitch 140-pin connectors.
6.1
Connector Pin-out Table 23 Pin # P1-1 P1-3 P1-5 P1-7 P1-9 P1-11 P1-13 P1-15 P1-17 P1-19 P1-21 P1-23 P1-25 P1-27 P1-29 P1-31 P1-33 P1-35 P1-37 P1-39 P1-41 P1-43 P1-45 P1-47 P1-49 P1-51 P1-53 P1-55 P1-57 P1-59 P1-61 P1-63 P1-65 P1-67 P1-69 P1-71 P1-73 P1-75 P1-77 P1-79 P1-81 P1-83 P1-85 P1-87 P1-89 P1-91 P1-93 P1-95 P1-97 P1-99 P1-101 P1-103 P1-105
Revised February 2013
Connector P1 CM-iGT Signal Name LAN0_MDIP1 LAN0_MDIN1 LAN0_EEDI_L2 5V_S0 LAN0_MDIP3 LAN0_MDIN3 LAN0_TXLED# SLP_S3B5V FCH_GPIO11 5V_S0 DP1_AUX_N DP1_AUX_P NC DP1_TX0_N DP1_TX0_P 5V_S0 DP1_TX1_N DP1_TX1_P A_VBAT PCIE_APU_RX1_N PCIE_APU_RX1_P 5V_S0 FCH_GPIOD145 DP0_AUX_P DP0_AUX_N DP0_TX1_N DP0_TX1_P 5V_S0 USB_HS0_P USB_HS0_N LVDS_DIGON DP0_TX3_N DP0_TX3_P 5V_S0 SIO_GPIO33 SIO_GPIO34 SIO_GPIO35 USB_FS1_P USB_FS1_N 5V_S0 PCIE_APU_RX2_P PCIE_APU_RX2_N TIN2_GPIO173 PCIE_APU_RX3_P PCIE_APU_RX3_N 5V_S0 VGA_R VGA_SCL FCH_GPIOD149 VGA_SDA VGA_G 5V_S0 VGA_B
Reference Section 4.2.1 4.2.1 4.2.1 5.1.1 4.2.1 4.2.1 4.2.1 5.1.2 4.10 5.1.1 4.1 4.1 4.1 4.1 5.1.1 4.1 4.1 5.1.1 4.3 4.3 5.1.1 4.10 4.1 4.1 4.1 4.1 5.1.1 4.5 4.5 4.1 4.1 4.1 5.1.1 4.10 4.10 4.10 4.5 4.5 5.1.1 4.3 4.3 4.10 4.3 4.3 5.1.1 4.1 4.1 4.10 4.1 4.1 5.1.1 4.1
Pin # P1-2 P1-4 P1-6 P1-8 P1-10 P1-12 P1-14 P1-16 P1-18 P1-20 P1-22 P1-24 P1-26 P1-28 P1-30 P1-32 P1-34 P1-36 P1-38 P1-40 P1-42 P1-44 P1-46 P1-48 P1-50 P1-52 P1-54 P1-56 P1-58 P1-60 P1-62 P1-64 P1-66 P1-68 P1-70 P1-72 P1-74 P1-76 P1-78 P1-80 P1-82 P1-84 P1-86 P1-88 P1-90 P1-92 P1-94 P1-96 P1-98 P1-100 P1-102 P1-104 P1-106
CM-iGT Reference Guide
CM-iGT Signal Name LAN0_MDIP0 LAN0_MDIN0 LAN0_EESK_L1 GND LAN0_MDIP2 LAN0_MDIN2 GND SB_PG SPDIFO SPDIFI AUD_SENSA MIN1_R GND DP1_TX3_N DP1_TX3_P DP1_HPD PCIE_APU_RX0_N PCIE_APU_RX0_P GND DP1_TX2_N DP1_TX2_P DP0_HPD LVDS_AUX_EN# LVDS_VARY_BL GND DP0_TX2_N DP0_TX2_P LVDS_BLON DP0_TX0_N DP0_TX0_P GND SIO_GPIO16 SIO_GPIO17 SIO_GPIO30 SIO_GPIO31 SIO_GPIO32 GND PCIE_APU_TX0_P PCIE_APU_TX0_N 5V_S5 PCIE_APU_TX1_P PCIE_APU_TX1_N GND PCIE_APU_TX2_P PCIE_APU_TX2_N FCH_GPIOD146 PCIE_APU_TX3_P PCIE_APU_TX3_N GND eSATA_TX0_P eSATA_TX0_N FNTH_GPIO56 PROCHOT#
Reference Section 4.2.1 4.2.1 4.2.1 5.1.1 4.2.1 4.2.1 5.1.1 5.1.2 4.7.1 4.7.1 4.7.1 4.7.1 5.1.1 4.1 4.1 4.1 4.3 4.3 5.1.1 4.1 4.1 4.1 4.1 4.1 5.1.1 4.1 4.1 4.1 4.1 4.1 5.1.1 4.10 4.10 4.10 4.10 4.10 5.1.1 4.3 4.3 5.1.1 4.3 4.3 5.1.1 4.3 4.3 4.10 4.3 4.3 5.1.1 4.4 4.4 4.10 5.1.2
26
Baseboard Interface P1-107 P1-109 P1-111 P1-113 P1-115 P1-117 P1-119 P1-121 P1-123 P1-125 P1-127 P1-129 P1-131 P1-133 P1-135 P1-137 P1-139
Table 24 Pin # P18-1 P18-3 P18-5 P18-7 P18-9 P18-11 P18-13 P18-15 P18-17 P18-19 P18-21 P18-23 P18-25 P18-27 P18-29 P18-31 P18-33 P18-35 P18-37 P18-39 P18-41 P18-43 P18-45 P18-47 P18-49 P18-51 P18-53 P18-55 P18-57 P18-59 P18-61 P18-63 P18-65 P18-67 P18-69 P18-71 P18-73 P18-75 P18-77 P18-79 P18-81 P18-83 P18-85 P18-87 P18-89 P18-91 P18-93
Revised February 2013
VGA_VSYNC VGA_HSYNC COM1_DSR COM1_DCD 5V_S0 COM1_RX COM1_TX COM1_RTS COM1_CTS COM1_DTR 5V_S0 USB_HS7_N USB_HS7_P USBOC3# USB_HS8_N USB_HS8_P 5V_S0
4.1 4.1 4.9 4.9 5.1.1 4.9 4.9 4.9 4.9 4.9 5.1.1 4.5 4.5 4.5 4.5 4.5 5.1.1
P1-108 P1-110 P1-112 P1-114 P1-116 P1-118 P1-120 P1-122 P1-124 P1-126 P1-128 P1-130 P1-132 P1-134 P1-136 P1-138 P1-140
FCH_GPIOD147 GND SIO_IR_RXD SIO_IR_TXD FCH_GPIOD147 eSATA_RX0_N eSATA_RX0_P GND COM1_RI AZ_SI1_FCH_PG USBOC2# USB_HS4_N USB_HS4_P GND USB_HS12_N USB_HS12_P 5V_S5
4.10 5.1.1 4.9 4.9 4.10 4.4 4.4 5.1.1 4.9 4.10 4.5 4.5 4.5 5.1.1 4.5 4.5 5.1.1
Connector P18 CM-iGT Signal Name
Reference Section
Pin #
CM-iGT Signal Name
LAN1_MDIP1 LAN1_MDIN1 LAN1_EEDI_L2 GND LAN1_MDIP3 LAN1_MDIN3 LAN1_TXLED# XB_PCIe_CLKREQ# XA_PCIe_CLKREQ# 5V_S0 SCLK0 SDATA0 SDATA2 SCLK2 FNTH2_GPIO58 5V_S0 SYS_RST# PWRBTN#_HW IRRX1_GEVENT20# USB_HS1_P USB_HS1_N 5V_S0 Reserved Reserved Reserved Reserved Reserved 5V_S0 FCH_GPIO13 IRRX0_GEVENT16# IRTX0_GEVENT17# INTRUDER_ALERT# CAN_TX 5V_S0 CAN_RX 5V_S5 AZ_SI2_GPIO169 USB_HS3_N USB_HS3_P 5V_S0 XA_PCIE_CLK_N XA_PCIE_CLK_P AZ_SI3_GPIO170 LFRAME# SERIRQ_GPIO48 5V_S0 SB_SATA_TX1_N
4.2.2 4.2.2 4.2.2 5.1.1 4.2.2 4.2.2 4.2.2 4.3 4.3 5.1.1 4.11 4.11 4.11 4.11 4.10 5.1.1 5.1.2 5.1.2 4.10 4.5 4.5 5.1.1 5.2 5.2 5.2 5.2 5.2 5.1.1 4.10 4.10 4.10 5.1.2 4.6 5.1.1 4.6 5.1.1 4.10, 4.7.2 4.5 4.5 5.1.1 4.3 4.3 4.10, 4.7.2 4.8 4.8 5.1.1 4.4
P18-2 P18-4 P18-6 P18-8 P18-10 P18-12 P18-14 P18-16 P18-18 P18-20 P18-22 P18-24 P18-26 P18-28 P18-30 P18-32 P18-34 P18-36 P18-38 P18-40 P18-42 P18-44 P18-46 P18-48 P18-50 P18-52 P18-54 P18-56 P18-58 P18-60 P18-62 P18-64 P18-66 P18-68 P18-70 P18-72 P18-74 P18-76 P18-78 P18-80 P18-82 P18-84 P18-86 P18-88 P18-90 P18-92 P18-94
LAN1_MDIP0 LAN1_MDIN0 LAN1_EESK_L1 GND LAN1_MDIN2 LAN1_MDIN2 GND FN2PWM_GPIO54 FCH_GPIO201_S5 FCH_PCIE_RST# SPKR SMBALERT# GND TMR0_GPIO197 TMR1_GPIO198 Reserved Reserved Reserved GND Reserved GPIO202_FCS# GPIO205_FCK FCH_GPIO204_S5 Reserved Reserved GND eSATA_TX1_P eSATA_TX1_N eSATA_RX1_N eSATA_RX1_P GND Reserved Reserved Reserved Reserved PCI_CLK3 GND eSATA_TX2_P eSATA_TX2_N FNTH1_GPIO57 eSATA_RX2_N eSATA_RX2_P GND LPC_CLK0 LAD0 LAD1 LAD2
CM-iGT Reference Guide
Reference Section 4.2.2 4.2.2 4.2.2 5.1.1 4.2.2 4.2.2 5.1.1 4.10 4.10 5.1.2 4.7.1 4.11 5.1.1 4.10 4.10 5.2 5.2 5.2 5.1.1 5.2 4.10 4.10 4.10 5.2 5.2 5.1.1 4.4 4.4 4.4 4.4 5.1.1 5.2 5.2 5.2 5.2 4.8 5.1.1 4.4 4.4 4.10 4.4 4.4 5.1.1 4.8 4.8 4.8 4.8
27
Baseboard Interface P18-95 P18-97 P18-99 P18-101 P18-103 P18-105 P18-107 P18-109 P18-111 P18-113 P18-115 P18-117 P18-119 P18-121 P18-123 P18-125 P18-127 P18-129 P18-131 P18-133 P18-135 P18-137 P18-139
6.2
SB_SATA_TX1_P 5V_S5 XB_PCIE_CLK_N XB_PCIE_CLK_P 5V_S0 PCIE_FCH_RX3_N PCIE_FCH_RX3_P PCIE_WAKE_UP# PCIE_FCH_TX3_N PCIE_FCH_TX3_P 5V_S0 AZ_SDATA_IN0 AZ_BITCLK AZ_RST# AZ_SDOUT AZ_SYNC 5V_S0 MIN1_L LIN1_R LIN1_L 5V_S0 LOUT_R LOUT_L
4.4 5.1.1 4.3 4.3 5.1.1 4.3 4.3 4.3 4.3 4.3 5.1.1 4.7.2 4.7.2 4.7.2 4.7.2 4.7.2 5.1.1 4.7.1 4.7.1 4.7.1 5.1.1 4.7.1 4.7.1
P18-96 P18-98 P18-100 P18-102 P18-104 P18-106 P18-108 P18-110 P18-112 P18-114 P18-116 P18-118 P18-120 P18-122 P18-124 P18-126 P18-128 P18-130 P18-132 P18-134 P18-136 P18-138 P18-140
LAD3 GND SB_SATA_RX1_N SB_SATA_RX1_P FCH_PCIE_RST# PCIE_FCH_RX2_N PCIE_FCH_RX2_P GND PCIE_FCH_TX2_N PCIE_FCH_TX2_P 5V_S5 SB_SATA_RX0_N SB_SATA_RX0_P GND SB_SATA_TX0_N SB_SATA_TX0_P HDD_ACT# USB_HS13_N USB_HS13_P GND USBOC6# USB_HS5_N USB_HS5_P
4.8 5.1.1 4.4 4.4 5.1.2 4.3 4.3 5.1.1 4.3 4.3 5.1.1 4.4 4.4 5.1.1 4.4 4.4 4.4 4.5 4.5 5.1.1 4.5 4.5 4.5
Connector Type Table 25
Connector type
Part Reference
Mfg.
CM-iGT connector P/N
Baseboard (mating) connector P/N
P1, P18
AMP
1-5353183-0
1-5353190-0 or CON140
Mating connectors and standoffs are available from CompuLab. For further details, please refer to http://compulab.co.il/support/cables-connectors-accessories/. CompuLab P/N for the AMP 1-5353190-0 connector is "CON140".
Revised February 2013
CM-iGT Reference Guide
28
Baseboard Interface
6.3
Mechanical Drawings Figure 2
Revised February 2013
CM-iGT Top (dimensions are in mm)
CM-iGT Reference Guide
29
Baseboard Interface
Figure 3
CM-iGT bottom (in mm; X-Ray view - as seen from top side)
1.
All dimensions are in millimeters.
2.
Height of all components is
