CMOS Variable-Gain Wide-Bandwidth CMFB-Free Differential Current Feedback Amplifier for Ultrasound Diagnostic Applications Hio Leong Chao and Dongsheng Ma Electrical and Computer Engineering Department The University of Arizona Tucson, AZ 85721-0104, USA
[email protected] Abstract—A CMOS current feedback amplifier (CFA) for ultrasound diagnostic applications is described in this paper. Unlike traditional CFA designs, this design proposes a new symmetrical circuit architecture which does not require extra common-mode feedback circuitry. The design employs active feedback to enhance the gain-bandwidth independence. Miller compensation is adopted for better frequency response and smaller on-chip capacitor. The CFA has been designed with TSMC 0.35 µm CMOS process. The active layout area is 0.052 mm2. HSPICE post-layout simulation shows that the CFA exhibits a bandwidth of 10.7 MHz for a variable voltage gain range of 6 dB to 60 dB, with a supply of 3.3 V and a power dissipation of 2.4 mW. Compared to CFA design without active feedback, the bandwidth variation is reduced by 8 times.
Fig. 1 Block diagram of ultrasound processor
To date, CFA design is still facing certain design problems. First, the offset voltage on the current feedback can not achieve systematically zero. CFA usually adopts an analog buffer as the input stage. As a result, the noninverting input has very high impedance, while the inverting input has very low impedance. Hence, the CFA’s offset is higher than in VFA designs [2], provided that all other design conditions are the same. Second, the constant bandwidth feature of the CFA is only approximate [3, 4], if the inverting input impedance rx is not small enough, which is common in CFA designs. Third, most of CFAs are still compensated by placing a capacitor at the high impedance node, which is usually before the output buffer stage [2, 4, 5, 6]. However, this technique leads to large capacitor value and thus large silicon area. The feasibility of applying advanced frequency compensation techniques in VFAs to CFA designs should be investigated. Last, in the perspective of process and cost, most of conventional CFA designs are still implemented with bipolar fabrication technology, which is capable of providing higher transconductance gain and faster speed than its CMOS counterparts. However, bipolar or BiCMOS designs are generally more expensive and consume more power [2, 5, 6].
I. INTRODUCTION In recent years, ultrasound diagnostic equipment has been utilized for medical analysis at an ever increasing rate. Compared to other established diagnostic technologies such as X-Ray, CAT Scan and MRI, it is safer and less expensive. In addition, it is the technology of choice in the areas such as obstetrics and cardiology. Fig. 1 shows a block diagram of an ultrasound processor, the core signal-processing function module in ultrasound diagnostic system. The ultra-sound signal is first amplified by a low-noise variable gain amplifier which converts the single-ended input signal to a differential signal. A differential signal has the advantage of reducing 2nd-order harmonic distortion and converting substrate and power-supply effects to common-mode noise. At the output stage, a variable gain post amplifier is used to amplify the differential signal from a voltage controller attenuator (VCA). Clearly, the variable gain amplifiers play a very critical role in the overall ultrasound system. To successfully achieve variable gain amplifier, the stability issue must be taken into consideration. Traditional voltage amplifiers usually have a constant gain-bandwidth product [1]. If the gain changes, the bandwidth shifts accordingly. This affects the speed and accuracy of the signal processing. In the worst case, the system becomes unstable. Current feedback amplifier (CFA) does not have this limitation and thus becomes very attractive in these types of applications, which motivates the authors to investigate highperformance CFA designs for ultrasound applications.
In this paper we propose a new CMOS CFA architecture with the following highlighted features. First, this proposed CFA is fully symmetrical and differential, which allows ideally zero systematic offset. Second, the design uses a resistive feedback path to set the DC output voltage, and thus eliminates external common-mode feedback (CMFB) circuits, making the circuit more power efficient. Third, we employ active feedback to reduce the inverting input
This work is sponsored in part by U.S. National Science Foundation under Grant No. EEC-0333046.
0-7803-9390-2/06/$20.00 ©2006 IEEE
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ISCAS 2006
the output impedance of the input buffer. The transimpedance of the CFA is determined by Cz and Rz. Thus, the transfer function can be expressed as
resistance, and gain-bandwidth independence is thus significantly enhanced. Last, we utilize Miller compensation technique to reduce the size of compensation capacitors in CFA design. The rest of this paper is organized as follows. In Section II, we describe the new CFA’s architecture and operation, and introduce gain-bandwidth independence enhancement technique. System loop gain and compensation technique will also be discussed. Circuit implementation issues are addressed in Section III. In Section V, simulation results are presented to verify the functionality and improvement of the proposed CFA. Finally, we conclude this research in Section V. II.
Vo = Vin '
. (2)
1 1+
R2 rx 2 R2 + 1 + Rz R z R1
2 R + sC z R2 + rx 1 + 2 R1
THE PROPOSED CFA
In this section, a new CFA circuit architecture is first proposed. The gain-bandwidth independence enhancement technique and loop gain transfer function are then analyzed to address the issues of system frequency response, stability and compensation. A.
1 2 R2 1 + 2 R1
Fig. 3 Half-circuit small signal model of CFA
Assuming Rz » R2 and rx = 0, then the cutoff frequency is only dependent on R2. Thus, the gain can be controlled by varying R1 without affecting the bandwidth. Clearly if rx ≠ 0 and rx·(1+2R2/R1) is comparable to R2, the cutoff frequency of the CFA becomes dependent on R1, R2 and rx. Varying gain leads to the variation of the bandwidth. To reduce this effect, the equivalent rx has to be very small. This could be achieved by the proposed feedback amplifier A1. With A1, the transfer function of the CFA is derived as
Architecture of Symmetrical CMFB-Free CFA
Vo 1 2 R 2 1 = 1 + Vin 2 R1 a ⋅ s 2 + b ⋅ s + c
Fig. 2 Block diagram of the proposed CFA
where
The architecture of the proposed CFA is shown in Fig. 2. It consists of two single-ended-output CFAs and a resistive feedback network. Thus the DC currents flowing through resistors R1, R2, R2’ (R2’ is equal to R2) are equal to zero. Hence, the DC outputs Vo+ and Vo– will have the same voltage potentials of Vin+ and Vin–, respectively. No extra common-mode feedback circuitry is thus necessary in this amplifier. The DC gain of the amplifier can be derived as, Vo _ diff Vin _ diff
2R = 2 + 1 , R 1
(1)
2 R2 R2 + rx 1 + R1 ,
a=
Cz A⋅ω
b=
1 R 2 rx 2 R2 1 + + 1 + A ⋅ ω R z R z R1
c =1+
(3)
r 2R + C z R 2 + x 1 + 2 A R1
,
and
R2 r 2R . + x 1 + 2 Rz R z ⋅ A R1
Assume that ω·A » (CzRz)-1, which is usually true for most cases. The transfer function (3) can be then simplified as
where the DC gain of the amplifier is well controlled by adjusting the ratio of feedback resistors R1 and R2. Also, because the CFAs are identical, symmetrical design is achieved, leading to zero systematic offset.
Vo 1 2 R2 = 1 + Vin 2 R1
B. Gain-bandwidth Independence Enhancement The equivalent half-circuit model of the CMFB-free CFA is shown in Fig. 3. An operational amplifier (op-amp) A1 is employed to create a feedback loop and to drive the noninverting input of the CFA. The transfer function of this opamp is represented as Av=A/(1+s/ω), where A is the DC gain and ω is the cutoff frequency.
1 1+
. (4)
R2 r 2R r 2R + x 1 + 2 + sCz R2 + x 1 + 2 Rz Rz ⋅ A R1 A R1
It is clear that the active feedback reduces the effective rx value to rx/A. Thus, the gain-bandwidth independence of the CFA is greatly improved. C. Loop Gain Analysis and Stability The small signal model for loop gain analysis is shown in Fig. 4. The loop gain transfer function can be derived by setting the input to zero and injecting a voltage source as shown in the figure. The derived loop gain transfer function is represented as
To address the effect of the active feedback circuit, we first analyze the CFA without this feedback amplifier. In this case, the CFA’s input is directly connected to Vin’/2. rx is
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T =−
R Vy 1 = t Vx Vin =0 R2 ' (1 + s / ω1 )⋅ (1 + s / ω 2 )
large silicon area. In this section, we will investigate the feasibility of applying Miller compensation technique, which has been widely used in VFA designs, to CFA designs.
(5)
where R2’ = R2·(1+2·rx/R1)+rx, and ω1 = (CtRt)-1 ; Ct and Rt are the internal parameters that determine the dominant pole location.
Fig. 5 Half-circuit small-signal model on the effect of the transimpedance Z(s)
Fig. 4 Small-signal model for CFA loop gain analysis
The half-circuit model for CFA’s transimpedance Z(s) is shown in Fig. 5. Here, rds is the small signal output resistance of the NMOS and PMOS transistors, C1 and C2 are the parasitic capacitance at node V1 and Vo, respectively. Note that a Miller capacitor CC has been placed in the circuit for compensation. The corresponding transimpedance Z(s) can be derived as
The transfer function of transimpedance Z(s) consists of a dominant pole ω1, and a high frequency pole ω2. We assume that ω2 » ω1, which is generally true, since the high frequency pole is normally far away from the dominant pole. Then the frequency ω|LG|=1 can be expressed as
ω LG =1 ≅ ω 2
2 − 1 + 1 + ω 2 ⋅ C t ⋅ R2 ' 2
2
.
(6)
Z (s ) =
The frequency ω|LG|=1 determines the cutoff frequency of CFA, and depends on Ct, R2’ and ω2. From (6), the phase margin can be expressed as Φ M = 180 − tan −1 (
ω |LG |=1 ω ) − tan −1 ( |LG |=1 ) . ω1 ω2
Vo g m ⋅ rds = ix 2
2
. 1 1 1 + s / ω1 ' 1 + s / ω 2 '
(8)
where ω1’ ≈ (gm·rds2·Cc)-1 and ω2’ ≈ gm· Cc/( C1· C2+ C2· Cc+ C1· Cc) ≈ gm/C2. When the CFA has no Miller compensation, the two poles in Fig. 4 are located at ω1 ≈ (2·C1·rds)-1 and ω2 ≈ 2· (C2·rds)-1. It clearly shows that the Miller compensation technique successfully splits the two poles by lowering the dominant pole and pushing second pole to higher frequency. The CFA can thus be stabilized with a smaller on-chip capacitor CC.
(7)
Hence, we could set the desired cutoff frequency of the CFA by choosing the values of Ct, R1’ and ω2 accordingly while meeting the phase margin specification. Equations (5) and (6) show that CFA has no trade-off between gain and bandwidth which usually occurs in a voltage amplifier. Thus, the only trade-off for CFA is bandwidth and stability. Theoretically, it proves that CFA can achieve desirable constant wide-bandwidth and variable gain at the same time.
III. CIRCUIT IMPLEMENTATIONS OF AMPLIFIER The schematic of the proposed CFA circuit is shown in Fig. 6. The two single-ended output CFAs are implemented by the transistors M1-M14. They are basically two two-stage amplifiers. The active feedback operational amplifiers consist of X1_M1-X1_M5 and X2_M1-X2_M5. The output of each op-amp is connected to the non-inverting input of a CFA to reduce the equivalent input resistance. Miller capacitors Cc are used to compensate the overall CMFB-free CFA and stabilize the system.
D. Miller Compensation in CFA In most of existing CFA designs, the amplifier is compensated by placing a capacitor at the high impedance node. However, this leads to large capacitor value and thus
Fig. 6 Schematic of the proposed CFA
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IV.
since the phase versus frequency plot of CFA’s output/input transfer function does not determine the system stability, we need to plot closed-loop frequency response to verify the stability issue, which is shown in Fig. 9. In this figure, a phase margin of 68.9° is obtained for the worst case when R1 = 60 Ω, while a gain margin of 27.5 dB is obtained. The system is thus well stabilized.
SIMULATION RESULTS 325µm
LG (dB)
160µm
Fig. 7 Layout of the proposed CFA
Gain (dB)
Phase (deg)
The circuit in Fig. 6 has been designed with TSMC 0.35µm N-well CMOS process. The layout, as shown in Fig. 7, has been submitted to MOSIS for fabrication. The active chip area is 0.052 mm2. The circuit was powered with a supply voltage of 3.3 V and consumed a total power of 2.4 mW. The Miller capacitor Cc is set to be 0.5 pF and R2 is set to be 30 kΩ.
Fig. 9 Loop gain of the CFA (top); phase plot of the loop gain (bottom).
Gain (dB)
V. CONCLUSION A new architecture of high performance fully differential CFA is introduced. It is based on a simple configuration that involves two CFAs in the feedback loops to achieve CMFBfree operation. A simple single stage operational amplifier is employed at each non-inverting input of the CFAs to reduce the equivalent resistance rx. This technique effectively improves the gain accuracy and gain bandwidth independence. Miller compensation technique is also used in this CFA for a more area-efficient design. Simulation result shows that the CFA’s gain and frequency response agree with the theoretical analysis. ACKNOWLEDGMENT The authors wish to thank Paul Prazak and Mike Koen from Texas Instruments for valuable discussion and support on the original work.
Fig. 8 Frequency response of the CFA’s transfer function with active feedback circuit (top) and without active feedback circuit (bottom).
Feedback resistor R1 in Fig. 6 is varied from 60 Ω to 30 kΩ to obtain various low frequency gains ranging from 6 dB to 60 dB. The cutoff frequency for 6 dB gain is 10.7 MHz and the cutoff frequency for 60 dB gain is 9.48 MHz. The cutoff frequency variation for a gain range of 54 dB is thus 11.4%. The transfer function of the overall CFA is shown in Fig. 8 (top trace). For comparison, a CFA without active feedback is simulated with all other design parameters unchanged. The result is shown in Fig. 8 (bottom trace), with a cutoff frequency variation from 312 kHz to 10 MHz. At a result, the bandwidth variation is reduced by 8 times with the proposed feedback technique. It should be note that without active feedback, the gain error also increases due to the relative large value of rx, which can be clearly observed by comparing the two simulation results in Fig. 8. Different from open loop design,
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