Collecting Traces in Dynamic Binary Translation Based Virtual Platforms Marcos Cunha, Nicolas Fournel and Fr´ed´eric P´etrot TIMA Lab, University of Grenoble Alpes
[email protected]
January 21, 2015
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Agenda
1
Introduction
2
Approach
3
Results
4
Conclusion and Perspectives
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Agenda
1
Introduction
2
Approach
3
Results
4
Conclusion and Perspectives
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Challenges in MPSoC Trend of # Processors / SoC for next years
>264 >256 >50
Source: ITRS Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Single vs Multiprocessor Debugging
Single processor Debugging printf and its variations (printk, write, ioctl, ... ) Dump of events Conventional debug is intrusive (gdb-like application)
Multiprocessor Debugging Traces as structured events Partial-Order of events Post-mortem trace analysis with gdb-like support
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Real vs Virtual Platforms Real platforms Available late for software development Complex trace ports to capture events in multiprocessor environment Hard to capture supplementary information, like causality
Virtual Platforms Available early for software development As accurate as the models are Easy to access supplementary information Non-intrusive solution Auto-generation of Traces
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Agenda
1
Introduction
2
Approach
3
Results
4
Conclusion and Perspectives
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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DBT Based TLM Virtual Platforms
Virtual Platforms: DBT + TLM DBT: Processors models (Translation block per block) TLM: Peripheral and interconnect models
DBT - Advantages Faster than Cycle Accurate Bit Accurate simulations Support for well known processors (ARM, MIPS, x86, ...)
DBT - Drawbacks Difficult development to support new targets and hosts No support for timing/power estimation
Marcos Cunha, Nicolas Fournel and Fr´ ed´ eric P´ etrot (University of Grenoble Alpes)
January 21, 2015
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Trace Definition
Event Definition e = {c, k, d, t}, where
c = component k = kind of event d = data t = timestamp
”Well Formed” Trace T = {E ,
