COMBINATIONAL LOGIC

COMBINATIONAL LOGIC

Digital Integrated Circuits

Combinational Logic

© Prentice Hall 1995

Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-CMOS


Combinational Logic


Combinational vs. Sequential Logic In

Logic In

Circuit

Out

Logic

Out

Circuit

State

(a) Combinational Output = f(In) Digital Integrated Circuits

(b) Sequential Output = f(In, Previous In)

Combinational Logic


Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Digital Integrated Circuits

Combinational Logic


Static CMOS VDD In1 In2 In3

PUN

PMOS Only F=G

In1 In2 In3

PDN

NMOS Only

VSS

PUN and PDN are Dual Networks Digital Integrated Circuits

Combinational Logic


NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A

B

X

Y

Y = X if A and B

A

X

B

Y

Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1 Digital Integrated Circuits

Combinational Logic


PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low A

B

X

Y

Y = X if A AND B = A + B

A

X

B

Y

Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0 Digital Integrated Circuits

Combinational Logic


Complementary CMOS Logic Style Construction (cont.)


Combinational Logic


Example Gate: NAND


Combinational Logic


Example Gate: NOR


Combinational Logic


Example Gate: COMPLEX CMOS GATE VDD B A C D

OUT = D + A•(B+C) A D B


C

Combinational Logic


4-input NAND Gate Vdd

VDD In1

In2

In3

In4 Out

In1 In2 Out

In3 In4

GND In1 In2 In3 In4 Digital Integrated Circuits

Combinational Logic


Standard Cell Layout Methodology

metal1

VDD Well

VSS Routing Channel signals


polysilicon

Combinational Logic


Two Versions of (a+b).c VDD

VDD

x

x GND

a

c

b

(a) Input order {a c b}


GND a

b

c

(b) Input order {a b c}

Combinational Logic


Logic Graph VDD x

b j

c

c

a

PUN

i

x

VDD

x b c

j

a PDN

i GND

a


b

Combinational Logic


Consistent Euler Path x

c i

x

b

VDD

a

j

GND

{ a b c} Digital Integrated Circuits

Combinational Logic


Example: x = ab+cd x

x c

b

V DD

x a

c

b

V DD

x a

d GND

d GND

(a) Logic graphs for (ab+cd)

(b) Euler Paths {a b c d} V DD

x GND a

b

c

d

(c) stick diagram for ordering {a b c d} Digital Integrated Circuits

Combinational Logic


Properties of Complementary CMOS Gates

High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)


Combinational Logic


Properties of Complementary CMOS Gates High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)


Combinational Logic


Transistor Sizing •for symmetrical response (dc, ac) •for performance V DD B

12

C

12

6

A

Input Dependent Focus on worst-case

6

D

F A D

1 B


2 2 C

2

Combinational Logic


Propagation Delay Analysis - The Switch Model RON

= VDD

V DD

Rp

Rp A

B F

F Rn CL

Rn

Rp

CL

A

B Rn A

(a) Inverter

Rp

Rp

B

A

A

VDD

(b) 2-input NAND

F

Rn

Rn

A

B

CL

(c) 2-input NOR

tp = 0.69 Ron CL (assuming that CL dominates!)


Combinational Logic


What is the Value of Ron?


Combinational Logic


Numerical Examples of Resistances for 1.2µm CMOS


Combinational Logic


Analysis of Propagation Delay VDD Rp A

1. Assume Rn =Rp = resistance of minimum sized NMOS inverter

Rp

B F Rn B Rn A

CL

2. Determine “Worst Case Input” transition (Delay depends on input values) 3. Example: tpLH for 2input NAND - Worst case when only ONE PMOS Pulls up the output node - For 2 PMOS devices in parallel, the resistance is lower t pLH = 0.69Rp CL

2-input NAND

4. Example: tpHL for 2input NAND - Worst case : TWO NMOS in series t pHL = 0.69(2R n)CL


Combinational Logic


Design for Worst Case V DD

V DD

1 A

1 F

2

CL

4

C

4

2

A

B

B

2

D

B

F

2 A

A D

2

1 B

2C

2

Here it is assumed that Rp = Rn Digital Integrated Circuits

Combinational Logic


Influence of Fan-In and Fan-Out on Delay VDD A

B

C

D

Fan-Out: Number of Gates Connected 2 Gate Capacitances per Fan-Out

A B C D

FanIn: Quadratic Term due to: 1. Resistance Increasing 2. Capacitance Increasing (tpHL )

tp = a1 FI + a2 FI 2 + a3 FO Digital Integrated Circuits

Combinational Logic


tp as a function of Fan-In 4.0 tpHL

tp (nsec)

3.0 2.0

tp

quadratic

1.0 linear

0.0

1

3

5 fan-in

7

tpLH 9

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4) Digital Integrated Circuits

Combinational Logic


Fast Complex Gate - Design Techniques •Transistor Sizing: As long as Fan-out Capacitance dominates

•Progressive Sizing: Out InN

MN

CL M1 > M2 > M3 > MN

In3

M3

C3

In2

M2

C2

In1

M1

C1


Distributed RC-line

Can Reduce Delay with more than 30%! Combinational Logic


Fast Complex Gate - Design Techniques (2) •Transistor Ordering critical path

critical path CL

In3

M3

In2

M2

C2

In1

M1

C1 (a)


CL

In1

M1

In2

M2

C2

In3

M3

C3 (b)

Combinational Logic


Fast Complex Gate - Design Techniques (3) •Improved Logic Design


Combinational Logic


Fast Complex Gate - Design Techniques (4) • Buffering: Isolate Fan-in from Fan-out

CL

CL


Combinational Logic


Example: Full Adder V DD VDD A

Ci A

B

B A

B Ci A

B

VDD

X Ci

Ci

A

S Ci

A

B

B

VDD A

B

Ci

Co

A B

Co = AB + Ci(A+B) 28 transistors Digital Integrated Circuits

Combinational Logic


A Revised Adder Circuit V DD VDD A

B

A

V DD A

B

B

Ci

B

Kill "0"-Propagate

A Ci

Ci

Co

S Ci

A

"1"-Propagate

Generate A

B

B

A

B

Ci

A B

24 transistors


Combinational Logic


Ratioed Logic VDD Resistive Load

VDD Depletion Load

RL

PDN VSS (a) resistive load

PMOS Load VSS

VT < 0

F In1 In2 In3

VDD

F In1 In2 In3

PDN VSS

(b) depletion load NMOS

F In1 In2 In3

PDN VSS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS Digital Integrated Circuits

Combinational Logic


Ratioed Logic VDD • N transistors + Load Resistive Load

• VOH = V DD

RL

• VOL =

RPN + RL

F In1 In2 In3

• Assymetrical response PDN • Static power consumption

VSS Digital Integrated Circuits

RPN

•tpL = 0.69 RL CL Combinational Logic


Active Loads VDD Depletion Load

VDD PMOS Load

VT < 0

VSS F In1 In2 In3

PDN

F In1 In2 In3

PDN

VSS depletion load NMOS


VSS pseudo-NMOS

Combinational Logic


Load Lines of Ratioed Gates

IL(Normalized)

1

Current source

0.75

0.5

Pseudo-NMOS

Depletion load 0.25 Resistive load 0 0.0


1.0

2.0

3.0 Vout (V)

Combinational Logic

4.0

5.0


Pseudo-NMOS VDD

A

B

C

D

F CL

VOH = VDD (similar to complementary CMOS) 2 VOL   kp 2 k n ( VDD – VTn )VOL – -------------  = -----( V DD – VTp ) 2  2 

V

kp – V ) 1 – 1 – -----= (V (assuming that V = V = V ) OL DD T T Tn Tp k n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! Digital Integrated Circuits

Combinational Logic


Pseudo-NMOS NAND Gate VDD

GND


Combinational Logic


Improved Loads V DD

M1

Enable

M2

M1 >> M2

F A

B

C

D

CL

Adaptive Load Digital Integrated Circuits

Combinational Logic


Improved Loads (2) VDD

VDD

M1

M2

Out A A B B

Out

PDN1

PDN2

VSS

VSS

Dual Cascode Voltage Switch Logic (DCVSL) Digital Integrated Circuits

Combinational Logic


Example

Out Out

B

B

A

B

B

A

XOR-NXOR gate Digital Integrated Circuits

Combinational Logic


Pass-Transistor Logic

Inputs

B Switch

Out

A Out B

Network B

•N transistors • No static consumption


Combinational Logic


NMOS-only switch C=5V

C=5V

M2 A=5V

A=5V B

B Mn M1

CL

VB does not pull up to 5V, but 5V - VTN Threshold voltage loss causes static power consumption Digital Integrated Circuits

Combinational Logic


Solution 1: Transmission Gate C A

C A

B

B C

C C=5V A=5V B CL C=0V Digital Integrated Circuits

Combinational Logic


Resistance of Transmission Gate

30000.0 Rn (W/L)p =(W/L)n = 1.8/1.2

R (Ohm)

20000.0 Rp

10000.0

0.0 0.0

Req

1.0

2.0

3.0

4.0

5.0

Vout


Combinational Logic


Pass-Transistor Based Multiplexer S

S

S

S

VDD S

A

V DD

M2 F

S M1 B

S

GND In1 Digital Integrated Circuits

Combinational Logic

In2 © Prentice Hall 1995

Transmission Gate XOR B

B M2 A

A

F M1

M3/M4 B

B


Combinational Logic


Delay in Transmission Gate Networks 5

5 V1

In

5

Vi

Vi-1 C

0

5

C

0

Vn-1

Vi+1 C

0

Vn

C

C

0

(a) Req In

Req

V1

Req

Vi

C

Vn-1

Vi+1 C

C

Req

Vn C

C

(b) m Req

Req

Req

Req

Req

Req

In C

CC

C

C

CC

C

(c)


Combinational Logic


Elmore Delay (Chapter 8) Vin

R1

C1

1

R2

Ri-1

2

i-1

Ci-1

C2

Ri

i

Ci

RN

N

CN

Assume All internal nodes are precharged to VDD and a step voltage is applied at the input Vin N τN =


N

N

i

∑ Ri ∑ Cj = ∑ C i ∑ R j i=1 j=i i=1 j=1

Combinational Logic


Delay Optimization


Combinational Logic


Transmission Gate Full Adder P VDD

Ci

A

P A

A

P B

VDD Ci

A P

Ci

S Sum Generation

Ci P B

VDD

A Co Carry Generation

P Ci

A Setup


VDD

P

Combinational Logic


(2) NMOS Only Logic: Level Restoring Transistor VDD VDD

Level Restorer Mr B A

Mn

M2 X

Out M1

• Advantage: Full Swing • Disadvantage: More Complex, Larger Capacitance • Other approaches: reduced threshold NMOS Digital Integrated Circuits

Combinational Logic


Level Restoring Transistor

5.0

with

5.0

3.0

VB

1.0 -1.00

without

3.0

with

VX

Vout (V)

without

2

t (nsec)

1.0 4

(a) Output node


6 -1.00

2

4

6

t (nsec) (b) Intermediate node X

Combinational Logic


Solution 3: Single Transistor Pass Gate with VT=0 VDD VDD

0V

5V

VDD

0V

Out

5V

WATCH OUT FOR LEAKAGE CURRENTS Digital Integrated Circuits

Combinational Logic


Complimentary Pass Transistor Logic A A B B

Pass-Transistor F

Network

(a) A A B B

B

Inverse Pass-Transistor Network

B

B

A

F

B

B

A

A

B

F=AB

A

B

F=A+B

F=AB AND/NAND


A

F=A ⊕ ΒÝ

(b)

A

A

B

B

F=A+B

B OR/NOR

Combinational Logic

A

F=A⊕ ΒÝ

EXOR/NEXOR


4 Input NAND in CPL


Combinational Logic


Dynamic Logic V DD φ

V DD φ

Mp

Me

Out CL

In1 In2 In3

PDN

In1 In2 In3

PUN Out

φ

Me

φ

φn network

2 phase operation:

Mp

CL

φp network

•Precharge •Evaluation


Combinational Logic


Example V DD φ

Mp

•N + 1 Transistors Out •Ratioless •No Static Power Consumption

A

•Noise Margins small (NML ) C

•Requires Clock

B

φ

Me


Combinational Logic


Transient Response 6.0 φ

Vout (Volt)

4.0

Vout

PRECHARGE

EVALUATION

2.0

0.0 0.00e+00 Digital Integrated Circuits

2.00e-09

t (nsec)

4.00e-09

Combinational Logic

6.00e-09 © Prentice Hall 1995

Dynamic 4 Input NAND Gate VDD

Out In1 In2 In3 In4

φ


GND

Combinational Logic


Reliability Problems — Charge Leakage VDD φ

φ

Mp Out (1)

CL

t

A Vout

(2)

φ

precharge

evaluate

Me t

(a) Leakage sources

(b) Effect on waveforms

Minimum Clock Frequency: > 1 MHz Digital Integrated Circuits

Combinational Logic


Charge Sharing (redistribution) case 1) if ∆V out < VTn

VDD φ

Mp Out CL

A

Ma

B=0

φ

Mb

Me

X Ca

Cb


C V = C V t + C (V – V ( V )) L DD L out ( ) a DD Tn X or Ca ∆V out = Vout ( t ) – V DD = –-------- ( V DD – V Tn ( V X )) CL

case 2) if ∆V out > VTn C  a  ∆Vout = –V DD ----------------------  Ca + CL 

Combinational Logic


Charge Redistribution - Solutions VDD

VDD φ

Mp

φ

Mbl

Mp

Mbl

φ

Out Out A

Ma

A

Ma

B

Mb

B

Mb

φ

Me

φ

Me

(a) Static bleeder Digital Integrated Circuits

(b) Precharge of internal nodes Combinational Logic


Clock Feedthrough VDD φ

could potentially forward bias the diode

Mp Out CL A

B

φ

Ma

Mb

Me


5V φ

X Ca

Cb

overshoot out

Combinational Logic


Clock Feedthrough and Charge Sharing

feedthrough

output without redistribution (Ma off) 6

out 4 V (Volt)

φ internal node in PDN

2

0

0

1

2

3

t (nsec) Digital Integrated Circuits

Combinational Logic


Cascading Dynamic Gates VDD

φ

VDD

φ

Mp

Mp

V

φ In

Out2

Out1

Out1 VTn

In

∆V

Out2 φ

φ

Me

Me

t (b)

(a)

Only 0→ 1 Transitions allowed at inputs! Digital Integrated Circuits

Combinational Logic


Domino Logic VDD

VDD VDD

φ

φ

Mp

Mp

Out1

Mr Out2

In1 In2

PDN

PDN

In4

Static Inverter with Level Restorer

In3 φ

Me


φ

Me

Combinational Logic


Domino Logic - Characteristics •Only non-inverting logic •Very fast - Only 1->0 transitions at input of inverter move VM upwards by increasing PMOS • Adding level restorer reduces leakage and charge redistribution problems • Optimize inverter for fan-out


Combinational Logic


np-CMOS VDD φ

In1 In2 In3

Mp

PDN

VDD φ

Out1

Me

PUN

In4

Out2 φ

Me

φ

Mp

Only 1→ 0 transitions allowed at inputs of PUN Digital Integrated Circuits

Combinational Logic


np CMOS Adder VDD φ A1

V DD

V DD

φ

φ B1

B1

A1

A1 φ

φ

C i1 A1 B1 φ

V DD A0

φ

S1

VDD

φ

B0

Ci1

B1

VDD

A0

φ

φ

Ci2

V DD

B0 φ

Ci1

φ A0

B0 φ

C i0

φ B0 A0 C i0

S0

C i0 Carry Path Digital Integrated Circuits

Combinational Logic


Manchester Carry Chain Adder V DD φ

0.5 P0

P1

M0

M1

3 C i,0

3.5

φ

4

G0


3

2.5 G1

3.5

P2 M2 2.5

3

P3 M3

2 G2

2

1.5 G3

2.5

Total Area: 225 µm × 48.6 µm

P4 M4 1.5

2

Combinational Logic

1 G4

1

C o,4

1.5


CMOS Circuit Styles - Summary


Combinational Logic


COMBINATIONAL LOGIC

COMBINATIONAL LOGIC

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