Combinational

Part IA Engineering

Aims

Digital Circuits &

The aims of the course are to:

• Familiarize students with combinational and sequential digital logic circuits, the analogue-digital interface, and the hardware and basic operation of microprocessors, memory and the associated electronic circuits which are required to build microprocessor based systems.

Information Processing Handout 1 Combinational Logic

Richard Prager Tim Flack January 2009 1

• Teach the engineering relevance and application of digital and microprocessor-based systems, give students the ability to design simple systems of this kind, and understand microprocessor operation at the assembly-code level.

2

From Semiconductors to Computers

Contents of Handout 1 Section A

Introduction to logic gates. This section covers the material for questions 1 and 2 on examples paper 1.

Section B

Building gates from transistors. This section covers the material for questions 3 – 6 on examples paper 1.

Section C

Boolean algebra for logic design. Introduction to VHDL. This section covers the material for questions 7 – 11 on examples paper 1.

Section D

Karnaugh maps for logic design. This section covers the material for questions 1 – 5 on examples paper 2.

• build transistors from semiconductors

• build gates from transistors

• build logic functions from gates

• build flip-flop bistables from logic

• build counters and sequencers from flip-flops

• build microprocessors from sequencers

• build computers from microprocessors 3

4

Logic Variables • Logic variables

Handout 1 Section A

• Binary variables • Boolean variables

Introduction to Logic Gates All names for the same thing. In this section we introduce Boolean algebra and logic gates.

A variable that can take only two values: • TRUE or FALSE

Logic gates are the building blocks of digital circuits. • 1 or 0 In electronic circuits the two states of a logic variable are represented by two voltage levels. For example, a high voltage for 1 and a low voltage for 0. 5

6

Uses of Simple Logic

Uses of Simple Logic

Washing Machine Heating Boiler

If drum not turning and no water in drum and program finished then permit door to be opened.

If chimney not blocked and house is cold and pilot light lit then open main fuel valve to start up boiler.

T W P L

B = chimney blocked

= = = =

drum turning water in drum program active door unlocked

C = house is cold P = pilot alight V

L = ( NOT T ) AND ( NOT W ) AND ( NOT P )

= open fuel valve We can write this using bars above the symbols to denote NOT.

V = ( NOT B ) AND C AND P L = T AND W AND P 7

8

Logic Gates Electronic circuits that have logic signals as their inputs and outputs are known as LOGIC CIRCUITS or DIGITAL CIRCUITS.

NOT Gate

Basic logic circuits with one or more inputs, and one output, are also known as GATES. GATES are used as building blocks in the design of more complex logic circuits. There are several ways of representing logic functions:

• Graphical symbols used to represent the gates.

Graphical Symbol

A

Input-output Map

Y

A

0 1

1 0

Boolean representation

Y =A

A NOT gate is called an ‘inverter’.

Y is TRUE if and only if A is FALSE. A circle on the output of a gate always implies that it is an inverting output.

• Input-output maps.

• Boolean algebra. 9

10

OR Gate

AND Gate

Graphical Symbol

Input-output Map

A

A B

Y

Graphical Symbol

Boolean representation

Input-output Map

A

B 0 0 0

1 0

1 0

1

B

Y = A.B

Y is TRUE if and only if A is TRUE and B is TRUE. In Boolean algebra AND is represented by a dot .

11

A B

Y

0 0 0

1 1

1 1

1

Boolean representation

Y =A+B

Y is TRUE if A is TRUE or B is TRUE (or both). In Boolean algebra OR is represented by a plus sign +

12

EXCLUSIVE OR Gate

Graphical Symbol

Input-output Map

A

A B

Y

B 0 0 0

1 1

1 1

0

NAND Gate

Boolean representation

Graphical Symbol

Input-output Map

A

B

Y =A⊕B

A B

Y

0 0 1

1 1

1 1

0

Boolean representation

Y = A.B

Y is TRUE if A is TRUE or B is TRUE but not both.

Y is TRUE if A is FALSE or B is FALSE (or both).

In Boolean algebra XOR is represented by an ⊕ sign.

Y is FALSE if and only if A is TRUE and B is TRUE.

13

14

Boiler Example NOR Gate

If chimney not blocked and house is cold and pilot light lit then open main fuel valve to start up boiler. B = chimney blocked

Graphical Symbol

Input-output Map

A

A B

Y

B 0 0 1

1 0

1 0

0

Boolean representation

C = house is cold P = pilot alight V

V = B.C.P

Y =A+B

Y is TRUE if and only if A is FALSE and B is FALSE. Y is FALSE if A is TRUE or B is TRUE (or both).

= open fuel valve

B C

V

P 15

16

Washing Machine Example Handout 1 Section B If drum not turning and no water in drum and program finished then permit door to be opened.

Building Gates from Transistors

T = drum turning W = water in drum P = program active

Logic circuits are non-linear so we first have to learn a graphical technique for analyzing non-linear circuits.

L = door unlocked

The construction of an NMOS inverter from an N-channel field effect transistor is described.

L = T .W .P

We then outline the structure of NMOS AND gates and OR gates, and estimate the speed of NMOS circuits.

T W

L A discussion of the power consumption of NMOS gates leads to the introduction of the CMOS inverter circuit.

P 17

18

Solving Non-linear Circuits Implementing Logic Gates A high voltage represents logic 1. A zero voltage represents logic 0.

A

The same technique will still work when we introduce non-linear components.

Y

10v 1Ω x 2Ω 0v

V

in

Inverter circuit

Vout Current through 1 ohm

Current through 2 ohm

V+

ic rist istor e t c res ara Ch ohm of 2

Note that it is non- V out linear. 0v

0v

V+ V

in

19

Voltage across 2 ohm

tic ris te ac ar hm Ch 1 o of

The graph shows an ideal characteristic for an inverter circuit.

Solve a simple circuit graphically.

x Voltage across 10v 1 ohm 20

10v 1Ω x Thing

x 1Ω 0v

Current through Thing

Current through 1 ohm

C of hara 1 ct oh er m ist

tic ris te ac ar hm Ch 1 o of

0v Voltage across Thing

Thing

0v

Current through 1 ohm Characteristic of Thing

The characteristic of I the upper component is drawn backwards along the V axis, starting at the supply voltage.

10v

V

V

Current through Thing

Thing characteristic

ic

Thing Suppose we now recharacteristic place the lower resistor I with a non-linear component (that we will call a ‘Thing’).

x Voltage across 10v 1 ohm

0v

21

Voltage across 1 ohm

Characteristic of Thing x

Voltage across Thing

10v

22

N-channel MOSFET OFF

Building Gates from Transistors

Drain +VD Gate

We start by building logic gates out of N-channel MOSFETs.

111 000 n+ 000 111

0v

Source 0v

111 000 n+ 000 111

Reverse biased p-n junction

p-type substrate

Metal Oxide Semiconductor Field Effect Transistor Enhancement mode: means off when VGS = 0. The alternative is a depletion mode transistor which is on (i.e. conducts from drain to source) when VGS = 0.

D

Silicon dioxide insulator G

ON Drain +VD Gate

+VG

Source 0v

111 000 000 111 n+ 00 11 000 111 00 11 00 11 00 11 000 111 00 11 000 111 n+ 000 111

S

N-type layer: inversion

p-type substrate 23

24

NMOS Inverter

NMOSFET Characteristics IDS 12 mA 10 8 6 4 2 0

VGS = 10v VGS = 8v VGS = 6v

0

2

4

6

10 8 VDS Volts

Here is the circuit to implement an inverter using an NMOS FET and a 1kΩ resistor.

VDD = 10v 1kΩ

VGS = 4v VGS = 2v VGS = 0v

Vout

Vin VGS

IDS as a function of VGS at constant VDS

The transistor conducts when VGS reaches the Threshold voltage: VT

VDS 0v

IDS mA

IDS 12 mA 10 8 6 4 2 0

0

3 VT

VGS

6 Volts

VGS = 10v VGS = 8v VGS = 6v

0

2

4

6

8 10 VDS Volts

NMOS FET Characteristic 25

VGS = 4v VGS = 2v VGS = 0v

I 12 mA 10 8 6 4 2 0

0

2

4

6 V

8 10 Volts

Resistor Characteristic 26

IDS 12 mA 10 8 6 4 2 0

VGS = 10v

Voltage Levels

VGS = 8v VGS = 6v

0

2

4

6

8 10 VDS Volts

VGS = 4v VGS = 2v VGS = 0v

The input-output characteristic of the gate is far from the ideal we originally wanted.

10 Vout 8 6 4 2 0

However if we say:

10

2

4

6

8

Vin

Vout 8

voltage > 9v voltage < 2v

6 4

is logic 1 is logic 0

the gate will work:

2 0

2

4

6

8

Vin

Vin > 9v Vin < 2v

10

27

⇒ ⇒

Vout < 2v Vout > 9v

28

10

VDD

VDD R

R VY

VA

VY

VB

VA 0v

What sort of gate is this? Think of the transistors as switches. When VGS is high they conduct. Otherwise they don’t conduct. A low

B low

Y high

high low

low high

low low

high

high

VB 0v

A low high low

B Y low high low high high high

high

high

low

low

This corresponds to a NAND gate: Y = A.B

This corresponds to a NOR gate: Y = A + B 29

30

Speed of NMOS Logic

Benefit of Using Gates When we have a complicated logic function to implement, (eg. the boiler example previously discussed V = B.C.P ), you don’t have to design a special transistor circuit to provide the functionality.

One of the main speed limitations in real NMOS logic is due to stray capacitance. The output of each gate is connected by a length of metal track to the input of the next. This has capacitance to ground. We therefore modify the circuit model.

Instead you just buy an integrated circuit (or chip) that provides the appropriate gates.

VDD = 10v IR R = 1kΩ Vout

ID IC

For the boiler example we would need a three-input AND gate and an inverter. 31

C

Vin 0v

32

Assume that initially Vin is high, hence Vout = 1 V.

Using a FET to replace the Resistor

At time t = 0, Vin falls to 0 V, so ID = 0. A big advantage of chips is that they are small. Implementing a resistor on a chip takes up a lot of space on the silicon.

IR = IC VDD − Vout dVout = C R dt

Fortunately it is possible to make a MOSFET behave (almost) like a resistor by connecting the Gate to the Drain. Thus VGS = VDS .

So IDS 12 mA 10 8 6 4 2 0

Vout V dVout + = DD dt RC RC

−t ⇒ Vout = VDD + (1 − VDD ) exp RC 



Which means that 95% of the voltage change will take a time of 3RC. 33

VGS = 10v VGS = 8v VGS = 6v

0

2

4

6

8 10 VDS Volts

VGS = 4v VGS = 2v VGS = 0v

It’s not quite a straight line, so behaviour will not be the exactly same as a resistor. However, it’s roughly like 900Ω. 34

Power Consumption Smaller NMOS Inverter 10

VDD = 10v

Using a FET to approximate a resistor we can produce a revised design for an inverter circuit that is easier to miniaturize.

VDD = 10v

6 Vout 4 2

0v

0

2

4

6

8

Vin

10

When Vout = 10v there is no current (ID = 0. There is therefore no power dissipated.

Vout

However, when Vout 6= 10v current will flow down through the resistor and heat will be generated.

switch

Vin

8

1kΩ

Vin

pseudo-resistor (load)

Vout

For example, when Vin = 10v ⇒ Vout = 1v and ID = 9mA so 81mW will be dissipated in the resistor and 9mW will be dissipated in the FET.

0v 35

36

Complementary MOS CMOS Inverter The problem with NMOS logic is power dissipation in the resistors. To solve this, CMOS logic was invented. This uses both NMOSFETS and PMOSFETS.

VSS = 10v

PMOSFETS are essentially NMOSFETS with all the polarities reversed: IDS -12 mA -10 -8 -6 -4 -2 0

VGS = -10v

S G PMOS D D

Vin

VGS = -8v

NMOS G

VGS = -6v

-2

0

-4

-6

-8 -10 VDS Volts

S

VGS = -4v VGS = -2v VGS = 0v

0v

S

D

Vin

G

low high

G S

Vout

NMOS PMOS off on

on off

Vout high low

D 37

38

PMOS

NMOS Characteristic IDS 12 mA 10 8 6 4 2 0

VGS = 10v VGS = 8v VGS = 6v

0

2

4

6

10 8 VDS Volts

VGS = 4v VGS = 2v VGS = 0v

PMOS Characteristic IDS -12 mA -10 -8 -6 -4 -2 0

VGS = -10v VGS = -8v VGS = -6v

0

-2

-4

-6

-8 -10 VDS Volts

VGS = -4v VGS = -2v VGS = 0v

PMOS

VGS = -10v 12 I 10 mA 8 6 4 2 0

VGS = -6v 12 I 10 mA 8 6 4 2 0

Intersection of curves NMOS

VGS = 4v 0

2

4

6

8

10

Voltage across NMOS Voltage across PMOS

(b) Vin = 4v ⇒ Vout = 9.5v, I = 2.7mA. NMOS

Intersection of curves

0

2

4

6

8

VGS = 0v

10

Voltage across NMOS

12 10 Intersection of curves I 8 mA 6 4 2 0 0 2 4 6 8

NMOS

VGS = 6v PMOS

VGS = -4v 10

Voltage across PMOS Voltage across NMOS

(a) Vin = 0v ⇒ Vout = 10v. No current flows.

(c) Vin = 6v ⇒ Vout = 0.5v, I = 2.7mA. 39

40

12 I 10 mA 8 6 4 2 PMOS

VGS = 0v

Power in CMOS Inverter NMOS

Intersection of curves

0

2

4

6

VGS = 10v

8

10

Voltage across PMOS (d) Vin = 10v ⇒ Vout = 0v. No current flows.

I /mA

Power /mW

0 2 4 5 6 8 10

0.0 1.0 2.7 3.6 2.7 1.0 0.0

0 10 27 36 27 10 0

Note that current 40 only flows when the Power gate is changing 30 state. This means mW that power is only 20 dissipated as the 10 gate switches on or off.

Using these values we 10 can construct the input- Vout 8 output characteristic of the inverter circuit. Note 6 that the CMOS inverter 4 is much closer to our 2 ideal than the NMOS inverter was. 0

Vin

2

4

6

8

Vin 41

10

0

2

4

6

8

Vin 42

10

CMOS NAND Gate

Logic Families

VSS = 10v NMOS Compact, slowish, cheap.

T2

T1

VB

VA

CMOS Propagation delay 8–50 nS, max clock frequency 12–40 MHz for gates in individual packages. Power consumption < 10−6 W/gate when not changing, and about 10−4 W/gate when changing at 100 kHz.

VY

T3

TTL Constructed from bipolar transistors. Propagation delay 1.5–10 nS, max clock frequency 35– 200 MHz. Power consumption is about 10−2 W/gate.

T4

0v VA low low high high

VB low high low high

T1 on on off off

T2 on off on off

T3 off on off on

T4 off off on on

VY high high high low

ECL Constructed from bipolar transistors. High speed. High power consumption; current flows all the time. 43

44

Handout 1 Section C Combinational Logic Design Boolean Algebra for Logic Design

In this section we introduce the laws of Boolean algebra and show how it can be used to design combinational logic circuits. We then introduce the hardware description language VHDL. This language can be used to enable computer-aided design of logic circuits.

In our washing machine example we needed to imple- T ment the logic function W L = T .W .P

L

P

This could have been achieved more simply using the fact that L = T .W .P = (T + W + P )

Combinational logic circuits do not have an internal stored state; the output is a function of the current inputs. (Later in the course we will study circuits with a stored internal state. These are called sequential logic circuits.) 45

so a single NOR gate will do the whole job.

T W P

L 46

We need: In an extreme example, it would be very useful to be able to work out that A

1. Techniques for simplifying logic expressions. Simpler expressions mean fewer gates which lead to lower cost.

B

2. Techniques for manipulating expressions so that the required function can be computed using gates of only certain types. We thus only need to stock a limited range of gates which can be readily available and cheap.

Y C D

can be replaced by We are going to study two ways of solving these problems: Boolean algebra and Karnaugh maps.

B C

Y Boolean algebra rigorous, computable.

This sort of problem can be solved using Boolean algebra and Karnaugh maps. 47

Karnaugh maps visual, exhaustive, copes with up to 5 variables. 48

Boolean Algebra

ORs A+0=A A+A=A A+1=1 A+A=1

Commutation A+B =B+A A.B = B.A

normal normal

Association (A + B) + C = A + (B + C) (A.B).C = A.(B.C)

normal normal

ANDs A.0 = 0 A.A = A A.1 = A A.A = 0

AND takes precedence over OR. For example A.B + C.D = (A.B) + (C.D). Every Boolean law has a dual: any valid statement is also valid with

Distribution A.(B + C + . . .) = (A.B) + (A.C) + . . . A + (B.C. . . .) = (A + B).(A + C). . . .

normal NEW

Absorption A + (A.C) = A A.(A + C) = A

NEW NEW

49

. + 0 1

replaced by replaced by replaced by replaced by

+ . 1 0

50

Every Variable in Every Term A useful technique is to expand each term until it includes one instance of each variable (or its compliment). It may be possible to simplify the expression by canceling terms in this expanded form.

Show that A.(A + B) = A.B A.(A + B) = A.A + A.B = 0 + A.B = A.B

If there are two variable (A and B) then terms like A.B or A.B are fine as they stand because they already include all the variables. A term A would need to be expanded to A.B + A.B.

Show that A + A.B = A + B

Here, as an illustration, the technique is used to prove the absorption rule:

A + (A.B) = (A + A).(A + B)

A + A.B

= 1.(A + B) = A+B

= A.B + A.B + A.B =A 51

52

De Morgan’s Theorem Simplify X.Y + Y .Z + X.Z + X.Y.Z

A + B + C + . . . = A.B.C. . . .

X.Y + Y.Z + X.Z + X.Y.Z = X.Y + Y.Z + X.Z

A.B.C. . . . = A + B + C + . . .

( X.Y + X.Y.Z = X.Y )

A + B + C + . . . = A.B.C. . . . A.B.C. . . . = A + B + C + . . .

= X.Y.Z + X.Y.Z + X.Y.Z + X.Y.Z + X.Y.Z + X.Y.Z In a simple expression like A + B + C (or A.B.C) you can change all the operators from OR to AND (or vice versa) provided you put a bar over each term individually and a further bar over the whole expression.

= X.Y + Y.Z

53

54

Proof of De Morgan’s Theorem Washing Machine Example For two variables we can prove A + B = A.B and A.B = A + B using a truth table. A 0 0 1 1

B 0 1 0 1

A+B 1 0 0 0

A.B 1 1 1 0

A 1 1 0 0

B 1 0 1 0

A.B 1 0 0 0

A+B 1 1 1 0

In our washing machine example we needed to implement the logic function L = T .W .P . This can be simplified with a single application of De Morgan’s theorem: L = T .W .P = T +W +P

Extending to more variables is by induction: A + B + C = (A + B).C = (A.B).C = A.B.C etc.

55

56

Show that A.B+A.(B+C)+B.(B+C) = B+A.C Simplify A.B + A.(B + C) + B.(B + C)

A.B + A.(B + C) + B.(B + C) = A.B + A.B + A.C + B.B + B.C (distribute)

A.B + A.(B + C) + B.(B + C)

= A.B + A.B + A.C + B + B.C

(B.B = B)

= A.B + A.B.C + B.B.C

(De Morgan)

= A.B + A.C + B + B.C

(repeated A.B)

= A.B + A.B.C

(B.B = 0)

= A.B + A.C + B

(B + B.C = B)

= A.B

(absorption))

= A.C + B

(A.B + B = B)

57

58

Simplify (A.B.(C + B.D) + A.B).C.D

Simplify: A B Y

(A.B.(C + B.D) + A.B).C.D C

= (A.B.(C + B + D) + A + B).C.D (De Morgan) = (A.B.C + A.B.B + A.B.D + A + B).C.D (distribute) = (A.B.C + A.B.D + A + B).C.D (cancel A.B.B) = A.B.C.D + A.B.D.C.D + A.C.D + B.C.D (distribute) = A.B.C.D + A.C.D + B.C.D (cancel A.B.D.C.D) = (A.B + A + B).C.D (distribute) = (A.B + A.B).C.D (De Morgan) = C.D (A.B + A.B = 1) 59

D

Y

= A.B.B.C.B.C.C.D = (A.B + B.C).(B.C + C.D) (De Morgan) = A.B.B.C + A.B.C.D + B.C.B.C + B.C.C.D (distribute) = A.B.C + A.B.C.D + B.C + B.C.D (remove repeated variables) = B.C (absorption) 60

Algebraic Logic Design

Solution using any gates.

A power plant is cooled by 3 ventilation fans, numbered 1 to 3, with flow rates F , 2F and 3F respectively. An alarm is to be sounded if the plant is running and the air flow rate is less than 3.5F . Design a logic circuit to do this.

A1 A2 A3 Y

B

Stage 1: assign logic variables. A1 implies that fan 1 is running. A2 implies that fan 2 is running. A3 implies that fan 3 is running. B implies that the plant is running. Y sounds the alarm.

Solution using only NAND gates and inverters. Y

= (A3 + A1.A2).B = A3.B + A1.A2.B = (A3.B).(A1.A2.B)

Stage 2: convert the problem to algebraic form. If A3 = 0 or if both A1 and A2 equal 0 then, provided A1

the plant is running, we must sound the alarm.

A2

Y

= (A3 + A1.A2 + A1.A2.A3).B = (A3 + A1.A2).B

B Y A3 61

62

To produce a solution using only NOR gates it is often best to go back to the original problem and write down an expression for when the alarm should be off i.e. Y

Standard Boolean forms Sum of Products (SOP): usually best to write down an expression for Y directly. Y = A3.B + A1.A2.B

Y

= A1.A3 + A2.A3 + B

Product of Sums (POS): usually best to write down an expression for Y and use De Morgan’s theorem.

= (A1 + A3) + (A2 + A3) + B ⇒Y

Y

= (A1 + A3) + (A2 + A3) + B

= A1.A3 + A2.A3 + B = (A1 + A3) + (A2 + A3) + B

⇒Y

= (A1 + A3).(A2 + A3).B

A1

It is not easy to convert between POS and SOP by algebraic manipulation. Best to consider all the binary permutations not included in one expression and then write down the other to include them. A Karnaugh map makes this easier.

A3 A2

Y

B 63

64

VHDL Structure of VHDL Computer-aided design tools are required for the development of complex digital systems. These tools enable the simulation, modelling and testing of designs before they are built. A hardware description language is required to describe the systems. It must be clear and readable for the designer, yet sufficiently precise to enable rigorous testing of the design.

Very high speed integrated circuit hardware description language, abbreviated VHDL, has been developed over many years and is the IEEE standard 1076-1993. 65

VHDL describes circuits in terms of design entities. Each entity consists of two parts. The interface and the architecture specification. entity compont name is list of input and output ports end compont name; architecture arch name of compont name is declarations of internal signals; begin description of what the the entity does and how it is implemented end arch name;

66

Definition of Logic Gates

Definition of More Logic Gates

entity INV is port(A : in BIT; Y : out BIT); end INV;

entity NOR2 is port(A, B : in BIT; Y : out BIT); end NOR2;

architecture IMOD of INV is begin Y