International Conference on Embedded Systems - (ICES 2014)
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Comparison of different attributes in modeling a FSM based vending machine in 2 different styles Varun Vaid Dept. of Electrical Engineering Shiv Nadar University UP, INDIA
[email protected] Abstract—Vending Machine as we all know is a machine which can vend different products which is more like an automated process with no requirement of man handling which we normally see in fast moving cities because of fast paced life. This paper compares different aspects like area, timing constraint, speed, power dissipation of a vending machine with 2 different design styles algorithm while installation. FSM based algorithm has been utilized to simulate model, synthesize the machine on the stratix III family of FPGA provided with quartus design tool which is logic device design software from Altera. Index Terms — Algorithm, Stratix, Vending machine. I.
Automated,
Quartus,
7. If no inputs are active, the state machine stays in the current state. 8. Outputs: All produce a pulse that activates the release mechanism: Ro: Return out (all money in the machine) Wo: Water out, Co: Soft drink out So: Snacks out, out10: Rs 10 out II.
STATE DIAGRAM
FPGA,
INTRODUCTION
Vending machine is an automated product dispenser which is normally installed in supermarkets, railway stations, offices, schools and various other public areas. There are various vending machine already present today some of them talk about concept [1] [3] some talk about the full implementation [2] [4] from scratch on some particular FPGA family. Our aim will be confined towards developing 2 different algorithm for a vending machine as described below and then finding out the switching speed, timing constraint, power, area requirement and usability of logic present in stratix fpga family in order to find out more efficient and synthesizable machine as for our vending machine specification. Vending machine features to be implemented is described as below: 1The machine takes multiples of Rs10 only (rs10). 2. The machine can dispense: Water: Rs 20 (Wi) Snacks: Rs 20 (Si) Soft Drink: Rs30 (Ci) 3. It has a Cancel button (Cc) 4. Only one input may be active at a time 5. A product can be dispensed in one clock cycle 6. If more than Rs 30 is inserted, the money is automatically returned
978-1-4799-5026-3/14/$31.00©2014 IEEE
Fig. 1. State diagram for 1st type of vending machine.
Initially the machine was in its reset state which we called state A for the design purpose Given an input of Rs 10 the machine goes in its 2nd state which was state B upto this point the vending machine is holding Rs 10 in its account and the user has 2 choices either to cancel the vending process with the input of Cc which is present on the machine or put in another Rs 10 note in the machine and go on to the next state which is state D .Now at this stage vending machine accumulated Rs 20 hence user is eligible to select choices between water or snacks both of which are of Rs 20 and then go back to its initial state else hit Cc button to stop the process or else put in another Rs 10 note in the machine to vend the soft drink which costs Rs 30 so by now the user has reached state G ,another Rs 10 note will be simply rejected and signal out10 goes high throwing off the extra Rs 10 out of the machine from this state user can select any one
International Conference on Embedded Systems - (ICES 2014)
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of the three products to vend from the vending machine i.e soft drink (Co), water bottle (Wo) or snacks (So) or one can even Cc and all money will be returned by pushing Ro signal. Total number of states used is from A to H i.e 8 states making it a little superfluous. Next we implemented the same vending machine with same features with a little more adept way so as to save some area and state requirement and then find out if the desired machine is more efficient or less efficient than the previous little more area taking machine in terms of various important aspects of a design cycle. The minimized state diagram for vending machine is shown below Fig.3 When the machine is in state E and cancel Cc button is pressed the ro signal which is the return money signal goes high taking it back to the A state which is the initial state.
Fig. 2 State diagram for 2nd type of vending machine with fewer states.
So after making the 2 types of state machine diagram for the proposed vending machine we implemented this project in VHDL programming on the altera software tool in order to find out various aspects and conditions imposed on our proposed design on stratix FPGA family.
III.
Fig.4 When the machine is in state E and snacks button Si is pushed the snacks out signal (so) goes high returning the machine to its B state which is holding Rs 10.
SIMULATION RESULTS
Some random cases were taken for simulation purpose to check for vending machine working condition.
Fig5. When the machine is in state D holding Rs 20 and given input of Rs10 signal is high as soon as the state E finishes its time period the extra 10 rupees are returned back shown by the out10 signal going high because machine can only hold up to Rs 30 .
International Conference on Embedded Systems - (ICES 2014)
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TABLE II. TIMING AND POWER ANALYSIS DATA FOR 1ST TYPE OF VENDING MACHINE
Timing constraints
ANALYSIS AND SYNTHESIS RESULTS
IV.
After checking the design for logic correctability implementation was done for both type of design in Quartus design tool to check for its various attributes between these 2 types of machine logic and finally compare between the two. For the 1st type of state machine diagram for the vending machine the usage data in terms of various LUTs and logic utilization on the stratix family the summary is given as TABLE I Resources
25
Dedicated logic register
16
Total combinational function
25
Estimated ALMs
13
I/O pins
15 16 161
1
st
design
machine PRE
Wi
D
y
shown
Q
Q[2..0]
E
WideOr1
D
ENA
C
396.93mW
I/O thermal power dissipation
27.48mW
Resources
Usage
Combinational ALUTs
21
Dedicated logic register
13
Total combinational func.
21
Estimated ALMs
11
CLR
I/O pins
15
Maximum fan out
13
Total fan out
141
Average Fan out
2.20
B A
out10~reg0 WideOr2
0 0
424.41mW
Core static thermal dissipation
F
clk
Si
Total Thermal power dissipation
G
Ci
rs10
is
Q[2..0]~reg0
WideOr0 H
Cc
Actual time
TABLE III.
Total fan out
Reset
Type of delay
Now we will analyze and synthesize the 2nd type of state machine designed for our vending machine so as to check out various changes occurred in the output parameters due to new type of algorithm implemented with less number of states.
Maximum fan out
RTL diagram (1st type) RTL view for the below:
Actual time 3.864ns 7.290ns -2.058ns 2.5 ns
Power constraints
Usage
Combinational Arithmetic LUTs
Cc Ci Clock Res et rs 10 Si Wi
Type of delay Worst case setup time(tsu) Worst case clock to out (tco) Worst case hold (th) Clock period
0
0
1
1
out10~2
1
out10~3
PRE D
Q
out10
ENA CLR
out10~0 0 1
1
out10~1 Wo~reg0
0 0
1
0 1
Wo~0
1
Wo~1
D
PRE
Q
Wo
ENA CLR
So~reg0
0 0
1
0 1
So~0
1
So~1
D
PRE
Q
So
ENA CLR
Ro~reg0
0 0
1
0 1
Ro~0
1
Ro~1
PRE D
Q
Ro
ENA CLR
1
Co~0
2nd design
machine
is
shown
Co~reg0
0 0
RTL diagram (2nd type) RTL view for the below:
0 1
1
Co~1
Res et
PRE D
Q
Co
CLR
Co~reg0
0 0
0
1 0
0
1
Cc Ci Clock
0
Cc Ci
E
clk
D
Reset
rs10 Si Wi
y
1
B
Si
A
1
Co~3
0
1
So~reg0 OUT
0 1
0
1
Q
So
CLR
So~3 out10~reg0 0
1
1 0 1
0
1
0 1
out10~3
0
1
out10~1
Ro~0
PRE
SELECTOR
1
So~2
0
out10~0
1
D
ENA
0
1
So~1
0
Wo
DATA[1..0]
1
So~0
0
Q
CLR SELECTOR
SEL[1..0]
Timing and power analysis data (1 type) For the 1st type of machine after performing the classic timing analysis and powerplay power analysis the results obtained are as follows.
PRE
ENA
1
0
st
D
DATA[1..0] 0
Wo~4 Selector5
Wo~2
Wo~0
0
Co
Wo~reg0 OUT
1
Wo~3
0
1
Wo~1
Q
CLR
Co~5 Selector6
SEL[1..0]
0
1
1
PRE
ENA
1
WideOr0
0 0
Co~6
0
1
Co~4
Co~1
C
rs10
1
Co~2
Wi
0
D
1
Co~0
ENA
D
1
Ro~1
PRE D
Q
out10
ENA CLR
out10~2 Ro~reg0 PRE
Q
Ro
ENA CLR
Q~0
Q[1]~reg0
Q~1
Q[0]~reg0
D
PRE
Q
ENA CLR
D
Q[2]~reg0 D
PRE
PRE
Q
ENA CLR
Q
Q[2..0] ENA CLR
International Conference on Embedded Systems - (ICES 2014)
Timing and power analysis data (2nd type) For the 2nd type of machine after performing the classic timing analysis and powerplay power analysis the results obtained are as follows.
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for further improvement of this vending machine by including more products and can also go for some age based products for which user have to give standard age ID along with the money to the machine in order to buy those age restricted products from the vending machine such as some medicine, alcohol etc, so that it will not be utilized by some minor.
TABLE IV. TIMING AND POWER ANALYSIS DATA FOR 2ND TYPE OF VENDING MACHINE
REFERENCES
Timing constraints Type of delay Worst case setup time(tsu) Worst case clock to out (tco) Worst case hold (th) Clock period
Actual time 3.631ns 6.927ns -1.810ns 2.5 ns
Power constraints Type of delay Total Thermal power dissipation Core static thermal dissipation I/O thermal power dissipation
Actual time 424.41mW 396.93mW 27.49mW
All the simulation and synthesis performed on quartus altera software with the use of other EDA tools as follows: Design entry/synthesis: Leonardo Spectrum EDIF format Simulation Tool: ModelSim VHDL format Timing analysis: Classic timing analyzer Power analysis: Power play power analyzer tool TABLE V. COMPARING GATE FUNCTIONS USAGE OF STRATIX FAMILY OF FPGA ACCORDING TO THEIR FAN IN’S Logic instances used in 1st vending machine
Logic instances used in 2nd vending machine
7 input functions-
1
0
6 input functions-
1
6
5 input functions-
8
7
4 input functions-
8
1
7
7
25
21
