Comparison of Three-Phase PWM Rectifiers to Interface Ac Grids and ...

3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2012

Comparison of Three-Phase PWM Rectifiers to Interface Ac Grids and Bipolar Dc Active Distribution Networks Joabel Moia, Jackson Lago, Arnaldo J. Perin, and Marcelo L. Heldwein Federal University of Santa Catarina (UFSC) Power Electronics Institute (INEP) 88040-970 — PO box:5119 — Florian´opolis, SC, BRAZIL E-mail: joabel ; jacksonl ; arnaldo.perin ; heldwein @inep.ufsc.br

Abstract—Dc active distribution networks seem to be a technically viable solution where high transmission efficiency, power quality, reliability and distributed generation are required. Modern power conversion devices are to be employed in order to create such networks by connecting them to three-phase ac power systems. This work present the evaluation of twolevel and three-level (NPC) bidirectional voltage source rectifier topologies for bipolar dc active networks from the perspective of power semiconductor efforts, efficiency, volume and weight. The evaluation methodology based on the rotating reference frame is used in the analysis of a 160 kVA NPC converter feeding unbalanced dc loads and the impact of this in the converter volume and weight is presented. Furthermore, the maximum dcside load unbalance for the NPC rectifier is derived.

Keywords – Power Rectifier Topologies; Semiconductor Efforts; rotating reference frame analysis; . I. I NTRODUCTION Many aspects of dc distribution network technologies have been discussed [1], [2] and several implementations of these networks have been proposed [3]–[9]. However, studies comparing different power converter alternatives to guide the definition of network architectures still lack in the literature. Analyzes on possible dc network topologies show that high reliability and low transmission losses can be found employing a bipolar dc architecture [8]–[10]. Therefore, a bipolar dc distribution network is the focus of this work. On the other hand, it is not completely clarified how to choose the power converters in such a network in the sense that different converter topologies lead to different network characteristics and possibilities for optimization of certain features. For instance, multilevel rectifiers might be optimum for medium voltage dc applications and not for low cost/low voltage ones. Another example is how to generate the bipolar lines, where dc generators, simple and/or complex converters that provide basic or advanced operating features could be employed. Therefore, this work aims on the theoretical comparison of converter topologies to implement bipolar dc active distribution networks. The scope of the work is limited to the analysis of bidirectional PWM rectifiers, which seem suitable for high efficiency and reliable network operation based on

978-1-4673-2023-8/12/$31.00/ ©2012 IEEE

the widespread industrial deployment of such rectifiers. Fig. 1 shows a general bipolar dc distribution architecture derived from a three-phase grid through a bidirectional rectifier followed by a voltage balancer supplying a bipolar line composed of three conductors that feed energy to two lumped loads in parallel to power sources. The loads/sources might present unbalanced powers and, thus, voltage balancers [7], [11] and/or current redistributors [12] can be employed to balance the supply line currents and/or voltages, consequently reducing transmission losses. The bidirectional rectifier is required to provide reversible power flow due to possible surplus energy being generated by the distributed power sources. Different converter topologies are able to implement the three functional blocks (rectifier, balancer and redistributor) included in Fig. 1. However, just a few topologies are widely employed in high power systems due to proven reasonable efficiency, cost and reliability. This work considers only active (PWM) rectifier topologies. Two alternatives are evaluated for the bidirectional rectifier: (i) a three-phase two-level voltage source rectifier (VSR) (cf. Fig. 2(a)); and, (ii) a three-phase/level Neutral Point Clamped rectifier (NPC) [13], [14] (cf. Fig. 2(b)), since these two are among the most widespread three-phase converters employed in industry. References [7], [11] propose the use of two types of voltage balancers connected to the output of a VSR to create the bipolar dc lines. The current redistributor for balancing the bipolar network currents was introduced in [12]. Both, voltage balancer topologies and current redistributors were evaluated in [15]. Section II presents the methodology adopted for the computation of power semiconductor current efforts, which is exemplarily presented for the NPC rectifier feeding unbalanced loads in steady state. Based on the current efforts, the conduction losses in all power semiconductors are evaluated in Section III along with the derivation of expressions for the calculation of switching losses. This work presents (cf. Section III) the design of two 160 kVA NPC rectifiers considering two situations, namely: balanced dc loads and unbalanced loads. In Section IV is presented a bipolar network system architectures comparison. Finally, conclusions on the comparison of the designed converter systems are given.

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3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2012

+

NPC

0 _

or

VSR

+

+

_

_

0

Fig. 1. Considered bipolar dc distribution architecture including a three-phase bidirectional rectifier, a voltage balancer (VB), a current redistributor (CR), lumped loads and power sources (DG).

being transferred to the ac grid. Both these situations are analyzed. The following assumptions are made: Iˆ and Vˆ are, respectively, the peak values of purely sinusoidal currents and voltages at the ac-side; Ph = I¯gp V¯p0 Pl = I¯gn V¯0n

(1) (2)

are, respectively, the upper and lower line load plus distributed generation total powers; the modulation index M is defined as (3) M = 2Vˆ /VDC for both the VSR and the NPC converters; the total output power is (4) P o = Ph + Pl ; the unbalance power is defined as Pu = Ph − Pl ;

(5)

and, an unbalance ratio αp is defined with αp = Pu /Po .

(6)

For the sake of brevity, this work presents only the methodology employed to find the current efforts for the power semiconductors of the three-phase NPC rectifier. For the threephase two-level voltage source rectifier VSR the analysis is similar and can be extended. (c)

(d)

Fig. 2. Power converter topologies considered for the evaluation: (a) threephase two-level VSR; (b) three-phase NPC converter; (c) voltage balance converter (VB); (d) current redistributor converter (CR).

II. S EMICONDUCTORS C URRENT E FFORTS C OMPUTATION — M ETHODOLOGY AND R ESULTS In order to find the current efforts for the rectifier topologies, it is important to consider power unbalances at the loadside of the bipolar line. Since PWM bidirectional rectifiers are considered, another aspect that is considered here is that the ac-side currents should be balanced and nearly sinusoidal, leading to high power factor (cos(φ)), i.e. cos(φ) ∼ = +1 for power flow towards the loads and cos(φ) ∼ = −1 for energy

A. Current Efforts Derivation From Fig. 2(b) it follows that the NPC rectifier is described in actual variables as, d (7) L iabc = vabc − vs,abc + vN 0 , dt where iabc = [ia ib ic ]T ; vabc = [va vb vc ]T ; vs,abc = [vs,a vs,b vs,c ]T ; vN 0 = [vN 0 vN 0 vN 0 ]T (vN 0 is the voltage from the grid neutral N to the dc-link center point 0). Assuming grid voltages vx = Vˆ sin(ωt + θx ), with x = a, b, c; θa = 0; θb = −2π/3; θc = +2π/3; currents ix = Iˆ sin(ωt + θx + φ); and, steady state operation, this system can be modeled employing transform B, with

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⎡

cos (ωt + 2π/3) sin (ωt + 2π/3) ⎦ , 1/2 (8) so that all variables are transformed to a stationary frame dq0. Thus, d  −1  L B idq0 = B−1vdq0 − B−1vs,dq0 + vN 0 ⇒ dt ⎡ ⎡ ⎤ ⎤ 0 -1 0 0 d   L idq0 =vdq0 −vs,dq0 + ⎣ 0 ⎦+ωL⎣ 1 0 0 ⎦idq0 , (9) dt vN 0 0 0 0 B=

cos (ωt) 2⎣ sin (ωt) 3 1/2

cos (ωt − 2π/3) sin (ωt − 2π/3) 1/2

⎤

where vdq0 = [0 Vˆ 0]T ; idq0 = [id iq i0 ]T and vs,dq0 = VDC /2 · [sd sq s0 ]T , with sj (j = d, q, 0) being the switching functions of the converter transformed to the stationary frame. Employing the local average value definition to the switching functions, leads to vs,dq0 Ts = VDC /2 ·   T ˜ [Dd Dq D0 + d0 ] , where Dj are the duty-cycle functions (constant values during steady state) in the stationary frame and Ts is the switching period. The term d˜0 refers to a modulation function common to all three phases that is used in modulation schemes, such as Space Vector PWM and third harmonic injection. Furthermore, the derivative terms in (9) are null considering steady state operation. Thus, ωLiq Dd = −2  Vdc Vˆ ωLid + . Dq = 2 Vdc Vdc

value for is0 given by is0  Tg = −6D0 iq /π. The unbalance 3 power depends on the center point current and is given by Pu = −(Is0 VDC )/2. Rearranging all terms leads to D0 =

The duty-cycle function dS/D for each semiconductor in phase a can be defined and the mean current value for a given device is approximated with IS/D,avg =

Applying the local average value definition and the dq0 frame transformation to (12) gives the local average value of the neutral point current is0     T   is0  = − B−1 · ddq0  · B−1 · idq0 , (13) with ddq0 = [dd dq d0 ]T . Assuming unity power factor, i.e. id = 0 and iq = (2Po )/(3Vˆ ), and that the rectifier is supplied by three wires, i.e. i0 = 0, and computing the average value in a third of the mains period Tg leads to a constant local average

1 2π

2π

dS/D Iˆ sin (ωt) dωt,

(16)

0

where subscript S/D denotes a generic transistor S or diode D. Respectively, the RMS current values are given by IS/D,rms 2 =

(11)

is0 Ts = (ia + ib + ic ) − |da | ia − |db | ib − |dc | ic ⇒



=0     is0 Ts = − dabc  · iabc . (12)

(14)

and the actual duty-cycle functions are found with dabc = B−1 · [Dd Dq D0 ]T . This shows that the average value of the 0-component duty-cycle is responsible for the compensation of dc-side power unbalances. Back-transforming Dd , Dq e D0 leads to the actual dutycycles, namely: ⎧ ⎨ da = M [sin(ωt) + π4 αp + d˜0 ] (15) d = M [sin(ωt − 2π/3) + π4 αp + d˜0 ] . ⎩ b π ˜ dc = M [sin (ωt + 2π/3) + 4 αp + d0 ]

(10)

The term ωLiq is typically much smaller than VDC . Thus, Dd ∼ = 0. Assuming close to unity power factor, then id = 0 and, consequently, Dq = M . Defining dxk (x = a, b, c and k = p, n, 0) as the duty-cycles for the equivalent switches connecting terminals x and k, dabc = [da db dc ]T and inspecting Fig.⎡ 2 it follows ⎤ that, ⎡ ⎤ isp Ts dap dbp dcp ⎣ isn T ⎦ = ⎣ dan dbn dcn ⎦ · iabc ⇒ s da0 db0 dc0 is0 Ts

πPu Vˆ παp M , = 2Po VDC 4

1 2π

2π

2  dS/D Iˆ sin (ωt) dωt.

(17)

0

For the sake of brevity, only two duty-cycle functions are defined in the following,   d (t) → ∀ (0 ≤ ωt ≤ π) , (18) dDS1,a (ωt) =  a 0 → ∀ (π ≤ ωt ≤ 2π)   1 − da (t) → ∀ (0 ≤ ωt ≤ π) . (19) dS3,a (ωt) =  0 → ∀ (π ≤ ωt ≤ 2π) Integrating (16) and (17) leads to the current efforts expressions for the power sourcing and sinking rectifier operation modes. Two carrier based modulation strategies are considered, namely the Sinusoidal PWM (SPWM) and the high modulation index (M > 1/2) Centered Space Vector Modulation (here named SVM for its equivalence to the conventional Space Vector Modulation). For high modulation indexes, the Centered Space Vector Modulation [16] is equivalent to the injection of properly computed triplen harmonics [17] in duty-cycle d˜0 . This modulation strategy reduces the harmonic distortion of the ac voltages along with the ac current ripple. Furthermore, higher modulation indexes are achievable. The zero axis duty-cycle variation d˜0SVM in the SVM modulation is defined with max(da , db , dc ) + min(da , db , dc ) , (20) d˜0SVM = − 2 which leads to a composition of sinusoids that changes at each sextant (π/3 rad).

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3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2012

TABLE I C URRENT AND VOLTAGE EFFORTS FOR THE POWER SEMICONDUCTORS OF BOTH RECTIFIERS , WHERE γ =

3 16π 2

−

1 96

∼ = 8.581 · 10−3 .

Fig. 3. RMS currents for the most demanded power semiconductors of both rectifiers: (a) NPC — DS2 ; (b) NPC — S2 ; (c) VSR — S1 ; (d) VSR — DS1 . Operating condition: Power factor cos(φ) = +1.

B. Maximum Allowable Dc-Side Unbalance for NPC Rectifier The NPC rectifier is able to generate ac-side voltages with perfectly sinusoidal local average values if the maximum dutycycles are limited to unity. This requirement guarantees that the converter operates in its linear range. Thus, considering balanced ac grid voltages, to achieve sinusoidal and balanced ˆ max for the phase dutyac currents, the maximum peak value D

cycles are         ˆ  ˆ  ˆ  ˆ  Da,max  = D b,max  = Dc,max  = Dmax  = 1

224

Reference [16] shows that  ˆ = km D 2 + D 2 + D 0 , D q d

(21)

(22)

3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2012

where km is the maximum effective modulation index. It was considered that Dd ≈ 0. Thus, |D0,max | = 1 − km |Dq |

(23)

From (14),

π αp,max M. (24) 4 Plugging (24) into (23) it follows that π (25) (1 − km M ) = |αp,max |M, 4 and the maximum power unbalance factor αp,max for the NPC converter linear range operation is   4 1 − km . (26) |αp,max | = π M D0,max =

SPWM = 1 for the SPWM Modulation According√to [16], km SVM = 3/2 with the SVM Modulation. and km Based on this static model for the NPC and a similar methodology for the VSR, the current efforts for the power semiconductor of both topologies are derived and the results are shown in Table I, where the VSR requires an additional dc-dc converter that generates the bipolar dc bus, i.e., a voltage balancer. Table I considers the two aforementioned types of modulation being employed for each of the rectifiers, namely: naturally sampled centered space vector modulation (SVM) with M > 1/2 and naturally sampled sinusoidal PWM (SPWM). Fig. 3 shows the rms values of the currents at the two most demanded semiconductors for each rectifier as a function of the ac peak current value. The presented equations have been tested against simulation results of the rectifiers, providing errors lower than 1% for a rectifier switching frequency (NPC and VSR) fsr = 4 kHz.

III. S EMICONDUCTORS L OSSES AND R ECTIFIER D ESIGN In order to design cooling systems and choose appropriate semiconductors it is necessary to evaluate the power losses in each device. This section shows the losses calculation procedure for a switched rectifier with the following specifications: ac grid rms line voltage value Vac,rms = 380 V; modulation index M = 0.816; ac grid frequency fg = 50 Hz; rated rectifier power Po = 160 kVA; ambient temperature Ta = 50◦ C; maximum junction temperature Tj,max = 125◦ C fsr = 4 kHz and the dc-dc converters (CR and VB) switching frequency fsc = 1.25 kHz. The conduction losses for each power semiconductor device under steady state operation is computed with PS/D,con

1 = 2π

temperature. A second order polynomial dependent on the instantaneous device currents for the forward conduction characterization was found to be a more precise model to derive the semiconductor losses for the case at hand, where high power IGBTs and PIN diodes were used. The switching energies are obtained from switching loss test data contained in the power modules data sheet and are mathematically expressed as second order polynomials for the turn-on eon , turn-off eof f and diodes reverse recovery err

TABLE II C OEFFICIENTS OF THE POLYNOMIAL FUNCTIONS EMPLOYED IN THE CALCULATION OF THE NPC CONVERTER SEMICONDUCTOR LOSSES . W ITH (j = 1..4) AND (i = 1..2). A LL SEMICONDUCTORS OF THE NPC CONVERTER USE THE F3L300R07PE4 I NFINEON NPC POWER MODULE .

Coefficient Unit kS/D,0 [V] [Ω] kS/D,1 kS/D,2 [Ω/A] [J] kon,0 [Wb] kon,1 [Ω·s] kon,2 [J] kof f,0 kof f,1 [Wb] kof f,2 [Ω·s] [J] krr,0 [Wb] krr,1 [Ω·s] krr,2

(27)

0

where vS/D,on = kS/D,2 · iS/D 2 + kS/D,1 · iS/D + kS/D,0

DSj .655e-0 0.445e-2 -0.510e-5 0 0 0 0 0 0 0.138e-2 0.206e-4 -1.712e-8

Di .655e-0 0.445e-2 -0.510e-5 0 0 0 0 0 0 0.138e-2 0.206e-4 -1.712e-8

TABLE III C OEFFICIENTS OF THE POLYNOMIAL FUNCTIONS EMPLOYED IN THE CALCULATION OF THE TWO - LEVEL VSR SEMICONDUCTOR LOSSES . W ITH (j = 1..2). A LL SEMICONDUCTORS OF THE VSR, VB AND CR CONVERTER USE THE DEVICES INCLUDED IN THE FF300R12ME4 I NFINEON POWER MODULE .

2π iS/D · vS/D,on dωt

Sj .644e-0 0.345e-2 0 0.372e-3 0.591e-5 -1.727e-9 0.421e-2 0.217e-4 8.303e-8 0 0 0

(28)

is the instantaneous forward conduction voltage drop curve fitted polynomial based on datasheet information for different current values at the considered operating junction

225

Coefficient kS/D,0 kS/D,1 kS/D,2 kon,0 kon,1 kon,2 kof f,0 kof f,1 kof f,2 krr,0 krr,1 krr,2

Unit [V] [Ω] [Ω/A] [J] [Wb] [Ω·s] [J] [Wb] [Ω·s] [J] [Wb] [Ω·s]

Sj 0.594e-0 0.608e-2 -0.420e-5 0.292e-2 0.426e-4 1.946e-8 0.229e-2 0.127e-3 -2.898e-8 0 0 0

DSj 0.620e-0 0.482e-2 -0.426e-5 00 0 0 0 0 0 0.650e-2 0.114e-3 -1.146e-7

3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2012

related switching intervals. Thus,   2  eon = kon,2 · iS/D  + kon,1 · iS/D  + kon,0   2  eof f = kof f,2 · iS/D  + kof f,1 · iS/D  + kof f,0   2  err = krr,2 · iS/D  + krr,1 · iS/D  + krr,0 .

(29) (30) (31)

The switching losses for a complete period are approximated with 2π fs [eon + eof f + err ] dωt. (32) Psw = 2π 0

Based on the computed current efforts and maximum device voltages, three Infineon NPC power modules F3L300R07PE4 are chosen to implement the three-level NPC rectifier. Using the according data sheet information the coefficients for the losses polynomial expressions for the NPC converter are listed in Table II. The coefficients for the semiconductors considered for the VSR, VB and CR converters are listed in Table III based on the FF300R12ME4 Infineon power module data sheet. Applying the adopted losses calculation methodology and the rectifier specifications to the chosen power modules semiconductors leads to the losses presented in Fig. 4 for some of the semiconductors and in Fig. 5 summing the losses in all semiconductors. Minimum losses are obtained for the balanced load condition. Computed efficiencies ranging from η ∼ = 0.9880 for maximum unbalance (αp = ±0.29) up to η∼ = 0.9884 for αp = ±0 are observed for the NPC employing (a)

150

SPWM and working as unity power factor rectifier mode. For NPC employing SVM modulation and working as unity power factor, the calculated efficiencies is η ∼ = 0.9878 for maximum unbalance (αp = ±0.46) up to η ∼ = 0.9886 for αp = ±0. The 2-level VSR switching at 4 kHz achieves an efficiency around η ∼ = 0.9901 under SPWM and η ∼ = 0.9902 under SVM. However, if the converter dimensions are important, the VSR would be switched at a higher frequency in order to keep the ac-side inductors (boost inductors) with reduced dimensions. Therefore, a second efficiency evaluation was carried out for fsr = 8 kHz. This led to η ∼ = 0.9854 under SPWM and η∼ = 0.9855 under SVM. The NPC converter operating as unity power factor rectifier system employing the SPWM is designed as shown in Fig. 6, where Fig. 6(a) shows a system where unbalance is not present, i.e. this rectifier is to be employed with a voltage balancer. Fig. 6(b) shows the system designed for maximum load unbalance (αp = ±0.29). The boxed volume increases approximately 7%, while the total heatsink weight increases 77.5%. This clearly shows the impact of the bipolar dc bus power unbalances in the design of bidirectional rectifier systems. A bidirectional rectifier configuration that uses a 2level VSR connected to a dc voltage balancer is impacted in a similar way. This comparison suggests that a current balancer applied close to the loads in a bipolar dc distribution network reduces the requirements for an NPC rectifier. Added to the reduced current efforts and total losses the balancing of the bipolar dc bus currents reduces the losses in the feeders [12]. These two characteristics are explored in the next section, where the dc-dc converters (VB and CR) losses are added to the rectifier losses in different system architectures.

Plosses [W]

DS2 100

IV. B IPOLAR N ETWORK S YSTEM A RCHITECTURES C OMPARISON

S2

The previous section has shown that all rectifier configurations show conversion efficiency improvements when modulated with Space Vector Modulation. Thus, only SVM is considered in the following.

50

D1 0 -0.3

-0.2

-0.1

0

0.1

αp

0.3

0.2

2400

(b)

150

S2

Plosses [W]

Plosses [W]

2200

100

50

VSR SVM(8kHz)

VSR SPWM(8kHz)

DS2

NPCSPWM (4kHz)

2000

NPCSVM (4kHz)

1800

D1

VSR SVM(4kHz)

VSR SPWM(4kHz) 1600

0

-0.5

-0.4

-0.2

0

αp

0.2

0.4

0.5

Fig. 4. Devices Losses for the NPC rectifier with: (a) SPWM Modulation; (b) SVM Modulation. fs=4kHz para ambos

-0.5

-0.4

-0.2

0

αp

0.2

0.4

0.5

Fig. 5. Total losses for NPC converter and VSR converter with SPWM Modulation and SVM modulation.

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Bus Capacitor Bank (40 x 1000uF/450V B43740-Epcos)

as a function of the cable length are shown in Fig. 8. The configuration with the NPC plus CR is advantageous for cable lengths: • lw ∼ = 12 m with power unbalance αp = 1.0 and fs,VSR = 4 kHz; • lw ∼ = 32 m with power unbalance αp = 0.5 and fs,VSR = 4 kHz; • lw ∼ = 100 m with power unbalance αp = 0.27 and fs,VSR = 4 kHz; • any with fs,VSR = 8 kHz.

Power Drives PCB

Fan (3 x SKF 16B/230 Semikron)

(a)

Thus, the decision for a given bipolar dc distribution network converters architecture must consider several parameters even when observing only overall system efficiency. Important

Heatsink (3 x P16/170 - Semikron)

Bus Capacitor Bank (44 x 1000uF/450V B43740-Epcos)

(a)

4000

Plosses [W]

l w =100m

Power Drives PCB

Fan (3 x SKF 16B/230 Semikron)

(b)

Heatsink (3 x PX16/200 - Semikron)

0

0.25

0.50 αp

0.75

1.00

(b)

Plosses [W]

l w =100m 6000

l w =50m 4000

2000

This section makes a comparison for the following bipolar network system configurations:

1000

cfg-1: NPC under SVM and a CR close to the loads; cfg-2: 2-level VSR under SVM connected to a VB.

l w =20m

l w =10m 0

0.25

0.50 αp

0.75

1.00

(c)

8000

The losses data for the dc-dc converters were presented in [15], where the dc-dc converters are compared and the bipolar dc feeder characteristics are explained. This includes the cable parameters, network length and the semiconductors of the dcdc converters. The total dc load power is assumed as Po = 152 kVA. Fig. 7 shows the total system losses as a function of the power unbalance αp for different cable lengths. The NPC plus CR configuration presents reduced losses for high power unbalances and long cable lengths even when compared to the VSR switching at fsr = 4 kHz. If the 2-level VSR is switched at fsr = 8 kHz, losses are higher even at null power unbalance and 10 m cable. Therefore, the maximum converter dimensions must be considered when deciding for a system architecture and strongly influence the overall system losses. The overall system losses for the considered configurations

l w =100m

Plosses [W]

•

l w =20m

l w =10m

8000

Fig. 6. NPC rectifier comparison for SPWM Modulation: (a) Balanced NPC Converter presents a boxed volume Volbox = 0.0877 m3 and the total heatsink weight WHS ∼ = 12.0 kg; and, (b) Unbalanced NPC Converter (αp,max = 0.29) with a boxed volume Volbox = 0.0936 m3 and the total heatsink weight WHS ∼ = 21.3 kg.

•

2000

1000

Total Volume: (a) = 0.0877 m,3 (b) = 0.0936 m3

l w =50m

3000

6000

l w =50m

4000

1000

l w =20m

l w =10m

2000 0

0.25

0.50 αp

0.75

1.00

Fig. 7. Overall systems losses for the following configurations: (a) NPC converter with SVM modulation plus Current Redistributor (CR) for fsr = 4 kHz and fsc = 1.25 kHz; (b) VSR converter with SVM Modulation plus Voltage Balance (VB) for fsr = 4 kHz and fsc = 1.25 kHz; (c) VSR converter with SVM Modulation plus Voltage Balance (VB) for fsr = 8 kHz and fsc = 1.25 kHz.

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3rd IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG) 2012

(a)

6000

Plosses [W]

5000

cfg-2(αp=1.0)

4000 cfg-1(αp=0.5)

ACKNOWLEDGEMENT

cfg-1(αp=1.0)

The authors would like to gratefully acknowledge the National Council for Scientific and Technological Development — CNPq (under grant 479982/2010-4) for the financial support to this research effort.

cfg-2(αp=0.5)

3000 cfg-1(αp=0.27)

2000 1000

R EFERENCES

cfg-2(αp=0.27)

0

25

50 lw

75

cfg-2(αp=0.5)

cfg-2(αp=1.0)

5000

100

(b)

6000

Plosses [W]

networks regarding system features, control strategies and the design of the converters.

cfg-1(αp=1.0)

4000 3000 2000 1000

cfg-1(αp=0.27)

0

25

cfg-1(αp=0.5)

50

lw

cfg-2(αp=0.27)

75

100

Fig. 8. Overall system losses considering the length of the bipolar feeder cables, where: (a) fs,NPC = 4 kHz and fs,VSR = 4 kHz; (b) fs,NPC = 4 kHz and fs,VSR = 8 kHz.

specifications are the expected power unbalance at the load end of the network; the length of the power cables; the maximum dimensions of the power converters; the modulation scheme that drives the rectifiers. V. CONCLUSIONS The static modeling of an NPC rectifier has been presented in order to evaluate power semiconductor demands when its dc output is subject to power unbalances. This methodology has been applied to both NPC and VSR operating with two types of modulation (SVM and SPWM). Rectifier system designs were presented and compared. It was shown that the design of NPC rectifier subject to dc side power unbalances leads to larger, less efficient and much heavier rectifiers. Finally, two bipolar dc distribution network converters architectures based on the analyzed rectifiers were compared regarding their overall losses with respect to several system parameters. It was shown that relevant system specifications are the expected power unbalance at the load end of the network; the length of the power cables; the maximum dimensions of the power converters; the modulation scheme that drives the rectifiers. Future works will include more types of architectures and analyze the

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