Complementary inverter from patterned source electrode vertical organic field effect transistors Michael Greenman, Svetlana Yoffis, and Nir Tessler Citation: Applied Physics Letters 108, 043301 (2016); doi: 10.1063/1.4940999 View online: http://dx.doi.org/10.1063/1.4940999 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/108/4?ver=pdfcov Published by the AIP Publishing Articles you may be interested in High performance unipolar inverters by utilizing organic field-effect transistors with ultraviolet/ozone treated polystyrene dielectric Appl. Phys. Lett. 105, 093302 (2014); 10.1063/1.4895121 The application of orthogonal photolithography to micro-scale organic field effect transistors and complementary inverters on flexible substrate Appl. Phys. Lett. 104, 053301 (2014); 10.1063/1.4863678 Ambipolar copper phthalocyanine heterojunction field effect transistors based organic inverter AIP Conf. Proc. 1512, 466 (2013); 10.1063/1.4791113 Ambipolar organic field effect transistors and inverters with the natural material Tyrian Purple AIP Advances 1, 042132 (2011); 10.1063/1.3660358 Selectively patterned highly conductive poly(3,4-ethylenedioxythiophene)-tosylate electrodes for high performance organic field-effect transistors Appl. Phys. Lett. 95, 233509 (2009); 10.1063/1.3273862
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 52.2.249.46 On: Fri, 29 Jan 2016 13:04:18
APPLIED PHYSICS LETTERS 108, 043301 (2016)
Complementary inverter from patterned source electrode vertical organic field effect transistors Michael Greenman, Svetlana Yoffis, and Nir Tesslera) Sara and Moshe Zisapel Nano-Electronic Center, Department of Electrical Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel
(Received 30 October 2015; accepted 18 January 2016; published online 28 January 2016) We report N-type and P-type high performance vertical organic field effect transistors. Insulation layer on top of the source electrode is used to reduce off currents leading to on/off ratio above 105 with on current density higher than 10 mA/cm2. A complementary inverter circuit was assembled from the transistors; examination of the inverter output characteristic indicates that the inverter C 2016 AIP Publishing LLC. gain is strong enough to be cascaded. V [http://dx.doi.org/10.1063/1.4940999]
Integrating organic semiconductors (OSCs) in thin film transistor (TFT) technology can lead to low-cost, flexible, and large-area electronics.1,2 Yet, the native low mobility of amorphous OSCs, compared with the inorganic crystalline semiconductors, limits the organic TFT performance and hinders its usage in commercial applications. In order to overcome the low mobility, recently, many new designs for organic transistor were developed.3–7 Those new designs minimize the path that the charge carriers drifts through the OSC, in order to achieve high current densities and high operational frequency while allowing the use of OSCs exhibiting low mobility values6 even down to 103cm2 V1 s1.8 One design approach is that of stacking the different layers on top of each other so the charge carriers’ path is determined by the OSC’s thickness. Those devices are normally called vertical organic field effect transistors (VOFETs).9–11 Achieving field effect while using stacking design is not trivial because a continuous layer of metal, such as the source electrode, will mask any electric field emanating from the gate. Our approach to deal with that problem is by using a patterned source (PS) electrode,12–14 an illustration of the device is shown in Figure 1(a). In the previous works, using block copolymer lithography,15 we presented low voltage PS-VOFETs16 as well as a turn-on time lower than 2 ls.8 Numerical models of the device proved our assumption that the origin of the on current is from the side walls of the holes.17 The surface of this side wall is strongly affected by the gate electric field that lowers the injection barrier between the source electrode and the OSC thus inducing the on current. The off current is generated, mainly, from the top part of the source electrode and is affected by the drain-source bias (see Figure 1(b)). In this work, we report high performance N-type and P-type PSVOFETs that are connected to form an inverter circuit. These devices were produced using a photolithography based fabrication process that included an insulating layer on top of the source electrode to reduce off currents.14,17 The devices were fabricated on top of a highly doped 4 in. silicon wafer having 100 nm thermal oxide. The doped a)
Author to whom correspondence should be addressed. Electronic mail:
[email protected]
0003-6951/2016/108(4)/043301/4/$30.00
silicon and silicon oxide layers were used as the gate electrode and gate dielectric, respectively. The fabrication process starts with creating the patterned source electrode which was fabricated using the lift-off process. The lift-off mask of the inverse hole arrays image was patterned in a photoresist using MA-6 contact mask aligner (SUSS). A 30 nm gold layer was evaporated and used as the source electrode. To enhance the adhesion, very thin layers of titanium and aluminum were evaporated below and above the gold layer, respectively. The electrode was then covered with 80 nm silicon oxide grown by plasma enhanced chemical vapor deposition (PECVD) (Plasma-Therm 790). After the photoresist removal, the fabrication of 1 mm 1 mm arrays of holes in the source electrode was completed. The wafer was cut into dies, each contained arrays with several different holes sizes (2, 5, 10, and 20 lm holes diameter) but with the same fill factor of 20%. In this context, the fill factor is the ratio between the sum of hole areas to the whole device area. The samples were cleaned by washing and sonication in acetone, methanol, and 2-propanol. Organic semiconductor layer was thermally evaporated, 300 nm of N,N0 -Dioctyl-3,4,9,10 Perylenedicarboximide (PTCDI-C8 98% Sigma) for the N-type devices and 360 nm of N,N0 -Di(1-naphthyl)-N,N0 -diphenyl-(1,10 -biphenyl)-4,40 -diamine (NPD 99% Sigma) for P-type. Different types also differ in their drain electrode; the N-type devices were completed using aluminum drain electrode and the P-type using gold drain electrode. The resulting devices are presented in Figure 1(c). Between the different fabrications steps, the samples were kept in ambient conditions. The electrical measurements were carried out using a Semiconductor Parameter Analyzer (Agilent 4155B) and inside a glove box in order to extended device life time. Although silicon is not a flexible substrate, all the fabrication steps were low temperature ones making them plastic substrate compatible. If used for active matrix display, an organic light emitting diode (OLED) can be fabricated instead of or directly on top of the drain electrode and lead to very high fill factor in the pixel.10 To examine the importance of adding an insulating layer on top of the source electrode, we compare a transistor having this layer (Figure 2(a)) with the one that does not (Figure 2(b)). The transfer characteristics of the two PTCDI based
108, 043301-1
C 2016 AIP Publishing LLC V
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 52.2.249.46 On: Fri, 29 Jan 2016 13:04:18
043301-2
Greenman, Yoffis, and Tessler
Appl. Phys. Lett. 108, 043301 (2016)
FIG. 3. Output characteristic of N-type VOFET having insulating layer on top of its source electrode.
FIG. 1. (a) 3D illustration of VOFET. (b) A cross-section illustration of VOFET; the arrows represent the on and off currents flow. (c) Optical photos of the samples, in the top row, 2 dies each contain 8 VOFETs. The left is P-type VOFET with NPD and the right is N-type with PTCDI-C8. In the bottom row, at the left enlarge photo of one transistor. On the right, enlarged photo of the patterned area.
VOFETs, shown in Figures 2(a) and 2(b), exhibit a clear N-type transistor like behavior. We note that the presence of the insulator on top of the source electrode (in Figure 2(a)) suppresses the injection from the top part of the electrode and thus significantly reduces the off current. Hence, the on/ off ratio in Figure 2(a) is much higher compared with that in Figure 2(b), which was measured for the VOFET without the insulating layer. The on/off ratio exceeds 105 for gate and
drain bias of 30 V for the VOFET with insulating layer and is 100 times higher than without the insulating layer. The major difference between the devices is the off current. The PECVD silicon oxide layer reduces the off currents by 3 orders of magnitude, supporting the assumption that the off currents were mainly generated at the top part of the electrode. A second source of leakage, which is not directly related to the transistor structure, has to do with the large overlap between the substrate which functions as a gate electrode and the other electrodes. The thermal SiO2 is not an ideal insulator and despite it being specified as better on 4 in. wafers it is still prone to leakage. To make the leakage lower and allow for even lower source-to-drain off currents, one needs to introduce a fabrication process using patterned gate electrode. The third source for apparent leakage is the capacitive charging of the organic semiconductor in regions outside the transistor area. As the sign of this leakage current depends on the sweep direction, the voltage at which the total gate current crosses zero is different between the forward and reverse sweep directions. This capacitive charging would also be rectified once a patterned gate process is implemented. The current density of VOFET with insulating layer is 10 times lower than without it, still the VOFET reaches current density over 10 mA/cm2, high enough to
FIG. 2. Transfer characteristics of (a) N-type VOFET with silicon oxide as insulating layer, the solid lines are for increasing gate voltage and the dashed lines are for retrace. (b) N-type VOFET without insulating layer. The inset shows transfer characteristics for N-type VOFETs differing only in holes size diameter with the fill factor of the hole remaining at 20% (VDS ¼ 30 V).
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 52.2.249.46 On: Fri, 29 Jan 2016 13:04:18
043301-3
Greenman, Yoffis, and Tessler
Appl. Phys. Lett. 108, 043301 (2016)
FIG. 4. (a) Transfer characteristics of P-type VOFET with insulating layer, solid lines for decreasing gate-source voltage and dash line for the increase. (b) Energy level diagram for N-type VOFET; the arrow indicates injection barrier for electrons. (c) Energy level diagram for P-type VOFET; the arrow indicates injection barrier for holes.
drive an OLED at brightness level needed for displays.1 The fabrication process is fairly stable; transistors from different dies with different holes sizes show similar performance (inset to Figure 2(b)). The output characteristics of a VOFET having a source insulator layer are shown in Figure 3. Note that for zero or negative gate bias the characteristics are of a rectifying diode with a rectification ratio of up to 103. Also, the off current measured for positive drain-source voltage is almost biasindependent. Both features are an indication of the injection blocking performed by the insulating layer covering the source electrode. In the reverse bias, the currents are essentially high due to the good injection properties of the top aluminum electrode. The strong modulation by the gate bias at the positive drain-source voltage supports the notion of the lowering of the injection barrier and the fact that the currentvoltage becomes symmetric at high gate bias suggests that the source electrode switched to being ohmic. The weak modulation at negative drain-source voltages can be explained by the large diameter of the holes (10 lm) compared with the small thickness of the OSC layer (300 nm). The large opening at the source electrode enables the electric field from the gate to reach the top aluminum electrode and OSC interface and enhance the field driving the electrons towards the source electrode. Having established the properties of the N-type VOFET, we present in Figure 4 the characteristics of a P-type VOFET. The transfer characteristics of 5 lm holes size NPD based VOFET (Figure 4(a)) show a transistor behavior for the P-type device with on/off ratio above 3 104. The maximum current density is also lower compared with the N-type device (1.7 mA/cm2). However, when matching the absolute drain-source voltages between the devices, the difference becomes more obscure. Drain source current density of 0.95 mA/cm2 for the N-type compared with 0.56 mA/cm2 for the P-type at 15 V drain-source voltage. The off currents in the P-type device are much greater than in the N-type device leading to lower on/off ratio and lower drain source operation voltage. The origin of the high off currents is attributed to the lower injection barrier17 for holes in the P-type device compared with the injection barrier for electrons in the N-type device. In the energy level diagram, based on the literature values,18,19 for the N-type device (Figure 4(b)), there
is 0.8 eV injection barrier, 0.4 eV higher than the barrier for holes in the P-type device (Figure 4(c)). The last property of the single VOFET we discuss is that of the hysteresis. In both types, a hysteresis phenomenon can be noticed as the difference between the solid and the dashed lines in Figures 2(a), 2(b), and 4(a). We have not resolved the mechanism underlying this hysteresis but judging by the OFET literature these are likely to be due to surface states at the insulator interface.20 Finally, the inverter circuit was assembled as shown in the inset to Figure 5. The P-type VOFET was connected through its source electrode to the positive supply voltage (VDD) and by drain electrode to the output terminal. The N-type VOFET was also connected by drain electrode to the output terminal and by source to the ground. Both gates were connected to the input signal. The voltage transfer curves of the inverter for different supply voltages (VDD) are presented in Figure 5; the curves reveal a truly inverter behavior with gains of 1.5–2. Further analysis of the curves suggests that although the gain is relatively low the inverter can still be cascaded. Using the conventional definition of VOH ¼ VOUT(VIN ¼ VOL), VOL ¼ VOUT(VIN ¼ VOH), VM ¼ VOUT(VIN ¼ VM), the result voltages for VDD ¼ 25 V are
FIG. 5. Output characteristics of the inverter circuit for different supply voltages. The electric scheme of the inverter circuit is presented in the right side of the figure.
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 52.2.249.46 On: Fri, 29 Jan 2016 13:04:18
043301-4
Greenman, Yoffis, and Tessler
VOH ¼ 21.4 V, VOL ¼ 6.6 V, VM ¼ 15.2 V and thus noise robustness (Min(VOH-VM, VM-VOL)) of 6.2 V. The high output voltage is kept about 3 V below VDD for all the curves meaning that the off current in the N type VOFET is not increasing with the increase in VDD. The low output voltage and the closing of the inverter are somewhat poorer and is due to the P-type VOFET not being fully closed at high drain-source voltage. In summary, we presented a fabrication process for PSVOFET with source insulating layer to reduce off current and improve performance. The device turn on mechanism is based on lowering of the injection barrier between the source and the OSC by the gate field. N-type and P-type PSVOFETs were demonstrated and when connected together an inverter circuit was achieved. This research was supported by the U.S.-Israel Binational Science Foundation (BSF, 2014396) and the Russell Berrie Nanotechnology Institute at the Technion–Israel Institute of Technology. Some of the fabrication steps were performed at the Micro-Nano Fabrication Unit (MNFU) at Technion. 1
H. Sirringhaus, Adv. Mater. 26, 1319 (2014). R. A. Street, Adv. Mater. 21, 2007 (2009). 3 A. Fischer, R. Scholz, K. Leo, and B. Lu€ ussem, Appl. Phys. Lett. 101, 213303 (2012). 2
Appl. Phys. Lett. 108, 043301 (2016) 4
K. Kudo, H. Yamauchi, and M. Sakai, Jpn. J. Appl. Phys. 51, 2 (2012). K. Nakayama, W. Ou-Yang, M. Uno, I. Osaka, K. Takimiya, and J. Takeya, Org. Electron. 14, 2908 (2013). 6 L. Bj€ orn, G. Alrun, F. Axel, K. Daniel, and L. Karl, J. Phys: Condens. Matter 27, 443003 (2015). 7 A. J. Ben-Sasson, M. Greenman, Y. Roichman, and N. Tessler, Israel J. Chem. 54, 568 (2014). 8 M. Greenman, A. J. Ben-Sasson, Z. Chen, A. Facchetti, and N. Tessler, Appl. Phys. Lett. 103, 073502 (2013). 9 L. Ma and Y. Yang, Appl. Phys. Lett. 85, 5084 (2004). 10 M. A. McCarthy, B. Liu, E. P. Donoghue, I. Kravchenko, D. Y. Kim, F. So, and A. G. Rinzler, Science 332, 570 (2011). 11 H. Hlaing, C.-H. Kim, F. Carta, C.-Y. Nam, R. A. Barton, N. Petrone, J. Hone, and I. Kymissis, Nano Lett. 15, 69 (2015). 12 A. J. Ben-Sasson and N. Tessler, Nano Lett. 12, 4729 (2012). 13 C.-M. Keum, I.-H. Lee, S.-H. S.-D. Lee, G. J. Lee, M.-H. Kim, and S.-H. S.-D. Lee, Opt. Express 22, 14750 (2014). 14 H. Kleemann, A. A. G€ unther, K. Leo, and B. L€ ussem, Small 9, 3670 (2013). 15 A. J. Ben-Sasson, E. Avnon, E. Ploshnik, O. Globerman, R. Shenhar, G. L. Frey, and N. Tessler, Appl. Phys. Lett. 95, 213301 (2009). 16 A. J. Ben-Sasson, G. Ankonina, M. Greenman, M. T. Grimes, and N. Tessler, ACS Appl. Mater. Interfaces 5, 2462 (2013). 17 A. J. Ben-Sasson and N. Tessler, J. Appl. Phys. 110, 044501 (2011). 18 N. Hiroshiba, R. Hayakawa, T. Chikyow, Y. Yamashita, H. Yoshikawa, K. Kobayashi, K. Morimoto, K. Matsuishi, and Y. Wakayama, Phys. Chem. Chem. Phys. 13, 6280 (2011). 19 W. X. Li, J. Hagen, R. Jones, J. Heikenfeld, and A. J. Steckl, Solid State Electron. 51, 500 (2007). 20 S. G. J. Mathijssen, M. Kemerink, A. Sharma, M. C€ olle, P. A. Bobbert, R. A. J. Janssen, and D. M. de Leeuw, Adv. Mater. 20, 975 (2008). 5
This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 52.2.249.46 On: Fri, 29 Jan 2016 13:04:18
