Computational Methods and High Speed Imaging

Keynote Presentation Computational Methods and High Speed Imaging Methodologies for Transient-Shock Reliability of Electronics Pradeep Lall Auburn University Department of Mechanical Engineering and Center for Advanced Vehicle Electronics Auburn, AL 36849, USA Tele: (334) 844-3424 E-mail:la:ll(i,ena.auburnxdu Abstract Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the stateof-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. In this paper, the modeling approaches and high-speed experimental techniques for first-level solder interconnects in shock and drop of electronics assemblies have been discussed. The shock and vibration reliability prediction of electronic interconnects involves multiple scales from macro-scale transient-dynamics of electronic assembly to micro-structural damage history of interconnects. Previous modeling approaches include, solid-to-solid sub-modeling using a half test PCB board, shell-to-solid sub-modeling technique using a quartersymmetry model. Inclusion of model symmetry in stateof-art models saves computational time, but targets primarily symmetric mode shapes. Explicit modeling approaches has been presented, which enable prediction of both symmetric and anti-symmetric modes, which may dominate an actual drop-event. Approaches presented include, smeared property models, Timoshenko-beam element models, explicit sub-models, and continuum-shell models. A failure-envelope approach based on wavelet transforms and damage proxies has been discussed to model drop and shock survivability of electronic packaging. Data on damage progression under transientshock and vibration in both 95.5Sn4.OAgO.5Cu and 63Sn37Pb ball-grid arrays has been presented. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confidence level. Transient dynamic behavior of the board assemblies in free and JEDEC-drop has been measured using highspeed strain and displacement measurements. Correlation of model predictions with dynamic measurements has been presented for acceleration, strain and resistance

using high-speed data acquisition systems capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video at 150,000 fps per second has been used to capture the deformation kinematics. Life Prediction have been correlated with experimental data for both leaded and leadfree ball-grid arrays. 1. Introduction Emerging trends of portable computing and communication applications towards smaller, lighter, form-factors has driven the need for robust-designs under overlapping environments of shock and vibration. Electronic products may be subjected to drop and shock due to mishandling during transportation or during normal usage. Test methods for drop reliability can be broadly classified into board-level and product-level tests, under constrained and unconstrained or free drop. Examples of board-level constrained drop include the JEDEC test method. The JEDEC test standard [2003] is often used to evaluate and compare the drop performance of surface mount electronic components for handheld electronic product applications. Correlation of the board-level tests to product-level performance is often challenging. Product-level failures are often influenced by housing design, in addition to drop-orientation, which may not always be perpendicular to the board surface [Lim 2002]. Factors such as drop height, mass of the product, impact orientation and the properties of the impacting surface affect the forces and the accelerations that are experienced by the product during impact. Design changes encompass an iterative process for improving the impact resistance of the electronic product. Use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Previous researchers have investigated the effect of board design and packaging technology [Saha 2004, Chai 2005], solder alloy composition, intermetallic growth [Chiu 2004, Lall 2005], surface finishes [Chong 2005] on solder joint reliability. Supplementary restraint mechanisms investigated include the use of cornerbonded underfills [Lall 2004, Tian 2005] and pre-applied underfills [Hannan 2004, Morganelli 2005]. Magnitude of acceleration, effect of drop orientation on the product

performance of fine-pitch electronics has been studied. [Wu 1998, Lim 2002, Tan 2005]. Failure modes typically include, cracking of the printed circuit board dielectric, copper trace fractures, copper-delamination, first-level and second-level solder-interconnects failure, silicon and dielectric failures in Cu Low-K devices. Transition to wafer-level chip scale package (CSP) and flip chips with smaller finer pitches and smaller solder joint interconnects requires the need for better predictive capabilities for determination of design margins. Modeling efforts have focused on prediction of the transient dynamic behavior, and included the use of explicit finite-elements with and without smeared properties [Lall 2004, 2005, Xie 2002, 2003, Wu 1998, 2000], implicit finite elements [Irving 2004, Pitaressi 2004, Syed 2005], and submodeling [Tee 2003, Wong 2003, Zhu 2001, 2003, 2004]. Previously, prediction of failure has been investigated using fracture mechanics [Shah 2004], von-mises stress [Tee 2004], and boardstrain based damage index [Lall 2005]. Strain behavior of electronic assemblies is not elastic and the large transient deformation are often not accurately represented by the small strain theory. In addition, the final or the peak strain does not capture the final strain or damage state of the assembly. The rate-ofchange of deformation and the latent damage in previous drops impacts the susceptibility to failure during successive drops. Dynamic responses at board level [Sogo 2001, Mishiro 2002] at product level [Lim 2002, 2003] have been measured by previous researchers. Failure may not happen in the first drop, and damage may be cumulative. There is need for techniques and damage proxies which enable the determination of damage equivalency and cumulative damage during overstress and repetitive loading for various packaging architectures. 2. Modeling Approaches One of the challenges in modeling shock response of electronic products, is the multiple-scale differences between the dimensions of the individual layers, such as solder interconnects, copper pad, chip-interconnects and the dimensions of the electronic assembly, which makes the computational effort needed to attain fine mesh to model chip interconnects while capturing the system-level dynamic behavior very challenging. Various modeling approaches have been pursued to reduce the computational time required for simulation. Zhu [2001] applied solid-to-solid sub-modeling technique to analyze BGA reliability for free board level drop using half PCB board. Shell-to-solid sub-modeling using beam-shell based quarter symmetry global model was employed by Ren, et. al. [2003, 2004] to further reduce the computational time. Previously, the JEDEC JESD22BIll has been modeled using the input-G method [Tee 2004]. Symmetry of load and boundary conditions has been used to attain computational efficiency and decrease the model size. The assumption of symmetry in state-ofart models targets symmetric modes predominantly. The explicit time-integration is most suitable for solving wave

propagation problems such as drop impact [Lall 2004, 2005]. The simulation time is determined by the size of the time step which is directly proportional to the length of the smallest element in the model. Board level drop simulations using smeared property approach have been carried out and validated with experimental data. Transient dynamic responses of board assemblies have been predicted fairly accurately while achieving computational efficiency.

Explicit Modeling Approach The transient dynamic response of a printed circuit board under drop impact can be represented in the finite element domain with step-by-step direct integration in time for the explicit formulations. The governing differential equation of motion for a dynamic system can be expressed as, [Lall 2006a, b, c, dI

[IM]{b} +[C]{}Mn+ J{R'}n

{R

(1)

t}

For a linear problem, {Rint } =[K]{D}n, where [M], [C] and [K] are the mass, damping and stiffness matrices respectively and {D}n is the nodal displacement vector at

various instants of time. Methods of explicit direct integration calculate the dynamic response at time step n+1 from the equation of motion, the central difference formulation and known conditions at one or more preceding time steps [Lall 2006a, b, C, d], [+

At2

2At

CijDj

1{ Rex}n- R'

+ At2 [M]{D}n At2

In

(2)

2AtCl{D}n1

Equation (2) has been combined with equation (1) at time step n. In the implicit algorithm, the dynamic response at time step n+1 has been calculated from known conditions at present time-step, in addition to one or more preceding time-steps. Using Newmark relations and the average acceleration method, the equation of motion can be written as follows [Lall 2006a b, c, d],

[Keff]{D}n+ +

{R ext}n

1 +( [mlpLPA2t2 {D}n + pAt In ~2p

)

In

[c] 7{D}n +( 13 {D}n +At 7- 1J {D}} Where, 1 [M]+ ' [C]+ [K] [Keff ]= f3At2 f3At

(3)

(4)

and y and D are numerical factors that control the characteristics of the algorithm such accuracy, numerical stability and amount of algorithmic damping. All the terms on the right hand side of Equation (2) are known and have already been calculated at earlier time steps,

however the same is not true of Equation (3). The mass matrix, [M] has been diagonalized, using the lumped approach, improving computational efficiency, because time step is executed very quickly without solution of simultaneous equations. Use of the lumped mass approach increases the allowable step time but is limited to the explicit formulation. For the implicit formulation, the effective stiffness matrix, [Keff] is not a diagonal matrix, even if the mass and damping matrices are diagonalized, since it contains the stiffness matrix, [K]. The diagonal mass matrix in implicit formulation therefore provides very little computational economy. Furthermore, the implicit method is usually more accurate when [M] is the consistent mass matrix, thus increasing the computational time and storage space. Element size in the explicit model has been limited due to the conditional stability of the explicit timeintegration, which influences the critical value for the time step, to avoid instability and error accumulation in the time integration process. This limiting criterion increases the number of time steps required to span the time duration of an analysis. Explicit time-integration is well suited to wave propagation problems including drop impact, because the dynamic response of the board decays within a few multiples of the longest period. Most implicit formulations, are unconditionally stable, which means that the process is stable regardless of the size of the time step, thus allowing a fewer number of time steps as compared to the explicit method. However, high deformation rates involved in impact, using the implicit formulation with a large time step might introduce too much strain increase in a single time-step, causing divergence in large deformation analysis. A large timestep may cause the contact force, which is proportional to the penetration of the contact bodies, to be very large at the contact causing local distortion and failure. Advantage of being able to use a larger time step with implicit methods can only be used in a limited manner for impact analysis. The explicit formulation is better suited to accommodate material and geometric non-linearity without any global matrix manipulation.

Explicit-Models and Element Formulations Reduced integration elements have been used in the analysis because they use fewer integration points to form the element stiffness matrices, thus reducing the computational-time for simulation of transient dynamic events. First-order elements perform better, when large strains or very high-strain gradients are expected as in the case of impact. Higher order elements have higher frequencies than lower order elements and tend to produce noise when stress waves move across an FE mesh. Therefore, lower order elements are better than higher order elements at modeling a shock wave front. Two types of shell elements are available in AbaqusTM including,: conventional shell elements and continuum shell elements. The use of both elements has been investigated for modeling transient-dynamic events. The conventional shell elements discretize the surface by

defining the element's planar dimensions, its surfacenormal, and its initial curvature. Surface thickness is defined through section properties. Quadrilateral elements have been used with linear interpolation. The conventional shell-element is a reduced integration element which accounts for large strains and large rotations

Figure 1: Printed Circuit Assembly has been modeled using Smeared Properties with Conventional Shell Elements. [Lall 2004, 2005]

Solder Interconnects Mold Compound

Chip

Die-Attach

L i.

Substrate

Figure 2: Printed-Circuit Assembly with TimoshenkoBeam Element Interconnects and CONTINUUM ShellElements. [Lall 2006a b] Continuum shell elements resemble three-dimensional solid elements and discretize the entire three-dimensional body. The continuum shell elements are formulated such that their kinematic and constitutive behavior is similar to

conventional shell elements. The continuum shell element (SC8R), has three-translational degrees of freedom at each node and the element accounts for finite membrane strains and arbitrarily large rotations [Abaqus 2005a]. Shell elements are used to model the printed circuit board, since the thickness dimension is significantly smaller than the other dimensions and the stresses in the thickness direction are smaller than in the in-plane directions. First order tetrahedral elements (C3D4) have not been used for analysis, since they have a simple, constant-strain formulation and very fine meshes are required for an accurate solution.

that the strain in the beam's cross-section is the same in any direction in the cross-section and throughout the section. For fine pitch solder interconnects, with very low stand-off heights, the constant cross-section assumption is a fairly good approximation.

Packag,e Pad Hexahedral Element Interconnects

Mold

Co~mno~iind Chip

A'

Timoshenko-Beam Interconnects

Die Attach Substrate Section AA' Figure 4: Global-Local Explicit Sub-Modeling with Hexadedral-Element Corner Interconnects, TimoshenkoBeam Element Interconnects and PCB meshed with Hexahedral Reduced Integration-Elements. [Lall 2006a b]

Figure 3: Printed-Circuit Assembly with TimoshenkoBeam Element Interconnects and CONVENTIONAL Shell-Elements. [Lall 2006a b]

*

,

Interconnects modeling has been investigated using two element types including the three-dimensional, linear,

*

U

Timoshenko-beam element (B3 1) and the eight-node hexahedral reduced integration elements. Threedimensional beams have six degrees of freedom at each node including, three translational degrees of freedom (13) and three rotational degrees of freedom (4-6). The rotational degrees-of-freedom have been constrained to model interconnect behavior. The B3 1 elements allow for shear deformation, i.e., the cross-section may not necessarily remain normal to the beam axis. [Abaqus 2005b]. Shear deformation is useful for first-level interconnects, since it is anticipated that the shear flexibility may be important. It is assumed throughout the simulation that, the radius of curvature of the beam is large compared to distances in the cross-section and that the beam cannot fold into a tight hinge. It is also assumed

3~~

U

Figure 5: Drop-orientation has been varied from 00 JEDEC-drop to 90° free-drop. [Lall 2006a b]

Table 1: Comparison of Actual and Simulated Component Masses. [Lall 2006a b] Component Actual Mass Simulated Weight (gm) (gm) PCB 28.15 28.25 CSP 0.140 0.142 31.8 31.8 Weight Four explicit model approaches have been investigated including, smeared property models (Figure 1), Timoshenko-beam element interconnect models with continuum shell-element (Figure 2), Timoshenko-beam element interconnect models with conventional shellelement (Figure 3), and the explicit sub-models with combination of Timoshenko-beam elements and reduced integration hexahedral element corner interconnects (Figure 4). For each different type of element used for the PCB, the various component layers such as the substrate, die-attach, silicon die, mold-compound have been modeled with C3D8R elements. The solder interconnections have been modeled with two-node beam elements (B31). Smeared properties have been derived all the individual components based on volumetric averaging [Lall 2004, 2005]. The simulated weight of the model for the PCB and all the components closely approximates the actual weights as shown in Table 1. The concrete floor has been modeled using rigid R3D4 elements. In case of free vertical drop, a weight has been attached on the top edge of the board. Node to surface contact has been employed between a reference node on the rigid floor and the impacting surface of the test assembly. The drop orientation has been varied from 00 JEDEC-drop to 90° free-drop (Figure 5). Explicit sub-modeling has been accomplished using a local model, in addition to the global model. The local model is finely meshed and includes all the individual layers of the CSP and the corresponding PCB portion. The four corner solder interconnections are created using solid elements while the remaining solder joints are modeled using beam elements. Shell-to-solid submodeling technique has been employed to transfer the time history response of the global model to the local model. Displacement degrees of freedom from the global model are interpolated to the local model and applied as boundary conditions. The corresponding initial velocities for the respective drop orientation were assigned to all the components of the sub-model. 3. Damage Detection Repeatability of drop orientation is critical to measuring a repeatable response. Small variations in the drop orientation can produce vastly varying transient-dynamic board responses. Significant effort was invested in developing a repeatable drop set-up. The drop height is varied to obtain shock pulses of various magnitudes, in addition to the 1500 Gs, 0.5 millisecond duration, halfsine input pulse (Figure 6). In addition to JEDEC droptest, free-drop test of the printed circuit assemblies can be studied with motion control setup of the drop-tower.

Figure 7 shows component locations on the test boards instrumented with strain sensors. Figure 8 shows strain and continuity data acquired during the drop event using a high-speed data acquisition system at 2.5 to 5 million samples per second. Figure 9 shows the drop-event simultaneously monitored with ultra high-speed video camera operating at 40,000 frames per second. Targets are mounted on the edge of the board to allow high-speed measurement of relative displacement during drop. [Lall 2004,2005 2006ab' C, d]

lmnact. [Lafl 2005

2006b]

Figure 7: Experimental Set-up for Controlled Drop. [Lall 2005, 2006b] 350

200 50

Strain Continuity

-100

-250 -400

Time (seconds)

Figure 8: Package Strain and continuity transient history in JEDEC drop-shock, for the 8mm, 95.5Sn4AgO.5Cu ball-grid array. [Lall 2005, 2006b]

Figure 8 shows strain, displacement, orientation angle, velocity, acceleration, and continuity data acquired simultaneously. Figure 6 shows a typical relative displacement plot measured during the drop event using an image tracking software to quantitatively measure displacements. The position of the vertical line in the plot represents the present location of the board (i.e. just prior to impact in this case) in the plot with "pos (m)" as the ordinate axis. The plot trace subsequent to the white scan is the relative displacement of the board targets w.r.t. to the specified reference. Figure 7 shows the board instrumentation for strain and relative displacement during horizontal JEDEC drop. In addition to relative displacement, velocity, and acceleration of the board prior to impact was measured. This additional step was necessary since, the boards were subjected to a controlled drop, in order to reduce variability in drop orientation.

displacements (Table 2) have been correlated between smeared property and conventional-shell models at the various locations along the board length. The error in the predicted values is in the neighborhood of 8-25% for both models.

S., Ci,

A

75

)

.X43 '4i

.j j j. UfM

*1991Q0o

*15976"

*23686+0

OdS o~1o

b AHAQ

IiX

M4V

66-

X2 515A&2 Thue

t = 2.4ms

1...

24l32r6iM

Figure 9: Test Set-Up for Free-Drop of Printed Circuit Assemblies. [Lall 2005, 2006b] Figure 8 shows the strain history during JEDEC dropshock for a 8mm 95.5Sn4AgO.5Cu ball-grid array package. Failure in the device has been identified as an increase in voltage drop. Different locations on the test board exhibit different strain histories during the same drop and different number of drops to failure. However, the strain histories are very consistent and repeatable at the same component location on the test board for various drops. The strain history is also very repeatable for the same component location across various test boards. 4. Model Correlation In this section, the field quantities and derivatives of field-quantities have been compared from both various explicit finite element models and experimental data in free-drop and JEDEC-drop. In addition, the transient strain histories of the solder interconnects have been correlated to location of failure. Susceptibility of the CSPs to chip-fracture in shock or drop has been investigated using the modeling approach. Correlation of Transient Mode-Shape, Peak Relative Displacement, and Peak Strain Figure 10 shows the transient mode shapes of the printed circuit board from high-speed video and explicit finiteelement simulation at 2.4 ms and 4.8 ms after impact. The model prediction shows good correlation with the experimentally observed mode shapes. The peak relative-

+1777q

*1244 Se +L. +533NOY

+1i 3007

ODW~JcdOqaddb A1WA &LXICf1[vWAd54 'm&O15ASKA254 I1563t pTio OEM

FX.Xr&lBe

t - 48ms

Figure 10: Correlation of Transient Mode-Shapes during JEDEC-Drop. [Lall 2006a b] Smeared E Continuum Shell-Beam

-A-

Conventional Shell-Beam A Experiment

--

0.0065-

w

0.0045

0.0025 w

0.0005 1-

2

-0.0015

1

50

100

150

200

> -0.0035

2 -0.0055 9 -0.0075

Board Length (mm)

Figure 11: Correlation Between Experimental Relative Displacement of Board Assembly at 2.4 ms with Model Predictions under zero-degree JEDEC drop-test. [Lall 2006 a, bI

Table 2: Correlation of Peak Relative-Displacement Values with high-speed experimental data in zero-degree JEDEC Drop (mm). [Lall 2006a b] Loc Loc Loc El E3 E5 4.58 Experiment (mm) 3.61 4.47 Smeared Property 3.86 3.35 3.39 25.86 Error (/O) -7.03 24.93 3.26 Timoshenko-Beam, 3.80 4.16 Continuum Shell 28.73 Error (°O) -5.17 6.97 4.15 Timoshenko-Beam, 4.43 4.85 Conventional Shell 9.21 Error (°O) -22.8 -8.62

Figure 11 shows the correlation of the board relative displacement 2.4 ms after impact, from high-speed image analysis with the model predictions from smeared, continuum-shell with Timoshenko-beam, conventionalshell with Timoshenko-beam models. The peak strain values have also been correlated for the models versus experimental data in 90-degree orientation free-drop. The peak strain values (Table 3) exhibit error in the rage of 10-30%. All the three-modeling approaches including smeared properties, conventional-shell with beam elements, and continuum-shell with beam elements exhibit similar results. The wires on the right-side of the board are for strain and continuity measurement during the shock-event. Table 3: Correlation of Peak-Strain Values from Model Predictions Versus Experiments for 90-degree Free-Drop. [Lall 2006a, b] Loc Loc Loc Cl C3 C5 2248 1667 Experiment (microstrain) 1417 1424 Smeared Property 1603 1563 Error (O) -13.15 30.48 14.56 Timoshenko-Beam 1820 1990 1960 Continuum Shell Error (O) -28.47 11.49 -17.60 Timoshenko-Beam 1760 1630 2070 Conventional Shell Error (°O) -24.24 27.50 -24.20

Solder Interconnect Strain Histories Figure 12 and Figure 13 show the strain plots from the Timoshenko-Beam Element with Conventional-Shell model prediction for the solder interconnection located at the outermost corner of the package and in the solder interconnect located at the corner of the fourth-row from the outside, during a 0° JEDEC-drop. Plots indicate that the transient strain history is very different at the fourcorners of the chip-scale package. Therefore, the susceptibility of the solder interconnects to failure may be different in different corners.

0.002 r

0.0015

0.001 ;

-- Top Left Top Right Bottom Left Bottom Right

0.0005 U~

0

e -0.0005

-0.001 0

-0.0015 -0.002

Time(sec)

Figure 12: Timoshenko-Beam Element with Conventional-Shell Model Prediction of Transient Strain History at the Package Corner Solder Interconnect during 00 JEDEC-Drop. [Lall 2006a b] A comparison of transient strain histories in Figure 12 and Figure 13 reveals that, a large portion of the strain is carried by the outside row of the solder interconnects. For this reason, the explicit sub-model includes reducedintegration hexahedral elements for the corner solder interconnect. The beam elements allow output of the axial strain and the transverse shear strain only. The hexahedral element mesh solder interconnects provide insight into the logarithmic strain, LE23, distribution in the solder interconnects. Model results indicate that the strains are maximum at the solder-joint to package interface and the solder-joint to printed circuit board interface, indicating a high probability of failure at these interfaces. Failure analysis of the samples reveals that the observed failure modes correlate well with the model predictions. (Figure 15) r

;

.I t

2 *5 a

0 ;

0.0001 0.00008 0.00006 0.00004

--

0.00002 0 -0.00002 -0.00004 -0.00006 -0.00008 -0.000 1

U~

Top Left Top Right Bottom Left Bottom Right

Time(sec) Figure 13: Timoshenko-Beam Element with Conventional-Shell Model Prediction of Transient Strain History in the Solder Interconnect Located at the Corner of the 4-Inner Row from Outside during 00 JEDEC-Drop. [Lall 2006a, b]

t

=

2.4 ms

t

=

3.6 ms

the complete duration of the stress signal, using sine and cosine functions that are uniform in time. The Fourier Transform does not contain any time dependence of the signal and therefore cannot provide any local information regarding time evolution of its spectral characteristics. Transient impulses often occur as discontinuities in the signal. Representation of the local characteristics of signal in Fourier Transform is very inefficient and requires large number of Fourier Components. 1000

C:

CZ, o

t =4.8ms

t =6ms

Figure 14: Global-Local Explicit Sub-Model Predictions of Transient Logarithmic Shear Strain, LE23, in the Solder Interconnect of one of the Chip-Scale Packages on the Printed Circuit Board Assembly during a Zero-Degree JEDEC-Drop. [Lall 2006a b]

500 0

C:-500 -1000

-1500l -5

0

5 10 Time (sec)

15

20

x

10-3

Figure 16: Transient Strain During Drop-Impact of Printed Circuit Assembly From 6ft. [Lall 2005, 2006b]

Figure 15: Cross-section of corner solder interconnect in the failed samples showing higher susceptibility of the samples to fail at the package-to-solder interconnect interface or the solder-to-printed circuit board interface. [Lall 2006a, b] 5. Wavelet Decomposition for Transient Analysis Wavelets have been used in several areas including data and image processing [Martin 2001], geophysics [Kumar 1994], power signal studies [Santoso 1996], meteorological studies [Lau 1995], speech recognition [Favero 1994], medicine [Akay 1997], and motor vibration [Fu 2003, Yen 1999]. However, the application of wavelets to analysis of transient-response of electronics under shock and vibration is new. In this paper, wavelets and wavelet transforms have been used to analyze transient signals acquired during drop-impact of printed circuit board assemblies. (Figure 16) Wavelets based time-frequency analysis is specifically useful to analyze non-stationary signals. A timefrequency representation describes simultaneously when a signal component occurs and how its frequency spectrum develops with time, so as to extract the transients or sudden spikes in the signal. Wavelet transform is more suitable to determine the frequency spectrum of the transient strain, acceleration or displacement signals as the Fourier transform extracts frequency information for

One candidate for extracting the local frequency information from a transient strain signal could have been the Windowed Fourier Transform. However, in a Windowed-Fourier Transform, a time series is examined under a fixed time-frequency window, i.e. the resolution or interval is constant in both time and frequency domains. In transient dynamics, a wide range of frequencies are involved and a fixed time window of the Windowed-Fourier Transform tends to have a large number of high-frequency cycles and a few lowfrequency cycles or parts of cycles. This causes overrepresentation of the high-frequency components and an under-representation of the low-frequency components. Therefore, different resolutions are required to analyze a variety of signal components of different duration. The accuracy of extracting frequency information is limited by the length of the window relative to the duration of the singularity in the signal. The use of wavelet transforms enables the examining of the transient signal shown in Figure 16, at different time windows and frequency bands, i.e. at different time resolutions and frequency resolutions, by controlling translation and dilation of wavelets and achieve optimal resolution with the least number of base functions. The size of the time window is controlled by the translation or positioning of the wavelet while the width of the frequency band is controlled by the dilations or scaling of the wavelet. In this case, wavelets therefore enable higher frequency-resolution and lower time-resolution in low frequency part, and at the same time enable lower frequency-resolution and higher time resolution in high

-iwApnxmato230De

frequency part. The wavelet transform is defined by [Lall 2005, 2006b]

Wf(u,s)=(fs))= Jff(t)= Is i

dt

(4)

where the base atom yv is the complex conjugate of the wavelet function which is a zero average function, centered around zero with a finite energy. The function f(t) is decomposed into a set of basis functions called the wavelets with the variables s and u, representing the scale and translation factors respectively.

Variable Amplitude Transient-LoadAnalysis In transient-shock and drop, the loads vary in both amplitude and frequency. Electronic structures very rarely experience constant amplitude loading. To analyze the structures in operating conditions, strain measurements and relative displacement measurements taken at specific locations, have been analyzed using Daubechies, D1o wavelet with 12-level decomposition. For cycle-counting analysis the second approximation, A2 has been used as input to the rainflow algorithms. In rainflow analysis, the strain time history data is drawn with time axis vertical with increasing time downwards. Rainflow cycles are then defined analogous to rain falling down the roof. Detailed rules for cycle counting are described in [ASME 1997, Bannantine 1990, and Downing 1982]. A flow of rain is begun at each strain reversal in the history and is allowed to continue to flow unless, (a) the rain began at a local maximum point (peak) and falls opposite a local maximum point greater than that from which it came. (b) the rain began at a local minimum point (valley) and falls opposite a local minimum point greater (in magnitude) than that from which it came. (c) it encounters a previous rainflow.

--

e

/

100,

-

20.1

histograms are very similar. Damage has been computed for each component, till failure. 100000 10000 1000 C)

100

10

I 50

300

550 800 1050 1300 1550 1800 2050

Strain Amplitude (microstrains)

Figure 18: Cycles Versus Strain Amplitude for Transient Strain History from Rainflow Algorithm. Histogram is for 95.5Sn4AgO.5Cu Solder Joint Failures during the Drop for 132 I/0, 8 mm Ball Grid Array. [Lall 2005, 2006 b] All information about the sequence of the individual strain variation is lost during counting. The resulting cumulative frequency distribution histogram, gives the overall number of load cycles for each load amplitude. A relative damage index has been defined such that the damage magnitude at failure is "1". Linear superposition of damage has been assumed in this study. The equation can be re-written as follows based on the assumed logarithmic relationship between strain and number of cycles (Coffin-Manson Relationship), [Lall 2005, 2006b] m 1 Dk 1 Nk (5a, b) k=l AE;8 k ki~~

D k=1 kiD

n

V2)

where, "k" is the bin-index for the histogram, Ag /2 is the printed circuit board strain amplitude, M is the total number of bins in the histogram, N is the number of cycles subjected on the sample in the kth histogram bin during all the drops until-failure of the device, and D is the damage index. Data from data sets has been solved as follows, [Lall 2005, 2006b]

Reduction in time-resolution (Sub-Sampling) but increase in frequency resolution. (Spans l/2 Frequency Band)

Figure 17: Approximation and Details 1-6 for a 12-Level Decomposition for Transient Strain Signal During Drop, Based on Daubechies 10 Wavelet. The transient-dynamic data in time-domain has been reduced into histograms of load cycle amplitudes and number of cycles. Number of cycles is calculated using cycle counting algorithm for the transient-strain history. Figure 18 is the histogram for one of the drops to failure showing the number of cycles for a specific strain amplitude during the transient signal. The transient strain signal has a high number of very small strain amplitude cycles and very few number of large strain amplitude cycles. Damage from both repeatable and non-repeatable drops has been analyzed. For repeatable drops, the strain

1

(6a, b)

/i+l

where the index "i" indicates the drop number. Each data-set includes test-vehicles which have been droppedto-failure, therefore the cumulative relative damage index is 1. The load histories have been varied by varying the angle of impact by a small magnitude. Subtracting the two equations, we get, N

N

N

N

(7)

Average values of the exponent, "n" and coefficient "A' have been computed over the complete data-set. Since, the values have been computed for board strain or package strain, they are specific to the test structure analyzed. The relative damage in any particular drop is computed based on total damage at failure (Figure 19, Figure 20). The advantage of the proposed approach is that it can be used to calculate damage in the test structures of interest, instead of an idealized test specimen. The test samples are cross-sectioned after failure, and the test data was sorted based on failure modes. 6. Definition of the Failure Envelope and Model Correlation The relative damage index has been used to predict the number of drops to failure for the 8 mm Ball Grid Array, The location for the 95.5Sn4AgO.5Cu, 132 I/0. predictions is different from location at which the experimental data was acquired. Therefore, the transientstrain history and the damage progression is also different. 1.2

0.8

Simulation,

E 0.6 0

~~~~~~~~~95.5Sn4.OAgO.5Cu, ~~~~8mm BGA

0.6

Experiment,

*~0.4" 0.2

95.5Sn4.OAgO.5Cu, 8mmBGA

/+

0

0

2

4

6

8

Number of Drops

Figure 19: Correlation of Damage Progression and Number of Drops to Failure Between Experiment and Simulation for the 8 mm, 95.5Sn4AgO.5Cu, 132 I/0 Ball Grid Array. [Lall 2005, 2006b] 1.2

.1E0.8

-4-~~~~~~~~~~~~~~~+/>f +~

o .6 0

/

1 0.4

Simulation, 63 Sn3 7Pb, 8mm BGA

Experiment, 63 Sn3 7Pb, 8mm BGA

0

0

5

10

15

Number of Drops

Figure 20: Correlation of Damage Progression and Number of Drops to Failure Between Experiment and Simulation for the 8 mm, 63Sn37Pb, 132 I/0 Ball Grid

Array. [Lall 2005, 2006b] Model prediction indicates 5 drops-to-failure and correlates well with the experimental data, which indicates that the ball-grid arrays at the location of

measured transient strain failed after 6 drops. The present data-set is one has been chosen for correlation, because it is a representative average of the damage progression at this location. Number of drops-to-failure at this location ranged between 5-7 drops. The correlation is for a nonrepeatable drop, indicated by the non-uniform damage progression in experimental data-set (Figure 19). Model predictions and correlation with experimental data for the 63Sn37Pb, 8mm BGA is shown in Figure 20. The model predictions indicate failure after 9 drops-tofailure at the location of the transient strain trace. Representative average experimental data for the failure location exhibits failure after 10 drops. The relative damage index approach outlined in this paper provides a method to define the failure envelope for packaging architectures. The solder interconnect strain is not as easily measurable as board strain. The proposed methodology enables evaluation of the failure envelope in the application of interest and for the packaging architecture in question. Damage during the life of the product should not exceed "1" for the design to have good survivability in drop and shock applications. The constants used for damage progression are specific to the package architecture and boundary conditions. The proposed methodology is amenable to implementation not just at board-level but also at system-level. 7. Summary and Conclusions Four explicit modeling techniques have been investigated for modeling shock loading of printed circuit board assemblies. The focus of the paper is on modeling multiple scales from first-level interconnects to assemblylevel transient dynamics. Modeling techniques investigated include, smeared properties, Timoshenkobeam with Conventional Shell Elements, TimoshenkoBeam with Continuum Shell Elements, and Explicit Submodeling. The paper extends the state-of-art, which presently focuses on prediction of interconnect stresses based on assumptions of symmetry of geometry and boundary conditions. In this paper, modeling techniques have been developed to capture system-level dynamics in

addition to interconnect transient-stress and transientstrain histories, without any assumption of assembly The ability to symmetry, has been demonstrated. eliminate symmetry assumptions enables the modeling of asymmetric modes in addition to symmetric modes. The model predictions have been correlated with experimental data from high-speed video, high-speed image analysis and high-speed strain acquisition. Methodology for development of the failure envelope for area-array packaging architectures has been presented. Wavelet transforms which have been used extensively in several areas including data and image processing, geophysics, power signal studies, meteorological studies, speech recognition, medicine, and motor vibration, have been applied to analysis of transient-response of electronics under shock and vibration. Wavelets have been used to avoid the problem of fixed time-frequency window with windowed Fourier transforms, which causes

over-representation of the high-frequency components and an under-representation of the low-frequency components of a transient drop-impact signal. The need of different resolutions required to analyze a variety of signal components of different duration has been addressed by using wavelet transforms. The Daubechies D1o wavelet with 12-level decomposition has been used to analyze non-stationary transient dynamic signals. A relative damage index has been developed for prediction of the number of drops-to-failure under transient loads. The research presented attempts to address the need for techniques and damage proxies which enable the determination of failure-envelopes and cumulative damage during overstress and repetitive The loading for various packaging architectures. approach is based on assembly strains, since there are experimental limitations of measuring field-quantities and their derivatives at the board-solder joint interface, primarily because of the small size of interconnects in fine-pitch ball-grid array packages. Explicit finite element models in conjunction with the proposed approach have been used to predict survivability of finepitch ball-grid arrays in transient-shock and vibration. The approach has been applied to both leadfree (95.5Sn4.OAgO.5Cu) and leaded (63Sn37Pb) ball-grid array architectures. The validation has been presented for both repeatable and non-repeatable drops. Acknowledgments The work presented here in this paper has been supported by a research grant from the Semiconductor Research Corporation (SRC), Research ID 1283. References Abaqus Documentation, Finite Elements and Rigid Bodies, Getting Started with Abaqus Explicit: Keywords Version, Version 6.5, Section 4.1, 2005 a Abaqus Documentation, Beam Element Overview, Abaqus Theory Manual, Version 6.5, Section 3.5.1, 2005 b

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