CSE567: Digital Systems Design Verilog Tutorial

CSE567: Digital Systems Design Verilog Tutorial Charles Gordon (Version 1.0: October 17, 2001)

Contents 1 Behavioral Model

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2 Test Framework

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Behavioral Model

Verilog is a hardware description language (HDL) used to design and document hardware. Verilog uses a C-like syntax to describe hardware logic. It can be used in SUE to avoid the sometimes tedious work of drawing large schematics. In most cases Verilog is used to create the small, “primitive” components of a circuit and then connected schematics are used to represent the high-level circuit. The visual view provides a highly readable representation, while the Verilog code reduces the amount of manual drawing that must be done. In this tutorial we will create a Verilog behavior model for the majority circuit from the first tutorial. To get started, go to the File menu, select “open...” and open the majority.sue file you created in the first tutorial. If you have not yet completed the first tutorial, you should go back and create this file now. Press the ’c’ key to switch to the icon view (this corresponds to the “swap views” command in the View menu). Now we will need to create a Verilog property for this circuit. Go to the Sim menu and select “create verilog property”. This will create a large text block which you can place below the other three text blocks. Your icon view should look like the one in figure 1.

Figure 1: The icon view with a Verilog property defined.

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Now type the ’c’ key to get back to the schematic view. We need to write the Verilog code for the behavioral model. Go to the Sim menu and select “edit verilog”. SUE will bring up a dialog box saying that it can’t find a Verilog file for majority. Simply hit Done and SUE will create a default file and bring it up in an emacs window. You should see some code that looks like the following: // Created by MMI_SUE3.4 module majority (A, B, C, Out); input A; input B; input C; output Out; // Enter verilog here endmodule Go to the blank line after the comment and enter the following: assign Out = A&B | B&C | A&C; So now the entire file should look like: // Created by MMI_SUE3.4 module majority (A, B, C, Out); input A; input B; input C; output Out; // Enter verilog here assign Out = A&B | B&C | A&C; endmodule At this point you have created a behavioral model for the majority circuit to go with its schematic view. You should have a good idea of the process of creating and attaching a Verilog model to a module. You have also had a first look at Verilog, which you will be learning more about in class. In the next section we will create a Verilog test framework you can use to test this new majority component.

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Test Framework

In the first tutorial, where you created the original majority circuit, we used a simple counter set up to test the circuit. In this tutorial we will create a slightly more complicated test framework that will use Verilog. To get started, go to the File menu and select “new schematic...”. Name the schematic majorityTF.sue. We are not going to create a schematic model of this module, but we still need to define the inputs and outputs. Create a single input named Cout and three outputs named A, B and C as shown in figure 2. Now go to the View menu and select “make other view”, which will create an icon view and switch you to it. Draw an icon using the rectangle tool and text tool to label inputs and outputs. Then go to the Sim menu and select “create verilog property”. Move the text below the other text blocks. You should have something like what is shown in figure 3.

Figure 2: The schematic for the test fixture. Now select “edit verilog” from the Sim menu. This will bring up a dialog box saying that it can’t find a Verilog file. As before, hit Done to create the default file and bring it up in emacs. Once you have the file open, type in the text under the comment: // Created by MMI_SUE3.4 4

Figure 3: The icon view for the test fixture.

module majorityTF (Cout, A, B, C); input Cout; output A; output B; output C; parameter delay = 10; reg[2:0] cnt; initial begin cnt = 0; repeat (8) begin #delay cnt = cnt + 1; end $finish end

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assign {A,B,C} = cnt; initial begin $monitor (‘‘@ time=%0d A=%b, B=%b, C=%b, Cout=%b’’, $time, A, B, C, Cout ); end endmodule This Verilog program will loop through all possible inputs and print out the signals at every step (this will appear on the command prompt from which you launched SUE). To test this framework, create a new schematic and connect it to the majority circuit you created in the first tutorial. Follow the standard steps to run the simulation (see the previous tutorials).

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