VLSI Digital Systems Design

VLSI Digital Systems Design

CMOS Processing

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Si Purification • Chemical purification of Si • Zone refined – Induction furnace – Si ingot melted in localized zone – Molten zone moved from one end to the other – Impurities more soluble in melt than in solid – Impurities swept to one end of ingot

• Pure Si = intrinsic Si (impurities < 1:109) cmpe222_03process_ppt.ppt

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Czochralski Technique for Single-Crystal Ingot Growth, Melt • Remelt pure Si – Si melting point = 1412 C – Quartz crucible with graphite liner – RF induction heats graphite

• Dip small Si seed crystal into melt – Seed determines crystal orientation

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Czochralski Technique for Single-Crystal Ingot Growth, Freeze

• Withdraw seed slowly while rotating

– Withdrawal and rotational rates determine ingot diameter – 30-180 mm/hour – Largest current wafers = 300 mm

• Si crystal structure = diamond

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Single-Crystal Ingot to Wafer • Diamond saw cuts grown crystal into slices = wafers – 0.25-1.00 mm thick

• Polish one side of wafer to mirror finish

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Oxidation Converts Si to SiO2 • Wet oxidation – Oxidizing atmosphere contains water vapor – 900-1000 C – Rapid

• Dry oxidation – Oxidizing atmosphere pure oxygen – 1200 C

• Volume of SiO2 = 2 x volume of Si – SiO2 layer grows above Si surface approximately cmpe222_03process_ppt.ppt as far as it extends below Si surface

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Dopants • Si is semiconductor: Rconductor < RintrinsicSi < Rinsulator • Dopants = impurity atoms – Can vary conductivity by orders of magnitude

• Dopant atom displaces 14Si atom in crystal • Each 14Si atom shares 4 electrons with its 4 neighbors in the crystal lattice, to form chemical bond – Group (column) IV-A of Periodic Table cmpe222_03process_ppt.ppt

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Donor Atoms Provide Electrons • • • •

Group V-A of Periodic Table Phosphorus, 15P, and Arsenic, 33As 5 electrons in outer shell, 1 more than needed Excess electron not held in bond is free to drift • If concentration of donors > acceptors, n-type Si

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Acceptor Atoms Remove Electrons from Nearby Atoms • • • •

Group III-A of Periodic Table Boron, 5B 3 electrons in outer shell, 1 less than needed Incomplete bond, accepting electron from nearby atom • Movement of electron is effective flow of positive current in opposite direction • If concentration of acceptors > donors, p-type Si cmpe222_03process_ppt.ppt

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Epitaxy • Greek for “arranged upon” or “upon-ordered” • Grow single-crystal layer on single-crystal substrate • Homoepitaxy – Layer and substrate are same material

• Heteroepitaxy – Layer and substrate differ

• Elevate temperature of Si wafer surface • Subject surface to source of dopant cmpe222_03process_ppt.ppt

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Deposition and Ion Implantation • Deposition – Evaporate dopant onto Si wafer surface – Thermal cycle • Drives dopant from Si wafer surface into the bulk

• Ion Implantation – Energize dopant atoms – When they hit Si wafer surface, they travel below the surface cmpe222_03process_ppt.ppt

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Diffusion • At temperature > 800 C • Dopant diffuses from area of high concentration to area of low • After applying dopant, keep temperature as low as possible in subsequent process steps

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Common Dopant Mask Materials • • • •

Photoresist Polysilicon (gate conductor) SiO2 = Silicon dioxide (gate insulator) SiN = Silicon nitride

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Selective Diffusion Process 1.Apply dopant mask material to Si wafer surface – Dopant mask pattern includes windows

2.Apply dopant source 3.Remove dopant mask material

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Positive Resist Example • Apply SiO2 • Apply photoresist – PR = acid resistant coating

• Pass UV light through reticle – Polymerizes PR

• Remove polymerized areas with organic solvent – Developer solution

• Etch exposed SiO2 areas

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Lithography Pattern Storage, Technique 1 • Mask – Two methods for making 1.Electron beam exposure 2.Laser beam scanning

– Parallel processing

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Lithography Pattern Storage, Technique 2 • Direct Write – Two writing schemes 1.Raster scan 2.Vector scan

– Pro • No mask expense • No mask delay • Able to change pattern from die to die

– Con • Slow • Expensive

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Lithography Pattern Transmission • Four types of radiation to convey pattern to resist 1.Light • Visible • Ultraviolet

2.Ion 3.X-ray (does not apply to direct write) 4.Electron

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Lithographic Printing • Contact printing • Proximity printing • Projection printing – Refraction projection printing – Reflection projection printing – Catadioptric projection printing

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Contact and Proximity Printing • Contact printing – 0.05 atm < pressure < 0.30 atm

• Proximity printing – 20 µm < mask-wafer separation < 50 µm – Pro • Low cost • Mask lasts longer because no contact

– Con • Inferior resolution cmpe222_03process_ppt.ppt

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Projection Printing • Projection printing – Higher resolution than proximity printing

• Numerical Aperture – It was once believed that a high NA is always better. – If NA too low, can't achieve resolution – If NA too high, can't achieve depth of field 2 • DOF = lambda/(2 NA ) cmpe222_03process_ppt.ppt

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Refraction Projection Printing • High resolution • To transmit deep UV, optical components are – Fused silica – Crystalline fluorides • Lenses are fused silica – Chromatic – Source bandwidth must be narrow • KrF laser cmpe222_03process_ppt.ppt

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Reflection and Catadioptric Projection Printing • Reflection projection printing – Polychromatic, larger spectral bandwidth

• Catadioptric projection printing – Combines reflecting and refracting components – Larger spectral bandwidth – More than one optical axis • Aligning optical elements can be very difficult

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Minimum Channel Length and Gate Insulator Thickness Improve Performance 2

• Ids

= Beta(Vgs – Vt) / 2

• Beta

= MOS transistor gain factor = ( (mu)(epsilon) / tox )( W / L )

• mu

= channel carrier mobility

• epsilon = gate insulator permittivity (SiO2) • tox

= gate insulator thickness

• W/L

= channel dimensions cmpe222_03process_ppt.ppt

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Silicon Gate Process, Steps 1 & 2 • Initial patterning SiO2 layer – Called field oxide – Thick layer – Isolates individual transistors

• Thin SiO2 layer – Called gate oxide – Also called thinox – 10 nm < thin oxide < 30 nm

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Silicon Gate Process, Step 3 • Polysilicon layer – Polycrystalline = not single crystal – Formed when Si deposited • Has high R when undoped • Used as high-R resistor in static memory

– Used as • Short interconnect • Gate electrode – Most important: allows precise definition of source and drain electrodes – Deposited undoped on gate insulator – Then doped at same time as source and drain regions cmpe222_03process_ppt.ppt

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Silicon Gate Process, Steps 4 & 5 • Exposed thin oxide, not covered by poly, etched away • Wafer exposed to dopant source by deposition or ion-implantation 1.Forms n-type region in p-type substrate or vice versa • Source and drain created in shadow of gate • Si gate process called self-aligned process 2.Polysilicon doped, reducing its R cmpe222_03process_ppt.ppt

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Silicon Gate Process, Final Steps • • • • •

SiO2 layer Contact holes etched Metal (Al, Cu) evaporated Interconnect etched Repeat for further interconnect layers

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Parasitic MOS transistors • Formed from – Diffusion regions of unrelated transistors • Act as parasitic source and drain

– Thick (tfox) field oxide between transistors overrun by metal or poly interconnect • Act as parasitic gate insulator and • parasitic gate electrode

• Raise threshold voltage of parasitic transistor – Make tfox thick enough – Add “channel-stop” diffusion between transistors cmpe222_03process_ppt.ppt

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Four Main CMOS Processes 1. 2. 3. 4.

n-well process p-well process Twin-tub process Silicon on insulator

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n-well Process, n-Well Mask A • Mask A defines n-well • Also called n-tub • Ion implantation produces shallower wells than deposition – Deeper diffusion also spreads further laterally – Shallower diffusion better for more closely-spaced structures

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n-well Process, Active Mask B, Page 1 • Mask B defines thin oxide • Called active mask, since includes – Area of gate electrode – Area of source and drain

• Also called • • •

thinox thin-oxide island mesa cmpe222_03process_ppt.ppt

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n-well Process, Active Mask B, Page 2 • Thin layer of SiO2 grown • Covered with SiN = Silicon Nitride – Relative permittivity of SiO2 = 3.9 – Relative permittivity of Si3N4 = 7.5 – Relative permittivity of comb. = 6.0

• Used as mask for steps for channel-stop mask C and field oxide step D cmpe222_03process_ppt.ppt

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n-well Process, Channel-Stop Mask C • Channel-stop implant • Raises threshold voltage of parasitic transistors • Uses p-well mask = complement of n-well Mask A – Where no nMOS, dope p-substrate to be p+

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n-well Process, Field Oxide Step D • • • •

Thick layer of SiO2 grown Grows where no SiN Grows where no mask B = no active mask Called LOCOS = LOCal Oxidation of Silicon

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n-well Process, Bird‘s Beak • Just as dopant diffuses laterally as well as vertically: • Field oxide also grows laterally, underneath SiN • Tapering shape called bird’s beak • Causes active area to be smaller – Reduces W

• Some techniques limit this effect – SWAMI = SideWAll Masked Isolation cmpe222_03process_ppt.ppt

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n-well Process, Planarity • • • •

Field oxide higher than gate oxide Conductor thins or breaks Problem called step coverage To fix, pre-etch field oxide areas by 0.5 field oxide depth

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n-well Process, Vt Adjust, After Field Oxide Step D • • • • • • • •

Threshold voltage adjust Optional Uses n-well mask A 0.5 v < Vtn < 0.7 v -2.0 v < Vtp < -1.5 v Add a negatively charged layer at Si-SiO2 Lowers channel Called “buried channel” device cmpe222_03process_ppt.ppt

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n-well Process, Poly Mask E • Mask E defines polysilicon • Poly gate electrode acts as mask for source & drain regions • Called self-aligned

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n-well Process, n+ Mask F • n+ mask defines active areas to be doped n+ – If in p-substrate, n+ becomes nMOS transistor – If in n-well, n+ becomes ohmic contact to n-well

• Also called select mask

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n-well Process, LDD Step G • 1. 2. 3.

LDD = Lightly Doped Drain Shallow n-LDD implant Grow spacer oxide over poly gate Second, heavier n+ implant – Spaced from edge of poly gate

4. Remove spacer oxide from poly gate • More resistant to hot-electron effects

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n-well Process, p+ Mask H • p+ diffusion • Uses complement of n+ mask • p+ mask defines active areas to be doped p+ – If in n-well, p+ becomes pMOS transistor – If in p-substrate, p+ becomes ohmic contact to p-substrate

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n-well Process, SiO2, After p+ Mask H • Entire chip covered with SiO2 • No need for LDD for pMOS – pMOS less susceptible to to hot-electron effects than nMOS

• LDD = Lightly Doped Drain

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n-well Process, Contact Mask I • Defines contact cuts in SiO2 layer • Allows metal to contact – Diffusion regions – Poly gates

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n-well Process, Metal Mask J • Wire it up! • n-well Process, Passivation Step – Protects chip from contaminants • Which can modify circuit behavior

– Etch openings to bond pads for IOs

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p-Well Process • Transistor in native substrate has better characteristics • p-well process has better pMOS than n-well process • nMOS have better gain (beta) than pMOS

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Twin-Tub Process • Separately optimized wells • Balanced performance nMOS & pMOS 1. Start with epitaxial layer •

Protects against latchup

2. Form n-well and p-well tubs

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Silicon-on-Insulator Process • Uses n-islands and p-islands of silicon on an insulator – Sapphire – SiO2

• No n-wells, no p-wells

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SOI Process Advantages • No n-wells, no p-wells – Transistors can be closer together – Higher density

• Lower parasitic substrate capacitance – Faster operation

• No latchup • No body effect • Enhanced radiation tolerance cmpe222_03process_ppt.ppt

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