Decoupling controller design for Z-source inverter

IET Power Electronics Research Article

Decoupling controller design for Z-source inverter

ISSN 1755-4535 Received on 19th March 2014 Accepted on 7th October 2014 doi: 10.1049/iet-pel.2014.0207 www.ietdl.org

Kai-Ming Tsang ✉, Wai-Lok Chan Department of Electrical Engineering, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong ✉ E-mail: [email protected]

Abstract: With the state-space averaging model and the proposed pulse-width modulation switching scheme, the Z-source inverter has been decoupled into a primary boosting stage and a secondary bucking stage. Two double-loop controllers are designed to handle the voltage regulation as well as the current regulation for the DC/DC and DC/AC conversion processes. The proposed scheme demands for two separate duty ratios and novel switching scheme has been derived to realise the combined duty ratios in one switching cycle. Power regulation, harmonics elimination and power factor correction control algorithms have also been derived for the Z-inverter when it is connected to the supply grid. Finally, experimental results are included to demonstrate the effectiveness of the proposed switching and control schemes.

1

Introduction

Renewable energy has attracted great attention in recent years because of the environmental concern. One of the most important components of grid-tied renewable power systems are a DC–AC power inverter [1]. Its main function is to convert the generated DC power to a power grid compatible AC form. Obviously, there is a need to design inverters which can operate efficiently with variable DC voltage sources such as fuel cells [2, 3] and photovoltaic systems [4]. Conventional H-bridge voltage source inverter (VSI) suffers from the drawback that the supply voltage has to be higher than the output voltage [5]. If the supply voltage is lower than the output voltage, a separate boosting stage is always added to the VSI. This cascaded arrangement of two power converters not only increases the complexity of power circuitry and control scheme but also increases the cost and the space requirement. If an impedance source (Z-source) is added to the input of the inverter, the single-stage H-bridge inverter can be converted to a boosting and bucking conversion processes. The Z-source inverter (ZSI) has been proposed [6] to overcome the problems in conventional inverters. ZSI employs a unique impedance network coupled with the inverter main circuit to the variable DC source. The lattice network which consists of two inductors and two capacitors is commonly employed. In this lattice network, two inductors form the series arms inductances and two capacitors form the diagonal capacitances. The impedance network changes the circuit configuration from a voltage source to an impedance source. It allows the VSI to be operated in a new state known as the shoot-through state in which the two switching devices in the same inverter leg are simultaneously switched on so as to generate a short circuit in the DC link. ZSI has the unique feature that it can boost the source voltage by introducing the shoot-through state (which is forbidden in conventional voltage source inverters). The voltage boosting the capability of ZSI is in fact because of the energy transfer from capacitors to inductors during the shoot-through state. As the capacitors may be charged to higher voltages than the input source voltage, a diode is required to prevent discharging through the input source. A ZSI can be used to realize both DC voltage boost and DC–AC inversion in a single stage. With this unique feature, the ZSI provides a cheaper and simpler approach for grid-tied applications. The Z-source concept can also be applied to many power conversion schemes such as DC–AC [7], AC–DC [8], AC–AC [9–11] and DC–DC [12, 13] as well as multilevel converters [14, 15].

The controller design for ZSI is not an easy task. The transfer function of the Z-source impedance has a right-hand-plane zero which cannot be eliminated by adjusting the parameters [16, 17]. This means a non-minimum phase characteristic in the capacitor voltage response, which is known to potentially introduce stability issues in the closed-loop controlled system. Just like single-ended primary-inductor converter converter [18, 19], to handle the non-minimum phase problem of the boosting stage, usually a multi-loop control is employed. To fully carry out the conversion process from the input to the output stage, a closed-loop control system with four loops is required as proposed in this paper. To implement a closed-loop system having four loops, the switching frequency has to be very high to fulfil the requirement for multi-loop controller design. As the ZSI can be decoupled to two conversion processes, two independent double-loop controllers can be designed for the two decoupled processes. As the number of loops for the closed-loop control processes reduces to two, the required sampling and switching frequency can be reduced. Apart from acting as voltage source inverter, the inverter can also be acted as a current source inverter. The proposed scheme demands for two separate duty ratios and novel switching scheme has been derived to realise the combined duty ratios in one switching cycle. Control schemes have also be derived for the ZSI such that it can perform power regulation, harmonics reduction and power factor correction when it is connected to the supply grid. The proposed converter is useful for grid-connected photovoltaic system [20]. Experimental results are included to demonstrate the effectiveness of the proposed switching and control schemes.

2

State-space averaging model for ZSI

Fig. 1 shows a schematic diagram for a symmetrical ZSI. Figs. 2a–d show the four operation modes of the inverter. Assume the inverter is operated in continuous conduction mode and the input capacitor voltage vC(t) is higher than the supply voltage vi (t). The dynamic equations describing the state shoot through state θ are given by 0 = vL (t) − vC (t)

(1)

iL (t) = −iC (t)

(2)

vL (t) = Li˙iL (t)

(3)

Ci v˙ C (t) = iC (t)

(4)

IET Power Electron., 2015, Vol. 8, Iss. 4, pp. 536–545

536

& The Institution of Engineering and Technology 2015

Fig. 1 Z-source inverter

0 = Lo˙io (t) + vo (t)

(5)

vo (t) = Ro io (t)

(6)

where vL(t) is the voltage across the input inductors Li, Ci is the capacitance for the input capacitors, iL(t) and iC(t) are the currents across the input inductors and capacitors, Lo is the output smoothing inductor, io(t) is the output current, Ro is the output loading resistor and vo(t) is the output voltage, respectively. For output state 0, the dynamics can be described as

From (5), (9), (12) and (15), we obtain Lo˙io (t) = d2 (t) 2vC (t) − vi (t) − vo (t)

(18)

Notice that d1(t) + |d2(t)| is set to be less than or equal to 1 and 1 − d1(t) − |d2(t)| is the duty ratio for the output state 0. Fig. 3 shows the timing diagrams for the four switches to realise d1(t) and d2(t) over one switching cycle.

vi (t) = vL (t) + vC (t)

(7)

3

Controller design

ii (t) = iL (t) + iC (t)

(8)

0 = Lo˙io (t) + vo (t)

(9)

As d1(t) and d2(t) can have different values, the ZSI can be decoupled to two conversion processes. The first stage is a DC/DC boosting process and the second stage is a DC/DC or DC/AC bucking process.

where ii (t) is the supply current. For output state 1 3.1 vi (t) = vL (t) + vC (t)

(10)

ii (t) = iL (t) + iC (t)

(11)

vC (t) − vL (t) = Lo˙io (t) + vo (t)

(12)

and finally for output state −1 vi (t) = vL (t) + vC (t)

(13)

ii (t) = iL (t) + iC (t)

(14)

−vC (t) + vL (t) = Lo˙io (t) + vo (t)

(15)

Table 1 shows the switch positions to realised the states θ, 0, 1 and −1. One additional advantage of using the switching Table 1 is that a three-level output can also be realised. If the inverter is operated at fixed switching frequency, d1(t) ≥ 0 is the duty ratio for the state θ and −1 ≤ d2(t) ≤ 1 is the duty ratio for the states −1 or 1. If d2(t) is less than 0, |d2(t)| represents the duty ratio for the state −1. Moreover, if d2(t) is larger than 0, d2(t) represents the duty ratio for the state 1. The state-space averaging model over one switching cycle can be obtained as follows. From (1), (3), (7), (10) and (13), we obtain Li˙iL (t) = d1 (t) 2vC (t) − vi (t) + vi (t) − vC (t)

(16)

From (2), (4), (8), (11) and (14), we obtain Ci v˙ C (t) = 1 − d1 (t) ii (t) − iL (t)

IET Power Electron., 2015, Vol. 8, Iss. 4, pp. 536–545 & The Institution of Engineering and Technology 2015

(17)

Primary DC/DC conversion stage

Consider (16) and assume that a steady state can be reached such that the input voltage vi (t) and capacitor voltage vC(t) can be regarded as constant. Equation (16) can be approximated as Li˙iL (t) = d1 (t)(2UC − Ui ) + Ui − UC

(19)

where Ui and UC are the steady-state values of the input and capacitor voltages, respectively. If d1(t) is taken as the control input and the inductor current iL(t) as the control variable, a simple proportional–integral (PI) controller of the form G1 (s) =

KP1 s + KI1 s

(20)

can be designed for (19) as shown in Fig. 4a. The purpose of including a PI controller in the closed-loop process is to eliminate the effects of Ui ad UC on the inductor current iL(t). Although other advanced control methods [21] could be used, PI controller is employed in this paper because the bandwidth of the control loop can easily be set. The closed-loop characteristic equation for the block diagram shown in Fig. 4a is given by D1 (s) = Li s2 + KP1 (2UC − Ui )s + KI1 (2UC − Ui )

(21)

The undamped natural frequency of this primary current control loop is given by KI1 (2UC − Ui ) v1 = Li

(22)

537

Fig. 2 Operation modes of the ZSI a State θ b State 0 c State 1 d State −1


538


Table 1 Switching table for ZSI State

θ θ 0 0 1 −1

be approximated as Switch position

S1

S′1

S2

S′2

on off on off on off

on off off on off on

off on on off off on

off on off on on off

Ci v˙ C (t) = (1 − D1 )ii (t) − iL (t)

On top of the primary current control loop, an outer voltage control loop is design for (24). Taking iL(t) as the control input and the vC(t) as the control variable, a PI controller G2 (s) =

and the damping ratio is

z1 =

KP1 (2UC − Ui ) 2v1 Li

(23)

With a given damping ratio and undamped natural frequency, the required controller settings KP1 and KI1 can easily be obtained from (22) and (23). The aim of the first stage DC/DC conversion process is to regulate the capacitor voltage vC(t). Consider (17) and assume a steady state has been reached with a steady-state duty ratio D1. Equation (17) can

(24)

KP2 s + KI2 s

(25)

can be designed for (24) as shown in Fig. 4b. The output from the controller G2(s) will be taken as the reference inductor current for the primary current control loop. The closed-loop characteristic equation for the block diagram shown in Fig. 4b is given by D2 (s) = Ci s2 + KP2 s + KI2

(26)

The controller settings can be obtained based on the specifications on the undamped natural frequency and damping ratio for the voltage control loop because the undamped natural frequency of this

Fig. 3 Timing diagram to realise positive and negative d2(t) a d2(t) > 0 b d2(t) < 0


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3.2

Secondary conversion stage

For the output conversion stage, DC/DC and DC/AC conversions can both be achieved depending on the sign of the duty ratio d2(t). If d2(t) is restricted to either positive or negative value, only DC/ DC conversion can be done. If d2(t) is allowed to have both positive and negative values, DC/AC conversion can be carried out. Consider (18) and assume the dynamics of io(t) is much faster than vo(t) and a steady state can be reached such that vi (t) and vC(t) can be regarded as constant. If d2(t) is taken as the control input and the inductor current io(t) as the control variable, a PI controller of the form G3 (s) =

KP3 s + KI3 s

(29)

can be designed for (18) as shown in Fig. 4c. If the dynamics of io(t) is much faster than vo(t), vo(t) can be treated as constant disturbance and its effect on the current io(t) can largely be reduced by the integral action of the PI controller. The closed-loop characteristic equation for the block diagram shown in Fig. 4c is given by D3 (s) = Lo s2 + KP3 (2UC − Ui )s + KI3 (2UC − Ui )

(30)

The undamped natural frequency of this secondary current control loop is given by KI3 (2UC − Ui ) v3 = Lo

(31)

and the damping ratio

z3 =

KP3 (2UC − Ui ) 2v3 Lo

(32)

Finally, consider (6) and take the output current io(t) as the control input. An integral controller Fig. 4 Block diagrams for the primary and secondary voltage and current control loops a Primary current control loop b Primary voltage control loop c Secondary current control loop d Secondary voltage control loop

G4 (s) =

KI4 s

(33)

can be designed for the control of the output voltage vo(t) as shown in Fig. 4d. The closed-loop transfer function becomes Vo (s) KI4 Ro = Vor (s) s + KI4 Ro

primary voltage control loop is given by

v2 =

KI2 Ci

(27)

where Vor(s) and Vo(s) are the Laplace transform of the reference output voltage and output voltage, respectively. The bandwidth of (34) is given by

v4 = KI4 Ro

and the damping ratio

z2 =

KP2 2v2 Ci

(28)

At the steady state, the disturbance (1–D1)ii (t) shown in Fig. 4b will compose of DC offset and high-frequency components caused by the switching actions. The DC offset can easily be removed by the PI controller while the high-frequency components will be substantially attenuated by the closed-loop process if the closed-loop bandwidth of the voltage control loop is very much lower than the switching frequency. The output from the PI controller G2(s) will be treated as the reference current for the primary current control loop. The cascaded controlled process can function properly provided the dynamics of iL(t) is at least four times faster than vC(t). The dynamics of iL(t) and vC(t) can easily be set using (22) and (27).

(34)

(35)

The output from the PI controller G4(s) will be treated as the reference output current for the secondary current control loop. The cascaded controlled process can function properly provided the dynamics of io(t) is at least four times faster than vo(t). The dynamics of io(t) and vo(t) can easily be set using (31) and (35). 3.3

DC reference voltage setting

The setting for the reference DC bus voltage Ur is very important for the correct execution of the conversion process. The ideal steady-state conversion ratio between vi (t) and vC(t) from (16) is given by UC 1 − D1 = Ui 1 − 2D1

(36)


540


where UC, Ui and D1 are the steady-state value of the capacitor voltage, input voltage and duty ratio, respectively. For the output stage, the ideal steady-state conversion ratio between vC(t), vi (t) and vo(t) from (18) is given by Uo = D2 (2UC − Ui )

(37) 4.1

where Uo and D2 are the steady-state value of the output voltage and duty ratio, respectively. The restrictions on d1(t) and d2(t) are 0 ≤ d1 (t) ≤ 1 −1 ≤ d2 (t) ≤ 1 d (t) + d (t) ≤ 1 1

(38)

2

If the input voltage vi (t) is very low, the required conversion ratio has to be very large in order to meet the output requirement. As D1 approaches 0.5, from (36), the conversion ratio approaches infinity. If d1(t) is restricted to 0 ≤ d1 (t) ≤ 0.5

(40)

From (40), the largest magnitude of d2(t) is 0.5. And from (37), the smallest reference voltage for vC(t) to provide an output Uo is Uo. Hence the reference bus voltage Ur can be set to the required peak output voltage. In actual practice, the reference bus voltage Ur can be set to a value slightly higher than the required peak output voltage to allow for voltage drop during the conversion process and the restrictions on d1(t) and d2(t) are 0 ≤ d1 (t) ≤ 0.5 d (t) ≤ 1 − d (t) 2 1

4

(41)

The usual tasks for the current source inverter to perform is either (i) the inverter output current io(t) to be in phase with the supply grid voltage vs(t) or (ii) the inverter output current io(t) will generate components to reduce the higher harmonics in the supply grid current is(t). If the inverter output current io(t) is commanded to produce current, which is in phase with the supply grid voltage and a steady-state has been reached for the primary stage, the output controller can take the form d2 (t) = KP3 eio (t) + KI4 eio (t) +

vs (t) 2UC − Ui

(45)

where eio(t) = ior(t)–io(t) is the output current error and ior(t) is the reference inverter output current. The required inverter output current ior(t) can be derived from the supply grid voltage as ior (t) =

vs (t) i vrms orms

(46)

where vrms is the root-mean-square (rms) value of the supply grid voltage and iorms is the rms value of the inverter output current. Fig. 6a shows the block diagram of the output current control loop. If the inverter output current io(t) is commanded to reduce the higher harmonics in the supply grid current is(t) and a steady-state has been reached for the primary stage, the output controller can also take the form d2 (t) = KP3 eio (t) + KI4 eio (t) +

vs (t) 2UC − Ui

(47)

The required supply grid current isr(t) can be derived from the supply grid voltage as

Current source inverter

The ZSI can also act as a current source inverter. If the inverter is connected to the supply grid as shown in Fig. 5, the inverter can perform power regulation and current shaping for the supply grid. The state-space averaging model over one switching cycle is very similar to (16)–(18) and they are given by Li˙iL (t) = d1 (t) 2vC (t) − vi (t) + vi (t) − vC (t) Ci v˙ C (t) = 1 − d1 (t) ii (t) − iL (t) Lo˙io (t) = d2 (t) 2vC (t) − vi (t) − vs (t)

Output current shaping

(39)

any reference bus voltage Ur can be achieved. If d1(t) is equal to 0.5, from (38) the available duty ratio for d2(t) to manoeuver is −0.5 ≤ d2 (t) ≤ 0.5

The only different is that the output voltage vo(t) in (18) becomes the supply grid voltage vs(t). As there is no change on the primary stage of the inverter, the controllers (20) and (25) for the primary DC/DC conversion stage remain unchanged.

(42) (43) (44)

isr (t) =

vs (t) i vrms srms

(48)

where isrms is the rms value of the supply grid current. Fig. 6b shows the block diagram of the output current control loop and indicates that the load current iLoad(t) and the inverter output current io(t) are both required in order to carry out the supply grid current regulation. If the supply grid current is(t) is taken as the feedback signal, only one measurement for the current is required to carry output the supply grid current regulation. Fig. 6c shows the

Fig. 5 ZSI with coupled inductor


541

capacitors used were Ci = 1000 μF. The switching frequency for the pulse-width modulation (PWM) was set to 30 kHz. An industrial PC was used to sample all required variables and to implement the control loops. The sampling frequency was set to 10 kHz and the supply voltage vi (t) was set to 250 V. For 220 Vrms, the required output peak voltage was 311.1 V. Hence the reference capacitor voltage was set to 330 V which was slightly higher than the required peak output voltage. The bandwidth of

Fig. 6 Output current control block diagrams a Inverter output current in phase with the supply grid voltage b Supply grid current in phase and of the same shape as the supply grid voltage c Supply grid current in phase and of the same shape as the supply grid voltage

modified control block diagram. The control law becomes d2 (t) = KP3 eis (t) + KI4 eis (t) +

vs (t) 2UC − Ui

(49)

where eis(t) = is(t)–isr(t) is the error for the supply grid current and the load current iLoad(t) can be treated as the output disturbance. The loop dynamics of Figs. 6a–c are exactly the same as Fig. 4c, the controller (29) remains unchanged.

5

Experimental and results

To demonstrate the effectiveness of the proposed switching and control schemes, an experimental setup was built and power metal–oxide–semiconductor field-effect transistors, SiHP22N60S, was used to realise the switches of the inverter. A rated output of 10 A 50 Hz 220 Vrms was synthesised using the ZSI. The inductors were chosen as Li = 200 μH, Lo = 500 μH and the Table 2 Experimental setup for ZSI output voltage Z-source output smoothing inductor output load switching frequency sampling frequency primary DC/DC stage secondary DC/AC stage

capacitor Ci inductor Li inductor Lo resistor Ro current loop bandwidth voltage loop bandwidth current loop bandwidth voltage loop bandwidth

220 Vrms/50 Hz 1000 μF 200 μH 500 μH 22 Ω 30 kHz 10 kHz 250 Hz 1 Hz 2000 Hz 500 Hz

Fig. 7 Gate signals, bus capacitor voltage, input inductor current, output voltage and output current a Gate signals b Gate signals, output voltage and output current c Bus capacitor voltage, input inductor current, output voltage and output current


542


the primary current control loop was set to 250 Hz such that it could cope with the 50 Hz output requirement. The damping ratio was set to 1. From (22) and (23), the required controller became

G1 (s) =

0.0015s + 1.2036 s

(50)

For the primary voltage control loop, the bandwidth was set to 1 Hz such that the 50 Hz signal and its higher harmonics would be substantially attenuated by the voltage loop dynamics. The damping ratio was set to 1. From (27) and (28), the required PI controller was given by G2 (s) =

0.0126s + .0395 s

(51)

For the secondary current control loop, the bandwidth was set to 2000 Hz such that it was much higher than the 50 Hz signal and the damping ratio was also set to 1. From (31) and (32), the required PI controller became G3 (3) =

0.0306s + 192.58 s

(52)

The bandwidth for the output voltage control loop was set to 500 Hz such that it was much higher than the 50 Hz signal but four times less than the output current control loop. For rated load, from (35) G4 (s) =

142.80 s

(53)

Table 2 summarised the experimental setup. To test the tracking performance of the closed-loop control scheme and the effectiveness of the PWM switching scheme, a 50 Hz 200 V

Fig. 8 Gate signals, bus capacitor voltage, input inductor current, output voltage and output current a Gate signals b Gate signals, output voltage and output current c Bus capacitor voltage, input inductor current, output voltage and output current


Fig. 9 Gate signals, bus capacitor voltage, input inductor current, output voltage and output current a Gate signals b Bus capacitor voltage, input inductor current, output voltage and output current

543

square wave was synthesised using the proposed control scheme. Figs. 7a–c show the gating signals for the four switches, input inductor current, capacitor bus voltage, output current and output voltage. The capacitor bus voltage was well regulated at 330 V and the output voltage tracked the 50 Hz 200 V square wave very well because the output voltage settled in about 2 ms. The

steady-state output was at about ±200 V. Figs. 8a–c show the gating signals, input inductor current, capacitor bus voltage, output current and output voltage when a 50 Hz 220 Vrms sinusoidal signal was synthesised. Again the capacitor bus voltage and the 50 Hz sinusoidal signal were well tracked. Figs. 9a and b show the gating signals for the four switches, input inductor current, capacitor bus voltage, output current and output voltage when the input voltage was increased to 350 V for the tracking of a 50 Hz 220 Vrms signal. As the reference bus voltage was lower than the input voltage, no boosting was required. The primary control loop set d1(t) to 0 as indicated by the gating signals shown in Fig. 9a where S1 was fully on and S′1 was fully off during the positive half cycle of the synthesised signal while S2 was fully on and S′2 was fully off during the negative half cycle of the synthesised signal. To demonstrate the current tracking capability of the switching scheme and control laws proposed in (45) and (49), the ZSI was connected in parallel with the supply grid and the connected output was an inductive load. Fig. 10 shows the supply grid voltage and current when the inverter was not in action. Figs. 11a and b show the performance of the control scheme (45) when the inverter output was commanded to deliver 5 Arms and 10 Arms in-phase current to the grid voltage. Clearly, the inverter output current was in-phase with the grid voltage. When the inverter output current was added to the grid, the supply grid current was reduced. Figs. 12a and b show the performance of the control scheme (49) when the grid current was commanded to deliver 5 Arms and 10 Arms in-phase current to the load. Apart from some high-frequency oscillations, the supply grid current was in-phase

Fig. 11 Performance of the current source inverter

Fig. 12 Performance of the current source inverter

a Inverter output current = 5 Arms b Inverter output current = 10 Arms

a Grid supply current = 5 Arms b Grid supply current = 10 Arms

Fig. 10 Supply grid voltage and current for inductive load


544


and of the same shape as the grid voltage. Some of the higher harmonics had been reduced by the inverter output current. In adjusting the rms value of the reference inverter output current, power regulation on the supply grid could be achieved. In adjusting the rms value of the reference grid current, power regulation, harmonics reduction and power factor correction could all be achieved.

6

Conclusions

The primary DC/DC conversion stage and the secondary DC/AC conversion of a ZSI have been successfully decoupled using the proposed PWM switching and control schemes. The capacitor bus voltage and the inverter output voltage can be independently controlled by two different duty ratios. With the proposed switching scheme, the two independent duty ratios can be realised in one switching cycle. When the ZSI is connected to the grid supply, power regulation, harmonics reduction and power factor correction can also be achieved in adjusting the rms value of the reference inverter output current or reference grid current.

7

Acknowledgments

The authors gratefully acknowledge the support of the Hong Kong Polytechnic University.

8

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