Design and Implementation of a Low-Phase- Noise

Design and Implementation of a Low-PhaseNoise Integrated CMOS Frequency Synthesizer for High-Sensitivity Narrow-Band FM Transceivers Marianne M. KAMAL, Emad W. EL-SHEWEKH, and Muhammad H. EL-SABA, A.O.I.E, [email protected]

Abstract--Frequency Synthesizers (FS) are used in a wide range of RF applications. The narrow-band FM transceivers are usually used in mobile communication networks e.g. (AMPS) and public safety applications, which employ a huge number of channels in a limited bandwidth. In such applications, it is required to have a stable local oscillator (LO) signal with minimum phase noise, in order to avoid the channel interference. In this paper we present a design of a low-power low-noise integrated FS, which can be used for such applications. The circuit is capable of digitally selecting one out of 400 channels, which are closely spaced by narrow windows (25 kHz). The FS circuit is based on the charge pump phase-locked-loop (PLL) architecture. In order to cope with switching phase noise problems, we employ a programmable dual modulus divider (DMD) with a differential input prescaler and a low phase-noise LC tunable voltage controlled oscillator (VCO). We also make use of a dead-zone free phase frequency detector (PFD) with output charge pump (CP) and a third order passive loop filter. The FS is fully integrated using 0.8-micron CMOS technology on a single chip operating at 3.3V. Being designed for narrow-band FM transceivers (operating at about 100 MHz), the single coil used in the VCO and the loop filter are placed off chip, for high-Q considerations. The integrated FS occupies 1mm2 area and consumes only 6mW. The phase noise is about -95 dBc /Hz at 25 kHz, and - 122 dBc /Hz at 100 kHz.

ratio (SNR) of the transceiver. On the other hand, the FS is an analog/mixed signal (AMS) device, in which the analog (VCO) circuit performance is greatly affected by the noise produced by the digital (divider and PFD) circuits. Hence, one of the main requirements of the FS is to generate low phase noise and low-spur signals, while achieving fast settling time when it is hopping from a certain frequency to another. The settling time is largely determined by the loop bandwidth. In this work, we present a low phase noise integrated FS, which is suitable for narrow-band FM applications. The paper is organized as follows; the second section discusses the FS architecture and operation. Section 3 recapitulates the system specifications. In section 4 we present the system analysis and design methodology. In section 5 we present the design issues of each building block. In sections 6, 7 we demonstrate the pre- layout simulation results and the layout of the integrated FS. The post-layout simulation results are illustrated in section 8. Finally, we present our conclusions in section 9.

Index Terms--Integrated Frequency Synthesizer, Low phase noise, Narrow-Band, High sensitivity FM Transceivers.

I. INTRODUCTION IN RF receivers, Fig. 1, the down- conversion of the modulated RF signal, needs a stable VCO to generate the LO signal, for channel selection. The FS is a sort of programmable VCO that generates various LO signals, from a common reference oscillator (usually a crystal oscillator). The narrow-band FM transceivers usually utilize a large number of channels stuffed in a limited bandwidth, which makes the channel selection a tedious job. Unfortunately, all known VCO's have built-in phase noise spectrum, which makes the LO energy to spread over the nearby channels and this limits the signal to noise

Fig. 1. Block diagram of a receiver front-end

II. ARCHITECTURE AND OPERATION The architecture used in this paper is sometimes called the charge-pump PLL (CPPLL) synthesizer. Fig. 2 depicts the

general block diagram of this architecture. This architecture is suitable for integrated circuit for the following reasons: the PFD in this architecture allows the PLL to have a pull-in range that is only limited by the VCO tuning range. The static phase error is zero between the input reference signal and the feedback signal even if the reference signal is not equal to the center frequency of the VCO. The CPPLL also exhibits high immunity to power supply variations. The charge-pump PLL is a digital PLL that uses a charge pump as the output of the PFD. The PFD compares the input reference signal and the feedback signal to produce two control signals up and down. Fig. 3. Schematic of the frequency spectrum of a signal with phase noise

Fig. 2. The frequency Synthesizer block diagram.

These control signals control how much error current flows into the loop filter. The loop filter minimum configuration consists of one capacitor in series with a resistor R. The CP current charges and discharges the loop filter to produce the VCO control voltage, via the loop filter. The VCO signal is then divided in frequency and fed back to the phase/frequency detector. III.

SYSTEM SPECIFICATIONS

The frequency synthesizer has to generate signals with frequencies from 71.7 MHz to 81.7 MHz with steps of 25 kHz. A. Loop Bandwidth The design of the loop bandwidth involves compromising between stability and noise performance. The loop bandwidth should be less than 1/10 of the reference frequency; therefore it should be less than 2.5 kHz. B. Phase Noise It is well known that the frequency spectrum of an oscillator with jitter consists of impulses with side skirts of energy as shown in Fig. 3. These skirts are known as phase noise.

The phase noise corrupts both the unconverted and downconverted signals. When the desired signal and a nearby interferer are mixed with non-ideal LO signal, the tail of the interferer spectrum corrupts the down-converted signal in the band of interest and thus reduces the signal to noise ratio (SNR). The degradation in the SNR of the system and reciprocal mixing effect are discussed in details in the system analysis section. The synthesizer can be designed in such a way to minimize the phase noise of the output signal. Generally, the dominant sources of phase noise are from a noisy reference signal or from a noisy oscillator. Also other PLL non-idealities, such as phase-detector dead zone and power supply fluctuations can contribute to phase noise. The way the frequency synthesizer is designed depends on what is the dominant source of noise in the loop. The phase noise was chosen to be -70 dBc /Hz at least. This value was chosen according to the calculations performed in the system analysis as will be discussed later. C. Switching Time In the switching time, we use the following rule: ∙Switching time = 50 / fref Where fref is the reference frequency. The switching time is hence equal to 2ms. D. DMD division ratios We make use of a two-stage DMD. The divide ratios of the utilized feedback dividers are Nmin= 2868 and Nmax= 3268. E. Reference Division Ratio A crystal of 1MHz was used with the frequency synthesizer. Since the reference frequency is 25 kHz a "reference divider" was placed after the crystal oscillator. The divider ratio equals 1 MHz / 25 kHz = 40. F. Spurious Frequencies Typical systems require that all sidebands be about 60 to 70 dB below the carrier.

IV. SYNTHESIZER SYSTEM ANALYSIS The designers of PLL-based synthesizers usually face tradeoffs related to the resolution, convergence speed, power consumption and phase noise of the synthesizer. The role of system analysis is to-trade off between different design issues such that the whole FS performance is optimized. The basic factor that limits the performance of the synthesizer is the low sampling rate of the phase difference. This sampling rate is dependent upon the frequency step of the synthesizer. Architectures like the Fractional-N techniques increase the sampling rate, but at the same time they introduce significant phase noise. In the following sections, we describe the adopted design methodology that significantly enhances the performance of the synthesizer. A. Design Methodology The design methodology, which we followed out in our design of the FS, is a combination of top-down and down-top scenarios. It can be summarized in the following steps [6]: 1) Determine VCO Tuning Range. The maximum and minimum output frequencies of the VCO determine the tuning range of the frequency synthesizer. As previously mentioned the maximum and minimum frequencies are 71.7 MHz and 81.7 MHz respectively so the tuning range is determined as 10 MHz. 2) Determine the loop division ratio. The loop division ratio range is the range that the programmable divider in the feedback path is operating. This is largely determined by the synthesizer frequency resolution Δƒ. Here, we choose Δƒ equal to the channel spacing 25kHz. Therefore the division ratios (Nmin, Nmax) are determined from the following formula: Nmin = fmin/ Δƒ, Nmax= fmax / Δƒ, where fmin and fmax are the minimum and maximum values of the VCO output frequency, respectively. So, we have: Nmin= 71.7 MHz/ 25KHz = 2868 and Nmax= 81.7 MHz/25KHz = 3268. The geometric mean Nmean= ( N min × N max ) = 3061 was used in defining other PLL parameters. 3) Determine the Damping Factor. The "damping factor (η)," has an effect on the speed and stability of the system. As a compromise between speed and stability, η is optimally set to the value of 0.707. 4) Determine Natural Frequency. The "natural frequency (ωn)," has a significant effect on the loop bandwidth. For a CPPLL with a passive loop filter, the "loop bandwidth (ω3dB)", is related to the natural frequency by the following equation:

w 3db = w n ( 2h 2 + 1 + ((2h 2 + 1) 2 + 1))

(1)

So, when η = 0.707 is assumed we'll have: ω3dB = 2.06 ωn. It is desirable to make the loop bandwidth less then 1/10 of the input reference frequency (25 kHz) in order to avoid the continuous time approximations of the charge pump synthesizer breaking down. However, it is desirable to make the loop bandwidth as wide as possible in order to suppress the VCO phase noise that is the dominant source of phase noise

for the integrated synthesizers. In order to compromise between stability and noise performance, the loop bandwidth is set to: ω3dB = (ωref /10)* 0.75 = 11.781 krad/s. This results in a natural frequency equal to: ωn = ω3dB /2.06 = 5.7 krad/s. 5) Determine VCO Gain. The charge pump will no longer behave ideally if the VCO control voltage rises too high or falls too low. Therefore, the VCO control voltage is limited to VDsat from the supply rails. With a power supply of 3.3V, a VCO control range of 2.2V can be assumed with a sufficient margin for process variations. This results in the following VCO gain: Kvco= 2π (71.7 81.7MHz) / 2.2= 28.6 Mrad/sV. 6) Determine Charge Pump Current and Loop Filter Capacitor. Fig.4 depicts a part of the utilized loop filter. The loop filter capacitor, C1, and the charge pump current, I, are related to the natural frequency, the loop division factor, and the VCO gain by the relation: (2) C1=(I. Kvco) / (2π.Nmean.ωn2)

Fig. 4. The Loop Filter circuit.

It is desirable to have a high charge pump current because it results in a higher loop gain and thus a more stable system. However, having a large charge pump current will result in a large capacitor. We choose I = 25 µA and C1 = 1.14 nF. 7) Determine Loop Filter Components. The loop filter resistor is used to set the "damping factor (η)," according to the following equation: R= 2 η / ω n. C1. With η= 0.707, ωn= 5.7 krad/s, C1= 1.1nF, R= 225K. The second loop filter capacitor, C2, used to suppress ripple in the control voltage is fixed to be less than a tenth of the main loop filter capacitor C1 so that the loop can still be considered a second order system. As C2 < C1/10= 0.11nF, so a value of 100 pF was chosen for C2. B. System Analysis The system analysis helps us to determine the impairment of the synthesizer on the whole receiver performance and determining the specifications of each block of the FS. 1) Phase Noise and its Effects In a receiver, the spurious tones and phase noise of the frequency synthesizer can mix with the undesired signal and

produce noise in the desired channel as shown in Fig.5. This noise reduces the sensitivity of the receiver and degrades its selectivity [4].

signal and the interfere are mixed with non-ideal LO, the tail of interfering spectra corrupts the converted signal and thus reduces the SNR. This effect is called the reciprocal mixing [4]. The reciprocal mixing effect is shown in Fig. 6.

Fig. 6. Reciprocal Mixing. Fig. 5. Effect of Phase Noise tones on a receiver.

2) Limit of the SNR in FM Systems The phase noise (PN) of a LO limits the maximum SNR that can be achieved by the receiver [4], according to the following relation: SNR=Ps/Pn

(3)

For a signal having 5kHz frequency deviation. The modulating power contained in the signal is the square of this value: Ps(5kHz)=2.5×107Hz2

(4)

The noise power in the FM demodulator output is the square of the incidental frequency modulation. Pn=βƒ2

(5)

The incidental frequency modulation βƒ may be found from the following equation: fb

b f = ( 2 × ò (Df 2 × £ ( f ) df ))

(6)

The receiver noise floor in a one-Hertz bandwidth is the sum of the receiver's noise figure, F, in dB and -174 dBm/Hz, Pn=F-174 (dBm/Hz)

(7)

The noise generated in the receiver from a nearby carrier is the sum of the carrier power; Pc, in dBm and the SSB phase noise of the local oscillator at an offset frequency equal to the difference between the carrier frequency and the frequency to which the receiver is tuned. Po=Pc+£(f) (dBm/Hz)

(8)

The apparent noise floor of the receiver is the sum of these two powers. For Receiver noise figure F= 12dB and 1µV input signal i.e. Pc = -107 dBm, we have: Pn = F - 174 = 12 - 174 = -162 dB Po = -107 - 56.3 = -163.3 dBm/Hz So, the apparent noise floor = -159 dB. The equivalent noise figure Feq of the receiver is the difference between the apparent noise floor and -174 dBm/Hz, Feq = 174 -159.5 =14.5 dB. So, the receiver noise figure (F), is increased 2.5dB when it is tuned 10 kHz off the –107 dBm carrier. For F=12dB the phase noise at this offset is equal to – 70 dBc/Hz.

fa

This is a measure of the RMS frequency instability over a band of offset frequencies and £(f) is the phase noise, Δƒ 2 is the frequency offset, fa and fb are the modulation bandwidth limits. For SNR= 12dB, Ps= 2.5x10 7 Hz2 and signal bandwidth = 10 KHz, we have: Pn = 6.2 dB and βƒ = 3.07 dB. Substituting in “(6),” results in a phase noise £(f) = -56.3 dBc/Hz. 3) Channel Blockers &Reciprocal Mixing In wireless applications, out-of-band signals or blockers (Vb) can be much larger than in-band ones (Vd). In order to get rid of such nuisance, the SNR has to be increased by a headroom factor HR = (1+ (Vb/Vd) 2). In addition, when the desired

V. SUBSYSTEM DESIGN In the above design procedure we defined the system-level parameters required for the FS design. In the following subsections we discuss the design of each building block of the frequency synthesizer and its design key issues. A. The PFD and the CP The charge pump (CP) is responsible for stabilizing the spurious current fluctuation of the PFD and hence to minimize the spurs in the VCO input. The charge pump forces current into/out the loop filter when the up/down signal is high. This makes the control voltage of the VCO to rise or fall, in such the manner that the VCO is precisely tuned to the desired

frequency. The CP also helps to reduce the FS switching time, when it hops from one frequency to another. The main criterion in designing the PFD and CP is to minimize the spurious frequency components and the phase noise. The factors responsible for increasing phase noise and spurious tones are: dead-zones in PFD/CP combination and the charge pump charging-discharging current mismatch. To avoid a dead zone region, which usually occurs, when the reference and the VCO feedback signal are near their lock state, an appropriate delayed reset is used. Fig. 7 shows the block diagram of PFD with the delay and reset elements.

filter schematic is shown in Fig. 9.

Fig. 9. Third order Loop filter circuit.

The circuit comprises a second order filter section and an RC section providing an extra pole to assist the attenuation of the sidebands at multiples of the comparison frequency. The values of R1, C1 and C2 were previously determined, the values for R2 and C3 are calculated as follows: R2=3R1, C3= (R1.C2) /(20 R2).

Fig. 7. Dead Zone free PFD.

C. Voltage Controlled Oscillator (VCO) The most common integrated VCO used in RF systems is the LC oscillator because of its superior phase noise performance. A fully differential negative-gm cross-coupled CMOS VCO, which is LC tuned, VCO was implemented using only one coil as shown in Fig. 10.

The value of the charge pump current determines the phase detector gain, KPD by the following: KPD = I/2 π A/rad. The charge pump model is shown in Fig. 8.

Fig. 8. The Charge Pump model.

B. Loop Filter (LF) In a CPPLL, the natural frequency and the damping factor is set independently by the values of the components used in the loop filter. A LF provides a low-noise control voltage for the VCO. We choose a third order LF for several reasons. The third order LF results in less spurious noise and a decrease in the size of the capacitor C1. The capacitor C1 sets the natural frequency. The resistor R1 sets the damping factor. The loop

Fig.10. The VCO circuit.

The main key parameters in the VCO design are the phase noise £(Δƒ), the power consumption P, and oscillation frequency ƒo and the tuning range. These design dimensions are not always orthogonal. A well-formed cost function is necessary for comparing the relative merits of various designs. The so-called VCO normalized figure of merit (FOM) is given by the following: FOM=[(ƒo./Δƒ)2.(1/£(Δƒ).P))]

(9)

According to the above definition our VCO has an FOM of 187 dB at Δ ƒ= 25 kHz. D. Dual Modulus Divider (DMD) As we stated above, in order to synthesize frequencies (71.7Mhz to 81.7Mhz), the division ratio of the programmable divider is required to change from 2868 to 3268. The DMD architecture was implemented to vary the modulus between these two numbers. The frequency synthesizer with DMD block diagram is shown in Fig. 11.

Fig. 11. DMD architecture.

As shown, the DMD consists of a prescaler (V/V+1) and 2 down counters (/N1 and /N2). The output of these counters is high if the counter content has not reached zero. There are two main considerations in the DMD design for correct operation, namely: counter ratio N1 should be greater or equal to N2. Also, N2 must be less than V. While the /N2 counter is operating (counting down), the prescaler divides by V+1, and the VCO generates N2. (V+1). fref pulses. When the /N2 counter reaches zero, the prescaler divides by V and the VCO generates (N1 -N2).V.fref pulses until the /N1 counter counts to zero. The input frequency of the divider is hence equal to: ƒo = (N1. V + N2) fref. (10)

Fig. (12-a). PFD simulation results.

VI. SIMULATION RESULTS Fig. 12. depicts some of the integrated CPPLL results. As shown in fig. 12-a, the PFD uses the rising edges of the input reference signal (25kHz) and the VCO feedback signal (after the divider) to generate the output UP/DN signals that control the CP. So, the width of the reference and the feedback signals are not influencing its operation. When both UP/DN signals are high, the RESET signal is activated and turns them low.

Fig. (12-b). Charge Pump simulation results.

Fig. (12-f). DMD output waveform.

Fig. (12-c). Loop Filter output.

Fig. (12). Shows the FS pre-layout simulation results. (a) PFD output, (b) Charge Pump output, (c) Loop Filter output, (d) VCO pre-layout output oscillations, (e) The phase noise, measure from 52MHz and (f) Programmable Divider waveform. The results from the charge pump when both the reference and the feedback signals are in phase are shown in figure (12-b). The loop bandwidth and the phase outputs from the LF are shown in figure (12-c). Fig. (12-d, e) shows the VCO output oscillations and the output phase noise in the prelayout simulation. Finally in fig. (12-f) the output waveform from the programmable divider is shown. VII. LAYOUT & PARASITIC EXTRACTION

Fig. (12-d). VCO Pre-layout output oscillations.

Fig. (12-e). VCO Phase noise simulation results.

We used the schematic-driven layout (SDL) tools in ICstation, from Mentor Graphics [5], to transfer schematic connectivity and instances to layout. However, we made use of the automatic layout generation tools for the complex digital parts. Fig. 13 depicts the layout photograph of the FS. Also the pin-out assignment of the FS is indicated in the table below. As shown in fig.13, the supply VDDA of the analog part (VCO) is separated from the supply VDD of the digital blocks (dividers, CP and PFD). In addition, all CMOS transistors are inter-digitized, and ties are placed around each block, as well as the whole FS, for better noise immunity and less interference. The layout parasitic (capacitances) of different layout paths is then extracted, and their lumped values are transferred to the original circuit netlist, with appropriate symbols and scale factors.

Fig. (14-a). VCO Post-layout simulations. Fig. 13. The FS layout. TABLE 1 FS PIN ASSIGNMENT

Name XTAL1,XTAL2

P1 TO P10 VDD GND RESET CP_OUT VCON VDDA

L+,LMIXER+, MIXER-

Description Crystal oscillator Input Channel Selection Digital VDD Ground Reset signal Charge pump output Control voltage Analog VDD off coil chip terminals Mixer input (from VCO)

VIII. POST-LAYOUT RESULTS

Fig. (14-b). VCO post-layout phase noise (offset 10k to 5MHz).

The original circuits, combined with parasitic effects and pads equivalent circuits are simulated again, to verify the behavior of the whole integrated circuit. Fig. 14. depicts some of the post layout simulation results of the integrated frequency synthesizer.

Fig. (14-c). VCO post-layout phase noise (offset 10k to 100k Hz).

achieved by the CPPLL architecture with the two-stage DMD multi-modulus divider. 2. The synthesized frequency has minimum "spurs" at the step Frequency of the Frequency of the synthesizer and phase noise has been reduced over a wide frequency range. 3. The behavior of the loop is constant and does not vary as the synthesized frequency varies. The FS is integrated on a single chip using 0.8 CMOS technology. The chip occupies 1 mm2 total area and consumes 6 mW at 3.3V supply. The phase noise is about –122 dBc/Hz at 100 kHz and -95 dBc/Hz at 25 kHz, which is far beyond the -70 dBc/Hz limits that achieve 12dB SNR. Fig. (14-d). Prescaler output at “MC = 0”.

Table 2 gives a brief summary about the performance of the frequency synthesizer. TABLE 2. PERFORMANCE SUMMARY OF THE FREQUENCY SYNTHESIZER

Parameter VDD Tuning Range Phase Noise Area Power Consumption

Fig. (14-e). Prescaler output at “MC = 1”.

Fig. (14-a) depicts the results of output oscillations from the VCO. The phase noise at different offset frequencies is shown in fig. (14-b, c). The waveform results from the prescaler block are shown in figures (14-d, e). In (14-d) the mode control signal “Mc” is set to be “0” so the prescaler divides by 4, while in (14-e) “Mc” is set by “1” so the Prescaler divides by 5. IX. CONCLUSION We have successfully designed and implemented an integrated PLL-based frequency synthesizer, which is dedicated for narrow-band FM transceivers. The designer of the integrated PLL-based synthesizer must face trade-offs related to the resolution, convergence speed, power and phase noise of the synthesizer. The basic factor that limits the performance of the narrow-band synthesizer is the low sampling rate of the phase difference. This sampling rate is dependent upon the frequency step of the synthesizer (which is equal to the narrow loop bandwidth). Fractional-N techniques increase the sampling rate, but at the same time they introduce significant phase noise. In this paper, we introduced a top-down/ down-top methodology for the design of a narrow-band frequency synthesizer that significantly increases the sampling rate of the phase difference without increasing the phase noise. The complete synthesizer circuit has been simulated, using ELDO RF from Mentor Graphics [5], and our results showed that its performance has been significantly enhanced in the following ways: 1. The settling time of the loop is greatly improved. This is

FOM Technology

Value 3.3 V 10 MHz (71.8 – 81.7 MHz) -95 dBc /Hz @ 25KHz -122 dBc /Hz @ 100 KHz 1 mm2 VCO 3.4 mW Total 6.0 mW 187dB 0.8 µm CMOS

ACKNOWLEDGMENT The authors wish to express their heartfelt acknowledgment to Eng. Muhammad Kamal Abdel Fattah, the Chairman of the Electronic factory at the AOI, for his great support and encouragement. We’d also like to thank Dr. Hazem ElTahawy, the manager of Mentor Graphics Egypt, for his kind cooperation and for accelerating the chip fabrication procedures.

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