Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)
Design and Implementation of SoCWire Codec for Space Applications Nitin Kumar Tiwari1, S. Ravi2, Ram Kumar3, Harish kittur4 VIT University, Vellore, TN, India 1
[email protected]
2
[email protected]
Abstract— Dynamic Partial Reconfiguration (DPR) permits a particular portion of an FPGA to be reconfigured while the remaining part continues to operate. In order to communicate between static(which is running during the whole application runtime and stores all critical interfaces ) and dynamic regions we propose dedicated Network-onChip (NoC) approach called System-on Chip(SoC)Wire .This SoC Wire provides guaranteed system qualification with hot-plug ability, high speed point-to-point connection and support of the adaptive macro-pipeline as compared to the Bus Macros which suffers from more area and power consumptions.In this paper we designed the SoC Wire Codec by using Verilog HDL code.The implementations have been done using XILINX FPGA platform and the functionality of the system is verified using Modelsim simulation and board level ChipScope PRO. The presented SoC Wire Codec design utilizes 13% reduced area and ultimately reducing cost of the design. Keywords- Dynamic Partial Reconfiguration (DPR), Single Event Upset (SEU),Flow Control Token(FCT),SoC Wire.
I. INTRODUCTION A complex system is generally composed of many functional discrete modules connected by communication architecture. In some applications not all of the functional modules need to operate concurrently. An unused module resident in an FPGA wastes power, utilizes resources and increases costs. It would be more sufficient if a functional module could be requested on demand and also could be replaced with an updated function to improve processing. These enhancements are covered by DPR and in-flight reconfigurability. In order to communicate on chip, a suitable communication architecture with high data transfer rates is required [2]. In this paper first we will take a glance at DPR and outlined the suitable FPGA for space applications and their sensitiveness for single event upset[1,2]. Then the limitations of bus based communication
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[email protected] [email protected]
architecture are outlined and in order to overcome those problems the NoC paradigm is introduced. Finally we will design and implement SoCWire Codec and verify it using a tool Xilinx chipscope pro[8]. II. DYNAMIC PARTIAL RECONFIGURATION Partial Reconfiguration (PR) is the ability to reconfigure portions of an FPGA any time after its initial configuration[5].This PR can be categorized into static partial reconfiguration and dynamic partial reconfiguration. The device must be at reset during Static partial reconfiguration in other words the FPGA is not active during the process of reconfiguration.On the other hand DPR permits a predefined portion of the FPGA to be reconfigured while the critical part of the device continues to operate[5]. Benefits of DPR are, it saves space on FPGA, reduces power consumption and takes very less time to change a particular portion of the design. DPR is especially valuable where devices operate in a mission critical environment like space applications’ that cannot be disrupted while some subsystems are being redefined. In this approach the system is distinguished between one entire static region and one or more Partial Reconfigurable Modules (PRMs) in reconfiguration region. The PRMs are bounded in Partial Reconfigurable Regions (PRRs). The static region is the region that manages all the inputs/outputs of the given application, remains stable during whole application runtime and stores all critical interfaces e.g. Processor, interfaces to spacecraft while the PRRs are dynamically configured on the fly. This has the advantage that only the updated module has to be qualified in a delta-qualification step process, not the whole system [1,2]. To communicate any signal from one reconfigurable module to other reconfigurable or fixed module, Xilinx provides unidirectional Bus-Macros which are used as fixed data paths and can connect modules horizontal and vertically.
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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)
bus macros for high data word width drastically increases the area of the system because only 4 bits of inter module communication is possible with single bus macros. For example total 16 bus macros are needed in order to communicate 64 bits of data between two modules[5]. Furthermore there are following disadvantages in these bus structure based system. •
Glitch effects during the dynamic reconfiguration process or radiation induced errors (SEUs) in the communication interface of PRMs can interfere with the system communication architecture and could lead to operational interrupts of the system. Bus based dynamic reconfigurable SoCs do not provide guaranteed system qualification with hot-plug ability, high speed reconfigurable point-to-point connection and support of the adaptive macro-pipeline[4]. No dedicated Bus-Macros are provided by Xilinx to access long lines which lead to manual time consuming routing [4,7]. Performance of these long wires and buses are unpredictable with high power consumption and noise phenomenon [1,2].
Fig.1 Partial Reconfiguration System with Bus Macros
The coding style should insure that the signal must be passed through these Bus Macros[5]. III.
FPGA USED FOR SPACE APPLICATIONS
DPR is supported only on some FPGAs. For example in Xilinx Spartan 3,Virtex II, Virtex II Pro, and Virtex 4.Out of these,The radiation tolerant Virtex-4 Q Pro-V family has the largest gate count and is available for space applications in a highly reliable ceramic package. The internal configurable logic of this is organized in a flexible matrix and includes logic elements like Configurable Logic Blocks (CLB), Block RAM (BRAM) and configurable input/output blocks. Xilinx support the DPR process with the PlanAhead tool. Since These FPGAs are SRAM based therefore their internal configuration memory, D flip-flop, BRAM are sensitive to single event upset (SEU) which are mainly found in space[1,2]. These SEU arise due to cosmic particles colliding with atoms in the atmosphere, creating cascades or showers of neutrons and protons, If this happens in a flip-flop or memory cell, the particle can deposit enough charge to cause the flip-flop or memory cell to change state (bit-flip), corrupting the data being stored. However SEU rates can be reduced by SEU mitigation techniques like scrubbing and triple modular Redundancy(TMR).The scrubbing process corrects the SEU errors but does not prevent a propagation of the error through the system. Therefore mitigation techniques like TMR have to be considered. IV. LIMITATION OF BUS STRUCTURE BASED DYNAMIC RECONFIGURABLE SOC To distribute the signals throughout the device bus structure requires wires.The Virtex family of Xilinx provides these wires in the form of bidirectional, horizontal, vertical long lines that span the full width and height of the device and 3-State buffer horizontal long lines that covers the full width .However the resources of these long lines are very limited, consisting of 24 bidirectional horizontal, vertical and four 3- State buffer long lines per column configuration logic block [2,6]. Also using
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•
• •
In order to overcome these issues we will develop a Network-on-chip (NoC) architecture: System-onChip Wire (SoCWire). V. SYSTEM-ON-CHIP WIRE (SoCWire) SoCWire is a Network-on-Chip (NoC) approach based on the European Space Agency (ESA) Space Wire interface standard to support dynamic reconfigurable System-on-Chip (SoC)[1,2,3]. It has been developed with the objective of providing: a) a robust communication architecture for the critical space environment and b) to support DPR in future space applications. This SoCWire will be used in the solar orbitar which is a proposed Sunobserving satellite, under study by the European Space Agency (ESA).This solar orbiter will perform unprecedented detailed measurements of the inner heliosphere and nascent solar wind, and perform close observations of the polar regions of the Sun. Following are the features of the SoCWire: • • • • • •
High speed data rate. Hot-plug ability. Detection of link errors. Scalable data word width (8-8192) Credit based flow control. Configurable Switch with 2 to 32 ports[1].
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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)
Msb 0 0
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lsb P
Regular packets are completed with an EOP marker. 1
Fig.2 Partial Reconfiguration System with SoCWire Codec.
The concept of SoC Wire is taken from a well known standard called the space wire interface which consists of 4 layered protocol (physical, character, exchange and network) and an accepted interface for space applications. It is a serial link, bidirectional (full-duplex) interface whose performance depends upon jitter and skew [2,4,7]. It includes flow control, hot-plugging, link reinitialization, detecting errors and performs its recovery in hardware. For future space applications we move towards a new approach named SoC Wire where the Space Wire interface has been modified to a parallel data interface . The advantage of this approach is that significantly higher data rates can be achieved. Furthermore a scalable data word width (8-8192) to support medium to very high data rates has been implemented[4,7]. On the other hand the advantageous features of the Space Wire standard including automatic reconnection whenever link is disconnected hot plugging, flow control, error detection are still fully support [4]. Like space wire the SoCWire works in character level, exchange level, packet level and network level .However in Contrast to Space Wire the SoCWire architecture does not require any physical layer. The character level tells about data and control characters . A data character is formed by scalable data bits (range 8- 8192),1 bit of parity, 1 data-control flag. The data-control flag bit helps in differentiating data(0) and control characters(1).
Msb Lsb D D D D D D D D 0 7 6 5 4 3 2 1 0
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EEP marker is exclusively send by the user to indicate an erroneous packet. To this the target can react accordingly and reject the packet. 0
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Escape Character (ESC) is 4 bit code used to form the 8 bit length control code. 0
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Null is formed by the combination of escape and FCT control code (ESC + FCT). 0
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To support the detection of transmission errors an odd parity is assigned to data and control characters. The parity bit covers two bits of control character( parity bit, data-control flag) and the previous eight bits of a data character[2]. 0
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Parity Coverage
Parity bit of the FCT covers the previous two bit of the control character (ESC character) and the data control flag of the FCT. Since all three bits are ‘1’i.e odd numbers of one, so parity bit of FCT will be ‘0’. 0
0
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Parity bit of Fct
VI. DESIGN AND IMPLEMENTATION OF SOC WIRE CODEC P
Data control flag Parity bit
In Soc wire there are four control characters of four bit length and one control code of eight bit length.Flow Control Token (FCT) is used to manage the flow of data across a link, it checks the sufficient space for normal-characters at the receiver end.
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The SoCWire CODEC connects a node or host system to a SoCWire network. It consists of six modules. The transmitter FIFO transmits the data from the host system to the transmitter module. It checks the credit counter to send the appropriate amount of data. The transmitter module codes the received data by assigning the parity bit and creates flow control tokens and Null code in the data flow. The receiver module decodes the data and sends the decoded user data to the receiver FIFO. Link errors are detected in this module only and forwarded to the state machine. The receiver FIFO
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Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011)
receives the user data from the receiver and
transfers to the host interface. A.SYSTEM SIMULATION
Fig.3 SoCWire Codec Architecture
In this paper the verification of the system architecture was done using ModelSim. Figure 4 and 5.demonstrates a simulation result of point-topoint unidirectional and bidirectional communication respectively. Data write, Data read are active low signals. As data write signal is low Codec starts writing data, after every eight data characters one FCT is sent which shows that Codec on the other host system is ready to receive another eight data. The transfer ends with an EOP[3]. As data_read signal is low Codec starts reading data.
Fig.4 Simulated Wave of SoCWire Codec For unidirectional Point-to-Point Communication.
Fig.5 Simulated Wave of SoCWire Codec For bidirectional Point-to-Point Communication.
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Fig.6 Waveforms of the SocWire Codec using a 50 MHz clock obtained from Chipscope Pro.
B. SYSTEM IMPLEMENTATION IN FPGA The implementation of SoCWire CODEC is done in Xilinx Virtex-4 LX60-10 FPGA. For memory implementation Xilinx BLOCK RAMs are chosen. The occupied area (LUTs, FLIP-FLOP, and RAM) of the implemented design for different data width are listed in the table below. Fig. 7 show the relation between data word width and resource utilization. Xilinx ISE 12.3 software is used as implementation environment. Table1.SoCWire Codec Synthesis Report Fig.7 SoCWire Codec Synthesis Report
VII. CONCLUSION
C. BOARD LEVEL VERIFICATION USING CHIPSCOPE PRO The board level verification of the architecture have been done using XILINX Chip Scope Pro [6,8] tool and the results are shown in the Figure 6.
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In this paper the Soc Wire Codec for future space applications has been designed and related issues were discussed. The verification of the design is done using modelsim. Finally, by using ChipScope Pro the proper functionality of the designed systems are observed. The presented SoC Wire Codec design utilizes 13% less area and ultimately cost of the design.This scalable datawidth SoCWire (8-8192) meets all requirements for a high speed reconfigurable architecture. High data rates are achieved with significantly small implementation efforts.
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REFERENCES [1] B. Osterloh, H. Michalik, B. Fiethe, K. Kotarowski. "SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications." In NASA/ESA Conference on Adaptive Hardware and Systems, Volume (AHS-2008), pp 51-56, Noordwijk, June 2008 . [2] B. Osterloh, H. Michalik, and B. Fiethe, "SoCWire: A Robust and Fault Tolerant Networkon-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs," in Architecture of Computing Systems - ARCS 2009. vol. 5455 Delft, Netherlands: Springer Berlin / Heidelberg, 2009, pp. 50-59.
[5] www.eetasia.com/ARTICLES/2002JUN/2002J UN28_AMD_AN01.PDF [6] Xilinx, Virtex-4 Configuration www.xilinx.com, October 2007.
Guide,
[7] Björn Osterloh, Harald Michalik, Sandi Alexander Habinc, Björn Fiethe, “Dynamic Partial Reconfiguration in Space Applications”,In NASA/ESA Conference on Adaptive Hardware and Systems, July 29 -Aug. 1 2009,pp.336-343 [8] Xilinx user manual, [Online]. Available: www.xilinx.com/support/documentation.
[3] ECSS, Space Engineering: SpaceWire–Links, nodes, routers, and networks, ESA-ESTEC, Noordwijk Netherlands, January 2003, ECSS-E-5012A. [4] Yannick Dadji, Björn Osterloh, Harald Michalik,“A Middleware Aided Robust and Fault Tolerant Dynamic Reconfigurable Architecture”, ASME/IFToMM International Conference on Reconfigurable Mechanisms and Robots, 22-24 June 2009, pp 572-579.
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