Design of Cascode Mixer Based on Bulk Injection and

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Journal of Low Power Electronics Vol. 14, 1–8, 2018

Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process for a High Performance Receiver Front End Shasanka Sekhar Rout1 ∗ , S. K. Mohapatra2 , and Kabiraj Sethi1 1

Dept. of Electronics and Telecom. Engineering, VSS University of Technology, Burla 768018, Odisha, India 2 School of Electronics Engineering, KIIT University, Bhubaneswar 751024, Odisha, India (Received: 10 October 2017; Accepted: 3 January 2018)

A proposed cascode mixer is investigated by using bulk injection and switched biasing techniques. This design is implemented in UMC 180 nm CMOS technology with a high conversion gain, low noise figure (NF), improved voltage and power operation. To diminish the voltage drop for low voltage action, the radio frequency (RF) stage is placed on the local oscillator (LO) stage. The bulk injection technique is used for low voltage operation as well as to provide a high conversion gain by modulating the threshold voltage of the LO stage. A switched biasing technique with the help of a dc level shifter is implemented for lowering the noise of the design as compared to a static bias current source. The results demonstrate maximum conversion gain of 14.8 dB at 4 dBm of LO power, NF of 9.4 dB at 100 MHz of intermediate frequency (IF) and power consumption 0.6 mW from a supply voltage of 0.9 V with the input third order intercept point (IIP3) of −9 dBm. The area obtained from the layout of the mixer design is 0.0503 × 0.0347 mm2 . This investigation helps to create an opportunity for designing a high performance receiver front end.

Keywords: Bulk Injection, Cascode, Conversion Gain, Level Shifter, Mixer, Switched Biasing.

1. INTRODUCTION In recent years, low power and low voltage design problems are essential for mobile wireless systems due to the drawback of battery capacity. Moderate performance is needed for the short distance wireless communication standards like Zig Bee application in the frequency range of 2.4 GHz. The receiver front end design based on CMOS technology scaling enhances the operation speed, power utilization and area of integrated circuits (ICs). A RF mixer is a key block in the receiver front end of the wireless system.1 It is a 3 port passive or active frequency conversion device, which changes RF to a lower baseband or IF for undemanding signal processing in receivers with the help of LO signal as exposed in Figure 1. It also changes IF frequency (or baseband signal) to a higher RF or IF frequency for competent transmission in transmitters.2 In CMOS transceivers, the Gilbert type mixers1–3 are broadly used as the down conversion mixers since they have better isolation, good conversion gain ∗

Author to whom correspondence should be addressed. Email: [email protected]

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and high linearity, but with some drawbacks, such as high power consumption and comparatively more supply voltage requirement due to more stacked transistors working in the saturation region. Depending on the CMOS process, more different numbers of advanced technology mixers like bulk driven mixer,4 direct conversion mixer,5 cascode mixer6 and source driven mixer7 are working to shot out these drawbacks. Besides these, the folded mixer8 works at a lower voltage because of the less number of stacked transistors. But in comparison to the Gilbert type mixer, it needs a superior dc current with same consumed power. The bulk injection technique9 10 is implemented to give flat conversion gain and low power consumption with a high NF, which is overcome by switched biasing technique.11 However, it requires high LO power and low port to port isolation.12 Also the current bleeding technique13 is intended to get better mixer noise due to low current passes at the switching stage, but the drawback of parasitic capacitance which increases in between the transconductance stage, the current bleeding circuit and switching stage. The resonating inductors are implemented to remove the

1546-1998/2018/14/001/008

doi:10.1166/jolpe.2018.1527

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Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process

Fig. 1. Mixer symbol.

parasitic capacitance with the drawback of increase in chip area due to the inductors.14 15 In this work, a cascode mixer is reported in which LO stage is stacked by the RF stage to get better low voltage and low power results with improvement in noise presentation by switched biasing technique with the help of dc level shifter based on UMC 180 nm CMOS technology. The bulk injection technique integrates the switching stage with the transconductance stage to formulate a single MOSFET stage, which improves the supply voltage and dc power consumption12 to reduce the cost, volume and weight of the transceivers. The isolation between LO and RF ports is enhanced due to the cascode configuration with high conversion gain and low power consumption by the operation of the mixer transistors in a sub-threshold region.16 17 The proposed design works on 0.9 V supply voltage with the power consumption of 0.6 mW, a conversion gain of 14.8 dB, IIP3 of −9 dBm and NF of 9.4 dB. The proposed design is described with the operating principles of the bulk injection and switched biasing technique with the performance analysis in Section 2. The corresponding simulation results with the comparison based table on different CMOS mixers are discussed in Section 3. Finally, Section 4 concludes it.

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Fig. 2. (a) Gilbert type single balanced mixer (b) bulk injection mixer.

the bulk injection mixer is represented in Eqs. (1) and (2) respectively.12 Av Gilbert ≈

gmLO 2 gm Z  gmLO + J Cp L

Av bulk injection ≈

2 g Z  m L

(1) (2)

where gmLO and gm are the transconductance of the LO and RF stage respectively, and ZL is the load impedance and Cp represents the shunt parasitic capacitance. From the above two expressions, it is found that the bulk injection mixer has a lesser conversion gain variation than the Gilbert cell mixer, which helps to obtain a broadly flat conversion gain over a large band of frequencies. As the LO signal is given directly to the bulk terminal, it offers a noisier transistor drain current. Hence, the bulk injection mixer is noisier than the Gilbert mixer. Figure 3 shows the schematic of bulk injection mixer where the gate voltage of the mixer core (M1–M4) is biased at 0.44 V. This voltage is smaller than the threshold voltage typically which is concerning 0.5 V in the 180 nm CMOS technologies. The LO signal is inserted into the body of core transistors (M1–M4) and modulates the threshold voltage. This threshold voltage is a function

2. MIXER DESIGN AND ANALYSIS 2.1. Bulk Injection Technique Based Mixer A Gilbert cell is preferable for the mixer design by consisting of transconductance (RF) stage, switching (LO) stage and load stage. In the bulk injection technique, the input LO and RF signals are given to the bulk and gate terminals respectively, and the output IF signal is produced from the drain so that the necessary bias is lesser than the threshold voltage (VTH  of the device.9 18 As a result, it operates in low voltage and consumes low power. But, the parasitic capacitance between the LO and RF stage, gives rise to a poorer conversion gain at a high frequency of a single balanced Gilbert cell mixer10 12 (Fig. 2(a)). This drawback is deducted by the bulk injection mixer as exposed in the Figure 2(b). The voltage gain of the Gilbert cell mixer and 2

Fig. 3. Bulk injection mixer schematic.

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Fig. 4.

Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process

Switched biasing technique mixer.

of voltage between body and source (VBS 9 and expressed as given in Eq. (3).   (3) VTH LO = VT0 +  2F − VBS LO −  2F where VT0 is the threshold voltage at zero substrate bias,  is the body effect factor and F is the surface potential. The LO signal operates the device turn off or on alternately. The small signal gain from the Figure 3 can be expressed as AV = −g m RO-pMOS  RO-nMOS 

(4)

Fig. 6.

Single ended mixer core schematic.

current Ib and (b) an “off-state” below threshold, in which, it is expected to forget about its last 1/f noise performance resulting in a reduced amount of 1/f noise in the active state.15 19–21 Hence, a decrease in the noise generated by M1 and M2 transistors in fractions of the current source concludes in a lower NF in comparison to a permanent current source. Since the output signal (IF) is used to operate the tail transistor by using self-biasing, the mixer does not require an additional bias, which results extra power consumption.

where RO-pMOS and RO-nMOS are the output resistances of the pMOS and nMOS transistors respectively. gm is the transconductance of nMOS transistor. The conversion gain (CG) of the mixer is represented in Eq. (5). 2 CG = − gm RO-pMOS  RO-nMOS  

(5)

2.2. Switched Biasing Technique Based Mixer The circuit of this type of mixer is shown in Figure 4. Here, the tail current source is divided into two equal size transistors (M1 and M2). Both transistors operate with the IF output signals periodically in between strong inversion and an accumulation region releasing trapped charge carriers, which reduces the flicker noise,11 as compared to the static current source, which is exposed explained in Figure 5. M1 and M2 transistors are periodically switched in between two states: (a) an “operational (active) state” in strong inversion, where it provides a constant bias

Fig. 5.

Switched biasing technique principle.

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Fig. 7.

Functional representation of mixer core.

Fig. 8.

Proposed cascode mixer design.

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Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process

Fig. 9. Simplified version of small signal equivalent circuit of the proposed design.

2.3. Proposed Cascode Mixer In this cascode mixer design, the voltage drop is reduced by stacking of the RF stage upon the LO stage for low voltage operation.22 The threshold voltage of the LO stage is modulated by the bulk injection technique. The mixer core schematic is exposed in Figure 6. It includes a LO switch stage (M1), an RF transconductance (Gm  stage (M2), an active load stage as a pMOS transistor (M3)

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and switched biasing stage (M0) as a current source. The equivalent functional model is represented in Figure 7. The transconductance stage is basically biased in active region, which operates as a voltage to current converter, to get low NF and high conversion gain. The switching task is carried out by the LO switch stage. The gate voltage VB (VG  of the LO stage is biased smaller than the threshold voltage (VTH , as VTH is concerning 0.5 V in the 180 nm CMOS process.12 The LO signal as the function of body to source voltage is applied into the body of the transistors and modulates the threshold voltage which is represented in the previous Eq. (3). The mixer core transistor (i.e., M1) is biased at 0.44 V < 0.5 V (VTH , which results the switching stage to almost in turn-off state with approximately no dc current to the core of the mixer6 with the low power performance. The current to voltage transformation is done by the high output impedance M3 transistor acting as an active load for the IF output signals. The circuit diagram of the proposed cascode mixer is represented in Figure 8, where dual balanced configuration is preferred to improve port to port isolation. The main parts of the proposed mixer include LO switch stage (M1–M4), RF transconductance stage (M5–M8), pMOS

Fig. 10. Schematic of proposed cascode mixer.

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Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process

Table I. Design parameters for the mixer. Design parameters

Proper value

(W/L)M1–M8 (W/L)M9 M10 (W/L)M11 M12 (W/L)M13 M14 RB

25/0.18 m 50/0.18 m 80/0.18 m 40/0.18 m 1.5 K

transistors (M9–M10) as active load. In addition this, the switched biasing stage (M13–M14) is used as a current source with a dc level shifter (M11–M12). The bulk injection technique is used here for low voltage and low power operation.9 But this technique has a high NF which is a major drawback. So to progress this noise performance, switched biasing technique is used. Here, tail current source is divided into two half-size transistors (M13 and M14) where the switching operation is a balanced one. These transistors operate alternatively by the IF output signals, which results in a reduced flicker noise by maintaining the identical dc current supply like static current source. Further, the symmetric switching operation is achieved by the insertion of dc level shifter (M11–M12) in the tail current transistors.11 To improve the NF, a dc level shifter is implemented in the proposed circuit to offer the tail current transistors with an appropriate gate to source voltage. This makes the overdrive voltage extremely small for the balanced switching operation with a little output swing.11 The 40 m width size has been taken for the transistors (M13–M14) to generate an enough current with a little overdrive voltage to reduce the output NF. So the diminution in the noise created by the MOS transistors in fractions of the current

Fig. 11.

Fig. 12.

Conversion gain versus LO power.

source concludes in a lower NF in comparison to a constant current source. Three stacked levels of transistors (M9, M5, and M1) are working in active, active and linear region respectively, with a 0.9 V supply voltage requirement for the proposed mixer. 2.4. Performance Analysis According to the principle of operation, a simplified version of the cascode mixer is explained in Figure 9. The common-source transistor amplifies the RF signal with a source degeneration resistor (ron  and the output load resistor (rop . So, the small signal voltage gain AV is expressed as AV = −

gm rop-active 1 + gmron-linear + ron-linear /rop-active

(6)

Transient of proposed mixer.

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Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process

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where rop and ron are the output resistance of pMOS and nMOS transistors respectively. The suffix of “linear” and “active” means the transistor’s operating region. Since ro−linear is smaller than ro−active , there should be linear operation of the LO transistor. The active load, which acts as output desires to bias in the active region to optimize small signal gain.6 In Figure 8, the differential RF transconductance currents are related with the transconductance (gM5 –gM8  and RF input signal (VRF = 1/2ARF COS(RF t)). By considering the LO switching voltage is a perfect square wave signal, the output signal (IF) is generated as follows

Fig. 13. Noise figure versus IF frequency.

iIF5 6 t = −gm5 m6 ARF COSIF t

(7)

iIF7 8 t = −gm7 8 ARF COSIF t

(8)

where IF is the IF angular frequency (RF –LO . Assuming the transconductances of M5, M6, M7 and M8 are equal, the overall differential output voltage (IF) is written as gm rop-active A COSIF t VIF t = 1 + gm ron-linear + ron-linear /rop-active RF (9) Thus, the voltage conversion gain of the proposed design is represented as CG =

gm rop-active 2  1 + gmron-linear + ron-linear /rop-active

(10)

Assuming that Fig. 14. IIP3 (IF power versus RF power) of proposed design.

gm ron-linear  1 and

gm ron-linear 

ron-linear rop-active

Fig. 15. Layout design of proposed mixer.

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Rout et al. Table II.

Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process

Performance summary of CMOS mixers.

References

CMOS process ( m)

Frequency (GHz)

LO power (dBm)

Conversion gain (dB)

DSB NF (dB)

IIP3 (dBm)

Supply voltage (V)

Power (mW)

[4] [5] [8] [9] [12] This work

0.13 0.13 0.18 0.18 0.18 0.18

10–35 3.1–10.6 0.2–16 0.5–7.5 0.2–13 2.4

13 −3 −2 5 5 4

1 14 87 57 99 148

– 145 – 15 117 94

−4 −11 −10 −57 −10 −9

1.6 1.2 1.8 0.8 0.8 0.9

6 185 15 05 088 06

4. CONCLUSION

the voltage conversion gain can be approximated as 2 rop-active CG   ron-linear

(11)

From the Eq. (11), it is concluded that the voltage conversion gain is dependent proportionally to the ratio of output resistance of active load pMOS transistor and output resistance of switch stage nMOS transistor. The noise in the MOS transistor is controlled by the thermal noise generated from the channel resistor. This noise source is expressed by a noise current12 generator from drain to source as follows; i¯n2 = 4kTgm f

(12)

where k is Boltzmann’s constant with absolute temperature T, gm is the transconductance and  is 2/3 for long channel transistors with f as a change in frequency.

3. SIMULATION RESULTS The proposed cascode mixer is realized using Cadence tools with UMC 180 nm CMOS technology. The schematic of the proposed design is shown in Figure 10. The design parameters used for the proposed mixer simulation are given in Table I. The transient analysis of the proposed cascode circuit is represented in Figure 11, in which the IF frequency is observed as 100 MHz. Figure 12 shows the graph in between the conversion gain and LO power, in which the maximum conversion gain is 14.8 dB for LO power of 4 dBm. The simulated NF with IF frequency is plotted in Figure 13, in which NF reduces with the IF frequency and finally, it is 9.4 dB at 100 MHz of IF frequency. Figure 14 shows the plot of IF output power versus RF input power. From this plot, the input third order intercept point (IIP3) is found as −9 dBm. The layout diagram of the proposed design is exposed in Figure 15, which represents the area of 0.0503 × 0.0347 mm2 . The comparison of the proposed cascode mixer design with other different reported designs is represented in Table II. From the Table II, it seems that the proposed mixer has the advantages of high conversion gain and low NF with the improvement in IIP3, power supply and power consumption than the other reported works. J. Low Power Electron. 14, 1–8, 2018

The design of cascode topology mixer with the bulk injection and switched biasing techniques is presented to get an improved voltage and power operation of the circuit with high conversion gain and low NF. The proposed mixer results a high conversion gain of 14.8 dB at LO power of 4 dBm, a NF of 9.4 dB, IIP3 of −9 dBm and the power consumption of 0.6 mW from the supply voltage of 0.9 V with chip area of 0.0503 × 0.0347 mm2 . Therefore, this mixer design is used as a suitable block in the low voltage and low power RF receiver front end. Acknowledgment: All the simulations and implementation are carried out in Laboratory of Department of Electronics and Telecom. Engineering, VSSUT, India and School of Electronics Engineering, KIIT University, India. This study did not receive funding from any agencies. The authors declare that there is no conflict of interest concerning the publication of this paper.

References 1. B. Leung, VLSI for Wireless Communication, Prentice Hall Electronics and VLSI Series, 1st edn., Pearson Education (2004). 2. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edn., Cambridge University Press (2004). 3. H. M. Wang, A 1-V multigigahertz RF mixer core in 0.5 m CMOS. IEEE Journal of Solid-State Circuits 33, 2265 (1998). 4. C. L. Kuo, B. J. Huang, C. C. Kuo, K. Y. Lin, and H. Wang, A 10–35 GHz low power bulk driven mixer using 0.13 m CMOS process. IEEE Microwave and Wireless Components Letters 18, 455 (2008). 5. J. B. Seo, J. H. Kim, H. Sun, and T. Y. Yun, A low-power and high gain mixer for UWB systems. IEEE Microwave and Wireless Components Letters 18, 803 (2008). 6. K. H. Liang and H. Y. Chang, 0.5–6 GHz low-voltage, low-power mixer using a modified cascode topology in 0.18 m CMOS technology. IET Microwaves, Antennas and Propagation 5, 167 (2011). 7. B. Han, X. Zhang, and X. Li, A 0.8 V low-voltage, low-power source-driven mixer in 0.18 m CMOS technology, International Conference on Wireless Communications and Signal Processing (WCSP) (2015), pp. 1–4. 8. F. C. Chang, P. C. Huang, S. F. Chao, and H. Wang, A low power folded mixer for UWB system applications in 0.18 m CMOS technology. IEEE Microwave and Wireless Components Letters 17, 367 (2007). 9. K. H. Liang, H. Y. Chang, and Y. J. Chan, A 0.5–7.5 GHz ultra lowvoltage low-power mixer using bulk-injection method by 0.18 m CMOS technology. IEEE Microwave and Wireless Components Letters 17, 531 (2007).

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Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process 10. S. S. Rout, R. K. Barik, and S. K. Dwibedi, A low voltage and low noise CMOS RF bulk injection mixer for UWB system application. International Journal of Advance Research in Electronics and Communication Engineering 3, 445 (2014). 11. J. H. Kim, H. W. An, and T. Y. Yun, A low-noise WLAN mixer using switched biasing technique. IEEE Microwave and Wireless Components Letters 19, 650 (2009). 12. M. G. Kim, H. W. An, Y. M. Kang, J. Y. Lee, and T. Y. Yun, A lowvoltage, low-power, and low-noise UWB mixer using bulk-injection and switched biasing techniques. IEEE Transactions on Microwave Theory and Techniques 60, 2486 (2012). 13. G. H. Tan, R. M. Sidek, H. Ramiah, W. K. Chong, and D. X. Lioe, Ultra-low-voltage CMOS-based current bleeding mixer with high LO-RF isolation. The Scientific World Journal 2014, Article ID: 163414 (2014). 14. L. A. NacEachern and T. Manku, A charge-injection method for Gilbert cell, Proceedings IEEE Canadian Conference on Electrical and Computer Engineering (1998), pp. 365–368. 15. J. Park, C. H. Lee, B. S. Kim, and J. Laskar, Design and analysis of low flicker noise CMOS mixer for direct-conversion receivers. IEEE Transactions on Microwave Theory and Techniques 54, 4372 (2006). 16. L. K. Meng, N. C. Yong, Y. K. Seng, and D. M. Anh, A 2.4 GHz ultra low power subthreshold CMOS low-noise amplifier. Microwave and Optical Technology Letters 49, 743 (2007).

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17. R. Raja, R. Theegala, and B. Venkataramani, A low-power and highly linear merged low noise amplifier-mixer for wireless sensor network applications. Journal of Low Power Electronics 12, 368 (2016). 18. N. Stojadinovic, I. Manic, V. Davidovic, D. Dankovic, S. DjoricVeljkovic, S. Golubovic, and S. Dimitrijev, Effects of electrical stressing in power VDMOSFETs. Microelectronics Reliability 45, 115 (2005). 19. S. S. Rout and K. Sethi, A high gain and low noise CMOS Gilbert mixer with improved linearity based on MGTR and switched biasing technique. ICTACT Journal on Microelectronics 2, 311 (2017). 20. E. A. M. Klumperink, S. L. J. Gierkink, A. P. van der Wel, and B. Nauta, Reducing MOSFET 1/f noise and power consumption by switched biasing. IEEE Journal of Solid-State Circuits 35, 994 (2000). 21. S. S. Rout and K. Sethi, Design of high gain and low noise CMOS Gilbert cell mixer for receiver front end design, 15th IEEE International Conference on Information Technology (ICIT) (2016), pp. 1–5. 22. Q. Wan, C. Wang, and F. Yu, Design of a 2.4 GHz high-performance up-conversion mixer with current mirror topology. Radioengineering 21, 752 (2012).

Shasanka Sekhar Rout Shasanka Sekhar Rout is doing his Ph.D. at VSS University of Technology (VSSUT), Burla, Odisha, India. He received his M.Tech degree in VLSI Signal Processing from VSSUT, Burla, India in 2014. His research area is on VLSI Signal Processing, analog and RF CMOS circuit design. He has various national and international conference papers and journals. Currently he focuses on designing the improved receiver front end. He is a life member of ISTE.

S. K. Mohapatra S. K. Mohapatra awarded Ph.D. on Nanoelctronics Devices from National Institute of Technology, Rourkela, Odisha in 2016, received the M.E. degree in Communication Control and Networking from the M.I.T.S, Gwalior, India, in 2001, completed B.E. (Electronics and Telecommunication) from Utkal University, Bhubaneswar, in 1994. Currently working in School of Electronics Engineering, KIIT University, Bhubaneswar as Assistant Professor (II). His research interests include Modeling and Simulation of CMOS for RF FoMs, FinFETs, Tunneling transistor, Low-power nano CMOS, VLSI design, III–V compound semiconductors, Wireless sensor networking with its application towards IoT. He has authored more than 47 research articles in National and International Journals and Conferences. He is a life member of ISTE, IETE, CSI, OITS and member of IEEE. The biography included in the “2016 33rd edition of the Marquis Who’s Who in the World.”

Kabiraj Sethi Kabiraj Sethi is working as Associate Professor in the department of Electronics and Telecom. Engineering at VSS University of Technology (VSSUT), Burla, Odisha, India. He received his Ph.D. degree from Sambalpur University, Odisha, India in 2014. He has guided more than 10 M.Tech scholars and currently guiding 4 Ph.D. scholars. He contributed various international journals and conference papers in the area of analog mixed mode design, digital processor designing and semiconductor device modeling. His research interests include VLSI design, VLSI Signal Processing and analog and mixed signal design.

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