Design of digit serial FIR filter using shift add architecture

2014 International Conference on Smart Structures & Systems (ICSSS-2014), Chennai-INDIA.

Design of Digit Serial FIR Filter Using Shift Add Architecture Shailesh S.Nichat

Prof.Shrikant J.Honade

Dr.Prashant V.Ingole

P.G.Scholar Department of E&TC GHRCEM, Amaravati SGBAU, Amaravati [email protected]

Assistant Professor Department of E&TC GHRCEM, Amaravati SGBAU, Amaravati [email protected]

Member, IEEE Principal GHRCEM, Amaravati SGBAU, Amaravati [email protected]

Abstract— Most of the researchers have developed the solution for designing multiplier and accumulator (MAC) section used in Digital signal processor by using number of algorithms and architectures. Multiple constant multiplications (MCM) is a factor which dominates the complexity of many digital signal processing systems. This paper deals with the designing of digit serial FIR filter which will reduce the complexity of multiple constant multiplications in digital signal processors by reducing the gate area and power consumption. In order to achieve this, shift/ add architecture concept is proposed.

point filters is used. The MAC unit is used for addition and subtraction operation. This set of functions implements arbitrary order non-recursive filter using Direct Form structure. These filters are implemented as a cascade of second order Biquard section. This Biquard functions has advantage of a slight memory saving. After execution, the generated result for Direct Form Filter is indicated in the form of pi-chart as shown in figure 2.

Index Terms— Multiplier and Accumulator, Multiple constant multiplications, Shift /Add architecture, Direct form filter, transpose form filter.

a(7:0)

U3

b(7:0)

c(13:0)

c(13:0)

multi16

a(7:0)

U24

U36

U31

b (3 1:0 ) c(3 1:0 )

adder1431

a(13:0)

a(13:0)

b(31:0)

q (7 :0 )

latch h1(7:0)

h0(7:0) b(7:0)

1.1 Direct Form Filter In the experiment shown in figure 1, first of all the MAC operation is performed by using direct form filter. To observe the performance of direct form filter, in direct form filter the Latch is connected in upper side with (0-7) input signal. In this experiment eighteen

d (7 :0 )

multi16

Finite Impulse Response (FIR) filter are of great importance in digital signal processing (DSP) systems since their characteristics in linear phase and feed forward implementation make them very useful for building stable high performance filters. The direct and transposed form FIR filters implementations are mostly use in the context of digital filters. Although both architectures have similar complexity in hardware, the transposed form is generally preferred because of its higher performance and power efficiency. The multiplier block of the digital FIR filter in input stage is very compact structure because of the complexity and performance of the design. This is generally known as the multiple constant Multiplication (MCM) operation. In order to perform multiple constant multiplications (MCM) in MAC unit of digital filters, many algorithms had been proposed. But these algorithms are unable to provide the better solution. To address this problem, a new method based on Shift/add concept is proposed.

x(7:0)

rst

INTRODUCTION

U37 clk

I.

rst clk

b (3 1:0 ) c(3 1:0 )

adder1431

Fig 1: - Direct form FIR Filter Structure

The disadvantage of this structure is that, it increases the possibility of arithmetic overflow for filter of high Q or resonance. It has been shown that as Q increases, the round-off noise of direct form topology increases without bound. Here fig. 2 (a) shows the area which is consumed by filter called combinational and non-combinational area. Here combinational area is greater than the non-

978-1-4799-6506-9/18 ©2014 IEEE 90

2014 International Conference on Smart Structures & Systems (ICSSS-2014), Chennai-INDIA.

combinational area. Fig. 2 (b) shows the internal power required for the execution.

filter0-area 1404.14563

Combinational area Noncombinational area

27050.45198

(a)

filter0-power

2.4014 Cell Internal Power Net Switching Power

simultaneously so that all latches should execute at same time. The direct form has to perform huge addition at the output, which maps very well to the MAC operations on a DSP processor but may be a problem if implemented in hardware. The transposed structure has many small additions separated by delay elements. This might work better in a FPGA or ASIC implementation. The direct form FIR filter needs extra pipeline registers between the adders to reduce the delay of the adder tree and to achieve high throughput. The FIR filter with transposed structure has registers between the adders and can achieve high throughput without adding any extra pine line registers. Transposed form is self pipelined with the cycle period, the delay of an adder and a multiplier. But it consumes more area than direct form. We can add even delay in direct form or transposed form to make the design faster which results in mixed form. Here fig. 4 (a) shows the area which is consumed by filter called combinational and non-combinational area. Here combinational area is greater than the noncombinational area. Also, the internal power required for the execution is shown in Fig. 4 (b).

3.4263

5616.58252

filter1-area

(b) Figure 2: Direct Form FIR Filter. Fig. (a) Specific area use by filter. Fig. (b) Power use by filter. Combinational area

1.2 Transpose Form Filter.

Noncombinational area

x(7:0)

29009.77936

h0(7:0)

h1(7:0) a(7:0) c(13:0)

U3

multi16

filter1-power

U31

b (3 1:0 ) c (3 1:0 )

U37 latch32 d (3 1:0 )

5.0117

b (3 1:0 ) c (3 1:0 )

Cell Internal Power

rst

clk

adder1431

q (3 1:0 )

a(13:0)

a(13:0)

b(31:0)

b(7:0)

a(7:0) c(13:0)

U24

multi16

b(7:0)

U36

(a)

adder1431

Net Switching Power

clk rst

7.7737

Figure 3: Transpose form FIR Filter Structure

In this case, the direct form filter structure is replaced by Transpose form structure as the transpose form provides the flexibility in filter structure. Here, for proper operation of filter, latch is connected to the bottom. The reason to use Transpose form filter is that, any changes in the filter structure is possible. Here implementation shown in fig. 3 consist 8 bit multiplier, 32 bit adder, and 32 bit input latch, One clock and one reset button is also connected to all latch

(b) Figure 4 : Transpose Form Filter 1. Fig. 4 (a) Specific area use by filter. Fig (b) Power use by filter.

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2014 International Conference on Smart Structures & Systems (ICSSS-2014), Chennai-INDIA.

Fig 5: - Shift/Add in Transpose form FIR Filter Structure

In filter 2, the shift/add architecture is added in transpose form filter. Here 18 orders Transpose form filter is used with symmetric impulse response so 9 coefficients are repeated. Because of reuse of filter coefficients, 9 multiplier blocks gets reduced which results in reduction of pulse combinational area required for filter.

1.3 Filter 2 x(7:0)

a(7:0) y(13:0)

U31 a(13:0)

a(13:0)

U37 latch32

b (3 1:0 ) c (3 1:0 )

d (3 1:0 )

q (3 1:0 )

b (3 1:0 ) c (3 1:0 )

clk

rst

b(31:0)

U24

mulh1

a(7:0) y(13:0)

U3

mulh0

U36

Because of less circuit complexity, power consumed by the unwanted 9 multiplier is saved due to the use of shift/add architecture. So, filter 2 is a similar filter structure like the transpose form filter only the shift/add concept is added to save the area and power consumption of filter. Here fig. 6 (a) shows the area which is consumed by filter called combinational and non-combinational area. Here combinational area is greater than the non-combinational area. Also the internal power required for the execution is shown in fig. 6 (b).

adder1431

adder1431

clk rst

filter2-area

filter2-power

5616.58252 0.8715258 Combinational area

Cell Internal Power

Noncombinational area

Net Switching Power 1.4735

15383.18436

(a)

(b)

Figure 6: Filter 2. Figure (a) Specific area use by filter. Figure (b) Power use by filter.

Table1: Comparative Result of MCM block for filter 0, filter 1 and filter 2.

Filter name

Filter 0

Total Cell Area Combinational NonArea Combinational Area 27050.45198 1404.14563

Total Dynamic Power Cell Internal Power Net Switching Power. 3.4263mW

2.4014mW

Filter 1

29009.77936

5616.58252

7.7737 mW

5.0117 mW

Filter 2

15383.18436

5616.58252

1.4735 mW

871.5258 uW

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2014 International Conference on Smart Structures & Systems (ICSSS-2014), Chennai-INDIA.

CONCLUSION In this paper, Shift/add architecture based designing of digit serial MCM operation with minimal area and power at gate level, by considering the implementation cost of digit serial addition, subtraction, and shifts operations is implemented. The experimental result indicates that the complexity of the MCM design is reduced by using Shift/ Add architecture operated on transpose form filter structure as depicted in Table 1. The future work of this project deals with the design of digit serial FIR filter using pipelining concept is under study in order to obtain the further reduction in area and power. REFERENCES [1] R. Hartley and P. Corbett.“Digit-Serial Processing Techniques,” IEEE TCAS II, 1990, 37(6), pp. 707-719. [2] L. Aksoy, E. Costa, P. Flores, and J. Monteiro, “Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications,” IEEE TCAD, , 2008, 27(6), pp. 1013-1026. [3] L. Aksoy, E. Gunes, and P. Flores, “Search Algorithms for the Multiple Constant Multiplications Problem: Exact and Approximate,” Elsevier Journal on Microprocessors and Microsystems, 2010, issue 34, pp. 151-162. [4] L. Aksoy, C. Lazzari, E. Costa, P. Flores, and J. Monteiro, “Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level. In ISCAS, to appear,” 2011. [5] I. C. Park and H. J. Kang, “Digital filter synthesis based on minimal signed digit representation,” Proc. DAC, 2001, pp. 468– 473. [6] Shailesh Nichat and Shrikant Honade “Design of digit serial FIR filter using Graph base technique,” IJCET, 2013. [7] C. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput, Feb. 1964, vol. 13, issue 1, pp. 14–17. [8] W. Gallagher and E. Swartzlander, “High radix booth multipliers using reduced area adder trees,” Proc. Asilomar Conf. on Signals, Syst. Comput. Pacific Grove, CA, Oct.–Nov. 1994, vol. 1, pp. 545–549.

ACKNOWLEGEMENT The author sincerely thanks to Mr. Shrikant. J. Honade, Assistant Professor, G.H.R.C.E.M., Amravati, Dr. P. V. Ingole, Principal, G.H.R.C.E.M., Amravati, Prof. N. N. Mandaogade, Head of E & TC Department G.H.R.C.E.M Amravati for their valuable suggestion, criticism and time to time encouragement. The author also expresses his warm appreciation to his Brother, Nilesh Nichat for his help in editing this article. AUTHOR BIOGRAPHY Shailesh S. Nichat completed B.E. in Electronics and Telecommunication Engineering from H. V. P. M’s College of Engineering Amravati, India in 2009 and now pursuing M.E. in Electronics and Telecommunication Engineering branch from G.

H. Raisoni College of Engineering and Management, Amravati. His area of research includes Wireless Communication, Image Processing, Network Security, Control System and Neural Networks. Prof. Shrikant J. Honade has received his M. Tech. degree in Electronic Systems and Communication from Govt. College of Engineering, Amravati, India and B. E. degree from H. V. P. M’s College of Engineering, .Amravati. He has published one paper at national level and eleven papers in various international journals. His area of research includes Signal / Image Processing, Artificial Intelligence and VLSI. He is presently working as an Assistant Professor in Electronics and Telecommunication Engineering department at G. H. Raisoni College of Engineering and Management, Amravati(Maharashtra)

Dr. Prashant V. Ingole has received his Ph.D. degree in Electronics Engineering from V. N. I. T., Nagpur in 2010. He has guided 16 M. E. students and presently guiding 5 Ph. D. Scholars. He has presented 15 papers at national conferences and 07 papers at various international conferences. His research paper publication includes 02 papers at national level journals and 14 papers in various international journals. His area of research includes signal / Image Processing, Artificial Intelligence and Biomedical signal processing. He is a member of IEEE, fellow of IETE and life member of ISTE. He is presently working as a Principal at G. H. Raisoni College of Engineering and Management, Amravati (Maharashtra)

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