Design optimization methodology of CMOS direct

2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

Design optimization methodology of CMOS direct Down-conversion Mixer for Wireless Sensors Hanen Thabet and Mohamed Masmoudi Electronics, Micro-technology and Communication (EMC) research group National Engineering School of Sfax (ENIS), BP W, 3038 Sfax, Tunisia E-Mail : [email protected], [email protected]

Abstract— This paper presents simulation results of an active down-conversion Mixer used in a frequency-hopped spread-spectrum receiver operating in the 863–870 MHz European band for wireless sensor applications. The doubly-balanced Mixer is designed using the Gilbert cell with the current-reuse bleeding technique based on the 0.35ȝm technology. The various parameters of the Mixer, as noise figure, conversion gain and linearity are simulated and optimized to meet Mixer specifications. The Mixer simulations show 12.5 dB conversion gain, -10.25 dBm CP-1dB, and 9.74 dB NF. Keywords— Direct down-conversion Mixer, CMOS technology, current-reuse bleeding technique, linearity, noise figure, conversion gain.

of the Mixer are the lowest possible noise figure with a reasonable gain. It is also desired that the mixer has high linearity and consumes the minimum possible power. This work deals with a down-conversion Mixer for the receiver section of an integrated frequency- hopped spreadspectrum transceiver operating in the 863– 870 MHz band. The receiver architecture (Fig. 1) is presented in Section II. The proposed Mixer topology and design methodology are given in Section III. Section IV presents simulation results and discussion. Finally, the conclusion is given in Section V. II. RECEIVER ARCHITECTURE

I. INTRODUCTION After the development of intelligent sensors, powerful microprocessors and communication protocols, recent studies have considerable interest in the field of Wireless Sensor Networks. These networks, composed by elements named sensors nodes, have the objective of data collecting, processing, and disseminating to a point of interest. These tiny nodes which are used in typical applications such as home automation, industrial control and monitoring, communicate in short distances and collaboratively work toward fulfilling the specific application objectives of the WSN. With the increasing demand of ultra-low-power low cost highly IC’s wireless sensor and to reach application’s objectives, we explore CMOS technology which presents the most attractive solution. Since the CMOS technology enables development of true System-on-Chips (SoCs) for wireless communication [1], it is used in combination with highly integrated RF-IC implementations (the direct conversion architecture), the 863-870 MHz band, which was established by the Electronic Communications Committee (ECC) [2] and even the new global standard for wireless connectivity: ZigBee. The direct conversion architecture used has recently attracted widespread use for its simplicity, monolithic integration, and as well as its low power consumption and low manufacturing costs [3]. In a radio frequency wireless communication system, as a part of RF frond-end circuit, the Mixer is a critical building block which set the receiving linearity of the overall system. The mixer generally directly follows the Low Noise Amplifier and therefore the main requirements

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As it is characterized by its low-power spectral density and high immunity to fading and interference, the Frequency Hopped Spread Spectrum (FHSS) system was chosen to be used. The receiver is designed for binary frequency-shift keying (BFSK) modulation with a data rate of 20 kb/ s. The peak signal energy in the modulated base band spectrum concentrates in the frequency of 20 kHz, while relatively little energy lies at dc. The transmission bandwidth of the BFSK signal was calculated to be 80 KHz. A maximum of 58 channels has been chosen to fulfil FHSS requirement and ETSI regulations (which demand a minimum separation of 25 kHz between adjacent channels) [4]. Therefore, the separation between adjacent channels has been chosen equal to 40 kHz to have eventually 58 channels. In spite of some well-known problems which prevented its widespread use, the direct conversion architecture has been well-recognized for its simplicity and potential for singlechip implementation. Furthermore, it requires a minimum RF section since there is no image-reject filter. The receiver (Fig. 1) operates as follows: the RF band pass filter (BPF) between the Low Noise Amplifier (LNA) and antenna suppresses out-of-band signals at the receiver input acting as the RF preselect filter. The received FHBFSK is first amplified with a LNA then down converted by the down-conversion Mixer using the hopping local oscillator (LO) to zero-IF. A low pass channel-select filter, in each path, passes only the selected user's received signal and suppresses adjacent channels by selecting the desired user’s channel, which is now centred at 0 Hz. As in any FM

2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

receiver, instead of a complicated linear AGC, a simple limiting amplifier converts the received signal to binary levels. Low Noise Amplifier Data out Mixers

LPF

Digital FSK detector

Limiters

This mixer consists of two differential stages. Transistors M3 and M6 are used as linear RF voltage-to-current converter or RF transconductance amplifier whose output current is commutated by the local oscillator (LO). Whereas M1, M2, M4 and M5 form the differential switching quad. For perfect switching, the size of transistors M1, M2, M4 and M5 is much smaller than M3 and M6.

LO - I

BPF

Hopping LO

LO - Q

Power Amplifier Digital FSK

Data in

Modulator

Fig.1. Wireless sensor receiver architecture

The receiver specifications were calculated taking in consideration the most demanding characteristics of an integrated receiver which are sensitivity, selectivity, linearity and dynamic range [4]. Then the receiver was simulated in order to determine blocks parameters that meet the overall predicted receiver specifications [5]. As a result of receiver simulations, Mixer specifications are illustrated by Table 1. Table 1. Specifications of the Mixer Conversion gain Noise figure (NFSSB) CP-1dB

12.7 dB 13 dB - 9 dBm

III. TOPOLOGY AND DESIGN METHODOLOGY

A. Mixer architecture An ideal mixer is a three-port circuit that converts signals from one frequency to another intermediate frequency by multiplying two signals at two different frequencies. The Mixer then produces at the third port a signal that is the difference of the two input frequencies it is placed at the receiver (down-conversion). Since time-invariant systems are linear, they can not produce outputs with spectral components not present at the input, to provide frequency translation, a non linear or time varying device is required [6]. The most commonly used kind of mixer is a double balanced mixer using the Gilbert cell multiplier. This mixer provides good port-to-port isolation due to its fully differential structure witch cancels both LO-IF and RF-IF feedback. The proposed mixer is a CMOS doubly balanced mixer based on the Gilbert cell as shown in Fig. 2.

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Fig. 2. Double balanced Gilbert mixer

B. Design methodology In a wireless receiver, the double balanced mixer follows the low noise amplifier LNA witch has a single ended topology [7]. Therefore, one of the mixer inputs will be shorted to AC ground and the other mixer input will be coupled to the single-ended LNA output. By doing so, we avoid the use of a balun transformer between LNA and mixer. For wide transistors, the use of multi-finger gates in the layout improves RF circuit performance in term of noise contribution since it results in a significant decrease of the gate resistance [8]. The mixer design is a challenge since requirements set on the down-converter are extremely stringent. The design is particularly tough since noise and linearity specifications are severe, also low noise and low power consumption is usually contrasting to high linearity. So a specific approach has been carried on to design an optimised circuit. A theoretical analysis undertaken by Terrovitis and Meyer gives an approximate model for the noise figure of CMOS Gilbert Cell based mixer [9]. Having calculated the noise contribution from the various sources to the output, the single-sideband (SSB) noise figure for the single balanced mixer given with details in [9] can be estimated by the following equation:

NF ( SSB )

ª § J 2D ¨¨ R S  rg 3  3 « g m3 D © 10 . log «« 2  c « «¬

· § 1 ·º ¸ ˜ g m 3 2  J 1 ˜ G  ( 4 rg 1 ) G 2  ¨ ¸ ¨ R ¸» ¸ © L ¹» ¹ 2 » R S ˜ c ˜ g m 3 » »¼

Eq 1

2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

The quantities Rs, rgi, gmi, G and G 2 depend on the aspect ratio W/L of transistors and also the bias current IB. So, the model given by Eq 1 can be used to determine transistors size and bias current value. Fig 3 exhibits the Noise Figure curve as a function of IB and W witch present width of transistors assumed all equal. According to this curve a bias current of 5mA can ensure simultaneously low power consumption and low noise contribution. Since the 0.35ȝm CMOS technology is employed for the design, the transistor length L is chosen equal to 0.35 ȝm in order to keep a small size circuit. The supply voltage was fixed at 3 V to guarantee low power consumption. Once the current is fixed, a second step consists in drawing variation of the SSB noise figure as a function of WRF and WLO which are widths of the RF port transistors and LO port transistors, respectively. We obtain then the curve Fig 4 for IB equal to 5mA:

Gc

2 2 .I B .R L .V LO

S .(V GS  VT ) LO (V GS  VT ) RF

§ sin ¨¨ ©

2 .(V GS  VT ) LO V LO

· ¸ ¸ ¹

Eq 2

Fig 5 shows the variation of the voltage gain as a function of WRF and WLO. It is obvious that higher conversion gain is obtained for wide RF transistors and narrow LO transistors.

Fig. 5. Conversion gain curve as a function of WRF and WLO

The equation Eq 3 describing the third-orderinterception point IIP3 shows that to achieve high linearity a high overdrive voltage of RF devices is required. IIP 3

4.

2 VGS  VT 3

RF

Eq 3

The optimisation methodology is based on the developed models already introduced for noise, gain and linearity. Higher gain, better linearity and lower noise figure can be achieved by increasing the bias current through the transconductance stage, but the power consumption will be excessive. On the other hand, to achieve higher gain without considerable noise degradation, switching transistors must be narrow. So, mixer’s parameters are not easy to achieve simultaneously. Therefore, to resolve all these trade-off cycles of optimization were carried using the command “tune parameter” of ADS tool and the following preliminary parameter’s values are obtained: - For transconductance stage: WRF=480Pm - For switching stage: WLO =210Pm - Resistance load: RL=500: For the design, the intermediate frequency FIF was chosen equal to 100 KHz, FLO is equal to the central frequency of the ISM band which is 866.5 MHz. Thus we have a FRF frequency of 866.6 MHz.

Fig. 3. Noise Figure curve as a function of IB and W

Fig. 4. Noise Figure curve as a function of WRF and WLO

We deduce that the noise figure decreases if widths increase but its variation is more dependent on WRF. The variation of WLO value has a negligible effect on the noise figure. So, we propose studying other mixer’s parameters to choose the appropriate width’s value. The total mixer conversion gain is the product of the RF-IF switching stage gain and the RF pair gain and it can be expressed by:

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IV. SIMULATION RESULTS AND DISCUSSION A. Simulation results 1) First approach It consists on simulating a double balanced mixer based on the Gilbert cell core with a power consumption of

2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

15mA. Before simulating the circuit, we must guarantee that all transistors are operating in saturation region. Simulation results obtained are shown in figures bellow: As can be seen in figures Fig 6 and Fig 7, the simulated mixer has a conversion gain of about 11.3 dB and a linearity of -14.5 dBm, respectively. Table 2 shows that the mixer has a single-side band noise figure (NFSSB) of 8.8 dB.

The reactive source degeneration has lower NF than that with resistive degeneration. Indeed, the use of an inductance connected in series with RS improves gain. By doing the same simulation process as done for RS we can notice that gain increases with the increase of inductance value. For inductance LS equal to 2 nH, simulation results are presented on Fig 9, Fig 10 and Table 3.

Fig. 8. Source degeneration

Fig. 6. Simulated conversion gain (first approach)

Fig. 9. Simulated conversion gain (second approach) Fig. 7. Linearity simulation (first approach) Table. 2. Simulated noise figure (first approach)

It is obvious that the Gilbert cell used gives acceptable levels in term of gain and noise figure but these results are not satisfactory in term of linearity which is lower than value required by mixer’s specifications.

Fig. 10. Linearity simulation (second approach) Table. 3. Simulated noise figure (second approach)

2) Second approach There are different techniques to improve linearity of a double-balanced mixer. The most used is the source degeneration witch can be implemented by using resistor, capacitor or inductor. In our circuit, we adopted first the resistive source degeneration whose topology is presented on Fig 8. The resistance is placed at source of the differential pair transconductance stage. To determine resistance value we carry out a DC analysis and an AC analysis, respectively with variation of both RS value and voltage at RF input. A value of 10Ÿ was kept for RS. We notice that by increasing RS value the linearity increases but the gain decreases.

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The second approach gives a conversion gain of about 8 dB, a linearity of -10.5 dBm and a single-side band noise figure (NFSSb) of about 10.4 dB. It is obvious that this technique gives acceptable levels in term of linearity and noise figure but results are not satisfactory in term of gain which is lower than value required mentioned on table 1. To reach mixer’s specifications, the third approach used consists in a technique allowing an improvement of the conversion gain without affecting the linearity.

2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

3) Third approach To improve both gain and linearity, we should increase the RF stage bias current without varying the bias current of the switching pair. This can be achieved using the charge injection or current-reuse-bleeding technique [10]. Fig 11 shows a single-balanced implementation of the proposed mixer using the bleeding technique in which a bleeding current source (IBLD) is added through the PMOS transistor MBLD in cascode with the transconductance stage transistor MRF. Fig. 12. Conversion gain curve as a function of RL and Wp (third approach)

According to simulation results given we obtain a conversion gain of about 12.5 dB (Fig. 13), a linearity of 10.25 dBm (Fig. 14) and a noise figure of 9.7 dB (Table 4), respectively.

Fig.11. Single-balanced mixer with current-reuse bleeding technique

With the bleeding current source the total bias current is: I D 1  I D 2  I BLD

I bias

Eq 4

Fig. 13. Simulated conversion gain (third approach)

The value of current through switching stage can be kept and that way the total power consumption would increase due to increase of the total bias current. Alternatively, it is possible to keep constant the total bias current and thus the power consumption. Consequently, ID1 and ID2 should decrease to reach a value of 1.5 mA as a somme. Then, the load resistor RL must decrease to not destroy the bias conditions of the switching pair. It follows that the conversion gain will be improved as shown in Eq 5: Gc

2

g

g

R

m Bld L Eq 5 S m RF From Fig. 12 presenting the new conversion gain curve as a function of RL and Wp the PMOS transistor width, and for the same RF stage transistor’s width and bias current, it can be seen that gain increases with the increase of RL. However, gain is less sensitive to the variation of Wp. On the other hand, increasing Wp can deteriorate linearity given that PMOS transistors introduce some distortion to the circuit [11]. Moreover, equations Eq 1 and Eq 3 show that an increase in the RF stage transconductance, by increasing the total width of this stage given by the somme WRF+Wp degrades the linearity and increases the noise figure. Consequently, we do not find it beneficial to increase Wp. Then, after cycles of simulation using the “tune parameter” ADS command, optimised results are obtained for Wp equal to 40 Pm and RL=310 :.

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Fig. 14. Linearity simulation (third approach) Table. 4. Simulated noise figure (third approach)

B. Discussion Table 5 contributes to a performance comparison of the three approaches studied above. The ISM band downconversion mixers were designed using a 0.35ȝm CMOS process. The first structure composed by the Gilbert cell provides a low linearity, low noise figure and a moderate conversion gain. Since a higher linearity is required, the second approach based on the source degeneration technique was carried out. However, this method leads to unsatisfactory

2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

results since improvement in linearity is accompanied by degradation in term of conversion gain and noise figure. In fact, the effectiveness of this approach is related to the frequency. For example, at 900 MHz the degradation of conversion gain and improvement of linearity for reasonable inductance’s size are limited [12]. It becomes more effective at higher frequencies. Moreover, inductances with silicon substrate have weak quality factors Q, which is about 2 to 3. For Q of 2.5, for example, an inductance of 5 nH at 900 MHz would have a series resistance of approximately 10 Ÿ. Then, to obtain optimised results we use the currentreuse bleeding technique witch allows a conversion gain improvement of about 4.5 dB for the same power consumption of 15 mW. With this technique it is also possible to improve the circuit linearity of about 4.25 dBm compared to Gilbert cell linearity. Concerning the noise contribution there is no significant effect on the total mixer noise figure.

the inductive source degeneration and the current-reusebleeding technique. Future work will be focused on generating the layout of the mixer and optimising parasitic component in order to meet mixer’s specifications.

REFERENCES [1] [2]

[3]

[4]

Table. 5. Comparison of results of overall approaches [5] Parameter Conversion gain (dB) Linearity (dBm) Noise Figure (dB)

First approach 11.3

Second approach 8

Third approach 12.5

-14.5

-10.5

-10.25

8.8

10.4

9.7

[6]

[7]

V. Conclusion

[8]

This paper describes the simulation results of a Mixer working at 863–870 MHz band. Parameters of this mixer are optimised so they meet the low power and the low cost receiver specifications. Lowering power is also achieved through the use of the current-reuse bleeding topology with the Gilbert cell. This addresses for CMOS technology and allow a highly integrated single chip solution. The performances obtained are very satisfactory in terms of noise and gain. However, the linearity is lower than the value specified. We can improve this value but on the other hand we will degrade the conversion gain.

[9]

[10] [11]

[12] [13]

Table. 6. Comparison with recent published mixers [14] Parameter

specification

[10]

[13]

[14]

863-870

This work 863-870

Frequency (MHz) Gc (dB) CP1dB (dBm)

900

1300

960

12 -9

12.5 -10.25

13

9.74

17 5.5 (IIP3) 11

11.7 -12

NFSSB (dB)

4 -1.6 (IIP3) 11.2

Consumption (mW)

---

15

12

14

18

10.1

Compared to recently published mixers [10], [13] and [14] using the same technology, results are in a good agreement in term of gain and noise figure. Linearity and gain should be improved by combining the two techniques:

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A. A. Abidi, “CMOS wireless tranceivers: The new wave,” IEEECommun. Mag., vol. 37, pp. 119–124, Aug. 1999. Electronic Communications Committee (ECC), “Strategic plans for the future use of the frequency bands 862-870 Mhz and 24002483.5 Mhz for short range devices”, the European Conference of Postal and Telecommunications Administrations (CEPT), Helsinki, may 2002. James Chang, “An Integrated 900 MHz Spread-Spectrum Wireless Receiver in 1-μm CMOS and a Suspended Inductor Technique”, Electrical Engineering Department, University of California, Los Angeles, CA 90095-1594, March 1998. H. Trabelsi, Gh. Bouzid, Y. Jaballi, L. Bouzid, F. Derbel and Mohamed Masmoudi," System level design of a low power, short Range FHSS transceiver for Wireless sensor", forth international conference JTEA 06, May 2006. H. Trabelsi, Gh. Bouzid, Y. Jaballi, L. Bouzid, F. Derbel and Mohamed Masmoudi, "A 863-870-MHz spread-spectrum direct Conversion receiver design for wireless sensor", first international Conference DTIS 06, September 2006. John Rogers, Calvin Plett, Radio-Frequency integrated circuit Design, Artech House Boston London, chapter 7, pp.217-243, 2003. Hanen Thabet, Hatem Trabelsi, Mohamed Masmoudi and Faouzi Derbel, "A 3-V, 863-870 MHz Low Noise Amplifier for wireless sensor", Fourth IEEE International Multiconference on Systems, Signals and Devices SSD07, Hammamet, 19-22 March 2007. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, pp.217-243, 2001. T.M. Terrovitis and R. G.Meyer, ”Noise in Current-Commutating CMOS Mixers”, IEEE Journal of Solid-State Circuits, vol. 34 n°6, June 1999. S.G. Lee and J.-K. Choi, “Current-reuse bleeding mixer”, Electronics Letters, Vol.36, Issue 8, pp. 696 – 697, 2000. V. Videjkovie, J. Vander Tang, A. Leeuwenburgh and A. V. Roermund, “mixer topology selection for a 1.8-2.5 GHz multistandard front-end in 0,18 Pm CMOS”, International Symposium on Circuits and Systems (ISCAS 2003), vol. II, pp. 300-303, 2003. A.A. Abidi, " RF CMOS Cames of Age", IEEE Journal of SolidState Circuits, vol.39, no 4, April 2004. F. Svelto, S. Deantoni, G. Montagna, R. Castello, "Implementation of a CMOS LNA plus Mixer for GPS applications with no external components", IEEE Transactions on Very Large Scale Integration Systems, vol. 9, no 1, February 2001. S. Douss, F. Touati and Mourad Loulou, "Design Optimization Methodologie of CMOS Active Mixers for Multi-Standard Receivers", International Journal of Electronics, Circuits and Systems, vol.2, no 1, 2007.