Development and Implementation of C4NP Technology for 300 mm Wafers Ajay P. Giri, Eric D. Perfecto, Hai P. Longworth, Krystyna W. Semkow, Sarah H. Knickerbocker IBM Systems & Technology Group (STG) 2070 Route 52, Hudson valley Research Park Hopewell Junction, N.Y.12533. Tel: (845-894-6194), email:
[email protected] Abstract Considerable work is ongoing worldwide on developing lead-free solutions for electronics industry to meet the needs of RoHs requirements. This paper describes the development and implementation of lead-free C4 interconnects for 300 mm wafers using, C4NP technology at IBM with equipment partnership with Suss MicroTech Inc. Key process modules of C4NP technology are: (a) UBM pads fabrication using simple unit processes in back end of the line semiconductor manufacturing facility, (b) Solder melt filling of glass molds with cavities in solder fill tool and inspection, (c) C4 bump transfer to UBM pads on wafers using vaporized flux process in solder transfer tool, (d) Final inspections and electrical tests. This process technology for C4 bumping eliminates the need for solder or solder alloy plating and provides wider latitude for selecting solder composition. For example, solders can be selected for improved mechanical properties and, or low alpha emission requirements. This can be accomplished by simple changing of mold fill head. Primary efforts of this study are focused on four key elements: (1) Development of unit processes for UBM pad patterning and solder transfer processing, (2) Chip / organic laminate module builds, using industry standard bond and assembly processes, (3) Selection of specific test vehicle wafers with 200 um pitch pads and over 1.25 million C4 bumps, and (4) Extensive reliability testing of modules with JDEC and IBM internal standards. Modules with test vehicle chips as well as product chips have shown excellent reliability data, comparable to that of high lead electroplated C4 bumps [1], and meet application requirements. In order to assess manufacturing robustness and yields, sector partitioning studies were undertaken to understand the effects of unit process windows and defect densities. Results show that C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Technology qualification studies have been successfully completed. Thus, enabling the path for manufacturing ramp up. This technology is extendable to higher density C4 interconnects and product qualifications studies on C4 bumps on 150 um pitch are ongoing. IBM is adapting this technology for 300 mm lead-free applications.
Table 1: Overview of Typical Application Conditions Up to 5000
Ambient Operating Temp.(C)
-40 to +100
Machine Ambient Temp. (C)
22 / 45
Storage Temp. (C)
-40 to +125
Device Junction Temp. (C)
-55 to +125
Chip Tj (C) Nominal / Maximum
60 / 125
Average Current (mAmp) / C4
20 - 100
Power-On-Hours (Nom.) KHrs
40 - 100
Typical # of Power / Ground C4s
2000
C4 Bump pitch (microns)
200 or 150
Chip Size (mm / edge)
4.0 – 18.7
reliability products which can meet increased needs of customers and end users. For example, current trends of increasing clock frequencies, and power, also pose increasing demands on material performance. Table 1 provides the typical application and usage requirements for current and projected next generation products. Typical application needs as shown above dictates careful product design and material selections. For given range of application conditions, suitable bump dimensions can be selected with help of FEM modeling and analysis of C4 interconnects, for example, in this study, C4 bumps at 200 um pitch ground rules, UBM pad sizes of 110 +/-10 um and bump heights of 70-90 um were selected. Solder materials can be selected on the basis of desired thermo-mechanical and fatigue properties of either Tin based binary or ternary alloys or other solders with four or five components [4, 5]. Electroplating through dry or wet resists was pioneered by IBM in early nineties [6]. This processing method is widely used in the industry for high lead C4 bump fabrication. However, for lead free solders, electroplating methods provide limited range and controls over the compositions that can be plated in manufacturing lines. To address these limitations for choice of solder materials, IBM has been developing C4NP technology [7, 8]. One of the key advantages of C4NP technology is that a wider range of solder compositions and solder alloys can be used in environmentally friendly, so called “Green”, manufacturing setups without complexity and costs associated with chemical waste disposals. Other technical advantages of C4NP, manufacturing simplicity and comparisons to other solder deposition methods have been discussed elsewhere [9, 10]. This paper discusses development and manufacturing implementation efforts on lead-free C4 interconnects for 300 mm wafers.
Introduction: As advances in silicon technology continues to follow Moore’s law, circuit densities on die need increasing number or Flip chip (C4) interconnects on tighter pitches. Also, worldwide drive for compliance to RoHS guidelines is creating urgency for lead free solutions for electronic industry. Over the last several years, work published by many researchers and NIST led consortiums, [2, 3] have highlighted materials challenges and reliability concerns for developing lead-free solutions, and their manufacturing implementation, particularly for high performance and high
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C4 NP Technology and Process Modules: Flow chart shown below describes the key process modules for C4NP technology. Mold and transfer modules are new elements, shown in light blue & yellow. Other modules shown in purple are standard processes and operations in manufacturing line. This report focuses on UBM Capture pad build, Solder transfer process and diagnostics/yield learning and reliability testing. UBM Capture Pad Build Wafers
Unit Process developments and integration: (A) Capture Pad Process: Wafers incoming to C4 bumping process, are typically coated with polyimide films (2-5 um thick) with via openings to final metal pads of aluminum. Polyimide via wall angles range from 45-75 degrees. To ensure adequate coverage of polyimide vias, sputter deposition process as well as seed metal thicknesses were optimized. Criteria were to achieve desired microstructure for TiW/Cu films, lower stress of composite film stack and adequate adhesion. After sputtering of seed layer TiW (0.16 um) and Cu (0.45um), wafers are processed through several steps to define capture pads. First step involves lamination of dry resist films to wafers. Dry plating resists compatible with nickel and copper electroplating baths and etch chemistries are suitable. After optimal expose and develop process, resist openings between 100 and 120 micrometer diameter were obtained for 200 um pitch designs. Resist processing is followed by electroplating of nickel from a nickel sulfamate bath. Thickness of nickel barrier between 1.0 and 2.5 um was found to be adequate for multiple solder reflow requirements during assembly processing steps. Nickel electroplating is followed by copper electroplating from a copper sulfate bath. The resist is stripped in a bath containing potassium hydroxide solution or organic stripper. Copper seed layer is then etched off in ammonium per-sulfate bath. During copper seed etching, electroplated copper is exposed to copper etchant and etches during this step; therefore, thickness of electroplated copper must accommodate a ‘sacrificial’ copper layer. A maximum copper thickness specification of 2.0 um after copper seed etch was defined. It allowed full consumption of copper by tin during solder transfer and post transfer reflows, and prevented formation of voids at copper surface. Kikendall voids at Cu3Sn intermetallic layer are usually seen with very thick Cu films. The TiW etch process follows the copper seed etch. It consists of peroxide type, proprietary to IBM, etch chemistry. Both, copper etch and TiW etch processes were demonstrated to produce low undercut (
