IEICE TRANS. ELECTRON., VOL.E90–C, NO.4 APRIL 2007
836
INVITED PAPER
Special Section on Low-Power, High-Speed LSIs and Related Technologies
Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations Toshiro HIRAMOTO†a) , Member, Toshiharu NAGUMO† , Tetsu OHTOU† , and Kouki YOKOYAMA† , Nonmembers
SUMMARY The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-bodyfactor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed. key words: SOI, body factor, body effect, FinFET, multigate MOSFET
1.
Introduction
The size of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been miniaturized for more than 35 years to attain higher speed, lower power consumption, higher integration, and lower cost. The gate length of the state-of-the-art complementary MOS (CMOS) transistors is now less than 35 nm. The device size will be further scaled down to achieve higher performance of very large-scale integrated circuits (VLSIs). Figure 1 shows the future technology nodes and gate length predicted by the International Technology Roadmap of Semiconductors (ITRS) [1]. It is predicted that the gate length will become less than 10 nm in 2016. Future information technologies will be still more improved thanks to the advancements in VLSIs. However, it is now well recognized that simple scaling of bulk MOSFETs will fail in the nanometer regime. According to the 2003 version of ITRS [1], the three major scaling challenges are (A) increasing saturation current while reducing the supply voltage, (B) controlling leakage current and short channel effects, and (C) control of device parameters across the chip and from chip to chip. Figure 2 summarizes the main approaches and possible solutions to the challenges. The main technical approaches to challenges (A), (B), and (C) above are, respectively, to (a) improve the carrier transport properties by introducing new materials, Manuscript received October 16, 2006. The authors are with the Institute of Industrial Science, The University of Tokyo, Tokyo, 153-8505 Japan. a) E-mail:
[email protected] DOI: 10.1093/ietele/e90–c.4.836 †
Fig. 1 The technology nodes and gate length of high-performance microprocessors as predicted by ITRS. The previous ITRS versions are also shown.
Fig. 2 The major challenges of device scaling and possible solutions. A combination of these technological approaches will be necessary in the nanometer regime.
(b) improve the electrostatics of MOSFETs by introducing new transistor structures, and (c) suppress the interchip and intrachip variations. There are numerous developments and research work on improving the carrier transport by using new materials (approach (a)) to solve challenge (A). One of the most promising strategies is the introduction of local strain [2] or global strain [3] in the channel of MOSFETs to enhance the carrier mobility. The possibility of utilizing new channel materials other than Si, such as Ge [4] or compound semiconductors [5] that have much higher mobility than Si,
c 2007 The Institute of Electronics, Information and Communication Engineers Copyright
HIRAMOTO et al.: DEVICE DESIGN OF NANOSCALE MOSFETS CONSIDERING THE SUPPRESSION OF SHORT CHANNEL EFFECTS
837
is also discussed. Utilizing crystal orientations other than (100) is another option [6]. Note that some new materials (high-k gate dielectrics for example) will also contribute to the suppression of the short channel effect (challenge (B)). There are also many developments and research on new transistor structures for the suppression of the short channel effect [7] (approach (b)) to solve challenge (B). Typical new structures are fully depleted (FD) silicon-on-insulator (SOI) structures and multigate transistors, which will be described in detail in the next section. Note that some of the new transistor structures will also contribute to increasing the saturation current (challenge (A)). On the other hand, various attempts have been made to suppress the interchip and intrachip variations of device characteristics [8] (approach (c)) to solve challenge (C). The interchip variations of device characteristics should be suppressed by controlling the threshold voltage (Vth ) via the back-bias voltage, and the intrachip variations may by suppressed by utilizing intrinsic-channel FD SOI transistors. All the above-mentioned challenges ((A), (B), and (C)) should be solved in future nanoscale MOSFETs. This will be accomplished by combining technical approaches (a), (b), and (c), which is the grand challenge in realizing future nanoscale MOSFETs. In this paper, we address the combination of (b) new transistor structures and (c) suppression of variations, which has not been much discussed so far. We propose two transistor architectures to achieve this combination. The key technology is the back-bias control scheme in an FD SOI transistor with an extremely thin buried oxide (BOX).
2.
New Transistor Structures with Back-Bias Voltage Control
Figure 3 summarizes the evolution of the new transistor structure designed to improve the electrostatics. A singlegate MOSFET on an SOI substrate is the simplest structure. The increase in the number of gate electrodes drastically improves the electrostatics of MOSFETs [7]. There are three arrangements for increasing the number of gate electrodes: planar type, vertical type, and FinFET type, as shown in Fig. 3. In double-gate devices, the channel is sandwiched between two gates. The three sides of the channel are surrounded by gates in triple-gate devices, and the channel is completely surrounded by the gate in gate-all-around transistors. On the other hand, post-fabrication Vth control by backbias voltage is virtually the only solution to the suppression of interchip characteristics variations [9]. In this technique, Vth is monitored after chip fabrication, and if the measured value is out of the targeted range, a substrate bias voltage (Vsub ) is applied to adjust Vth . This adaptive Vth control [10] is very effective. The sensitivity of Vth to Vsub is called the body factor γ, and γ is given by [11] γ = Csub /Cg ,
(1)
where Cg is the gate-channel capacitance and Csub is the substrate-gate capacitance. To control Vth , a sufficient value of γ is necessary, and γ is one of the most important parameters in the back-bias scheme. Unfortunately, the combination of new transistor structures on SOI and the back-bias scheme fails. This is because γ is too small because of the thick BOX layer that leads to
Fig. 3 Evolution of the new transistor structure to improve the electrostatics of a MOSFET. The electrostatics are improved as the number of gate electrodes that surround the channel increases. In the FinFET-type transistor, the current direction is perpendicular to the page sheet. In the FinFET doublegate transistor, the gate dielectric of the top of the fin is thicker and the current flows at only the right and left sides of the fin. In the FinFET triple-gate transistor, the gate dielectric of three sides of the fin is the same and the current flows at three sides of the fin.
IEICE TRANS. ELECTRON., VOL.E90–C, NO.4 APRIL 2007
838
3.
New Device Architectures
3.1 Variable-Body-Factor FD SOI MOSFET
(a)
(b)
Fig. 4 Schematics of the proposed variable-body-factor FD SOI MOSFETs. (a) Active state. The depletion region below the BOX expands in the substrate, and therefore, Csub is small and γ becomes small, resulting in higher drive current. The parasitic capacitance below the drain is also reduced. (b) Standby state. The substrate below the BOX is inverted, and therefore, Csub is large and γ becomes large, resulting in larger Vth shift, which reduces subthreshold leakage current.
Fig. 5 Schematic of the proposed multigate MOSFET with sufficient large γ.
too small Csub . If the BOX thickness is reduced in order to increase γ, the parasitic capacitance between the drain and the substrate increases, resulting in the degradation of circuit performance. Furthermore, in planar double-gate transistors or gate-all-around transistors, the value of γ is zero because the electric field due to the substrate bias is completely shielded by the gate electrode between the channel and the substrate. These are serious disadvantages of the new transistors structures on SOI substrates. Among the new transistors in Fig. 3, the single-gate FD SOI transistor and FinFET double- and triple-gate transistors have a finite value of γ. In order to overcome the disadvantages, we have proposed two new device architectures. Figures 4 and 5 show the schematics of the new device architectures. One is a variable-body-factor SOI MOSFET with an extremely thin BOX [12], [13]. This device architecture is classified into a single-gate FD SOI MOSFET. The other is a multigate MOSFET with a relatively low aspect ratio and a sufficient body factor [9], [14]. This device architecture is classified into a triple-gate FD MOSFET. The details and characteristics of the proposed device architectures are described in the next section.
The key features of this device architecture are an extremely thin BOX (typically 10 nm) and a very low substrate impurity concentration (typically 1 × 1016 cm−3 ). Depending on the substrate voltage (Vsub ), the substrate below the BOX is depleted or inverted. When the substrate below the BOX is depleted, Csub is the series capacitance of the SOI layer, BOX, and depletion layer capacitances, as shown in Fig. 4(a). On the other hand, when the substrate below BOX is inverted, Csub is the series capacitance of only the SOI layer and BOX capacitances, as shown in Fig. 4(b). Therefore, γ is modulated depending on Vsub in accordance with Eq. (1). The modulation of γ is greater when the BOX is thinner and the substrate impurity concentration is lower. The basic operation principle is described below. In the active mode, a slightly positive Vsub is applied. Then, the substrate below BOX is depleted and a small γ is obtained (Fig. 4(a)). We can also obtain higher drive current because the vertical electric field is lower due to a small γ. The parasitic drain capacitance is also reduced due to the depletion layer below the drain, and therefore, a higher circuit speed can be obtained. In the standby mode, negative Vsub is applied. Then, the substrate below the BOX is inverted, as shown in Fig. 4(b). Then, Csub is given by the series capacitance of only the SOI layer and BOX capacitances. Therefore, Csub is large and γ becomes larger, and we can obtain large Vth shift, which results in the suppression of standby current. Accordingly, in variable-body-factor FD SOI MOSFETs, both subthreshold leakage suppression and higher speed can be achieved at the same time. The validity of this device architecture has already been confirmed by the device simulation of a long-channel device [12]. The higher circuit speed due to suppressed parasitic drain capacitance in a short-channel device has also been confirmed by simulation [13]. The fabrication and measured data will be discussed below. Figure 6 shows a schematic of the n-type device structure we have fabricated. This is a long-channel device. The experimental dc characteristics and circuit speed of shortchannel devices have been reported elsewhere [15]. The fabrication process is almost the same as that of normal MOSFETs except that we must prepare an extra side electrode (an n+ region for NMOS) that is used to provide the inversion charges to the substrate immediately. The extra electrode is connected to the substrate. In the fabrication, n+ regions are also formed below the source and drain regions because of the very thin SOI and thin BOX, as shown in Fig. 6. Figure 7 shows measured Id -Vg characteristics of the fabricated n-type device. Vsub is varied at constant intervals. It is found that the Vth shift is not constant, suggesting that γ is modulated. Figures 8 and 9 show the measured Vsub dependences of Vth and γ, respectively. The simulation results
HIRAMOTO et al.: DEVICE DESIGN OF NANOSCALE MOSFETS CONSIDERING THE SUPPRESSION OF SHORT CHANNEL EFFECTS
839
Fig. 6 Schematic of variable-body-factor FD SOI MOSFET we fabricated.
Fig. 9 Measured Vsub dependence of γ of the fabricated variable-bodyfactor FD SOI MOSFET. The simulation results are also shown.
Fig. 7 Measured Id -Vg characteristics of the fabricated n-type device. Vsub is varied at constant intervals.
Fig. 10 Measured Vsub dependence of the S factor of the fabricated variable-body-factor FD SOI MOSFET. The simulation results are also shown.
Figure 10 shows the measured Vsub dependence of the subthreshold factor S . It is very interesting to note that the behaviors of γ in Fig. 9 and S in Fig. 10 are very similar. This is because S in a long channel device is determined by Csub and is given, at room temperature, by [11] S = 60(1 + Csub /Cg ) = 60(1 + γ). Fig. 8 Measured Vsub dependence of Vth of the fabricated variable-bodyfactor FD SOI MOSFET. The simulation results are also shown.
assuming the same device parameters as those of the fabricated device are also shown. The slope of Fig. 8 corresponds to γ. It is clearly observed that γ is modulated around Vsub = 0 V. When Vsub < −1 V, a large γ is obtained because the substrate is inverted and Csub is large. When Vsub is around 0 V, γ becomes small because the substrate is depleted and Csub is small. On the other hand, when Vsub > 1 V, a much larger γ is obtained. This is because the substrate is accumulated (large Csub ) and the back channel of the SOI/BOX interface is inverted (small Cg ), although this region is not used for practical applications.
(2)
Therefore, there is a close relationship between γ and S . Almost identical behaviors in Figs. 9 and 10 clearly indicate that the modulation of γ is caused by the modulation of Csub . A slight degradation of S in measured data compared with simulation results may be caused by the interface traps in the fabricated MOSFET. Finally, measured Ion-Ioff characteristics are shown with the simulation results in Fig. 11. In the simulation, Type A is the case of device parameters identical to those of the fabricated device, while Type B is the case of the same parameters except for a very high substrate impurity concentration (1 × 1020 cm−3 ), as a result of which the depletion layer does not expand and γ is not modulated. The data are obtained from a p-type MOSFET with a BOX thickness of 50 nm. In the standby state where the substrate is inverted,
IEICE TRANS. ELECTRON., VOL.E90–C, NO.4 APRIL 2007
840
4.
Fig. 11 Measured Ion-Ioff characteristics of the fabricated variablebody-factor FD SOI MOSFET. The simulation results are also shown. In the simulation, Type A is the case of device parameters identical to those of the fabricated device, while Type B is the case of the same parameters except for a very high substrate impurity concentration (1×1020 cm−3 ), as a result of which the depletion layer does not expand and γ is not modulated.
the measured Ion-Ioff curve is similar to that of Type B. It is interesting to note that when Vsub increases and the substrate is depleted, the measured Ion suddenly increases with almost constant Ioff. This is because the vertical electric field is reduced owing to substrate depletion and the mobility increases. As a result, the high current drive and suppression of leakage current in the proposed device architecture are confirmed. 3.2 Multigate MOSFET with Sufficient γ To suppress the short channel effect more sufficiently, a multiple gate structure must be introduced in the nanoscale regime. However, γ of FinFET double-gate or triple-gate MOSFETs is generally much smaller than that of the singlegate FD SOI MOSFET, because the channel is formed far above the Si/BOX interface, resulting in smaller Csub . Furthermore, the channel is surrounded by the gate, and hence, Cg is large, resulting in even smaller γ. A special design is necessary to obtain sufficient γ in the FinFET double-gate or triple-gate MOSFETs. A schematic of the proposed structure is shown in Fig. 5 [9], [14]. The features of this structure are a relatively low aspect ratio of the Si channel (typically less than unity) and an extremely thin BOX (typically less than 10 nm). It has been shown by three-dimensional device simulation that there is a design window to meet the requirements of small S (less than 80 mV/dec) and large γ (larger than 0.05), assuming the same parameters as those of the low-standby-power devices in the 45 nm technology nodes [14]. Although this device architecture has lower drive current than a multigate device with a high aspect ratio, the post fabrication control of device characteristics, can be achieved, which is more important than having a high drive current in the nanometer regime.
Conclusions
Device design of future MOSFETs in the nanometer regime is discussed in terms of new transistor structures and backgate voltage control. Two new device architectures are proposed. In the variable-body-factor FD SOI MOSFETs, the body factor is modulated in accordance with substrate bias voltage, and high circuit speed in the active state and low power in the standby state can both be achieved. In the multigate MOSFETs with low aspect ratio, suppression of the short channel effect and a sufficiently large body factor can be obtained at the same time. The consideration of not only the suppression of the short channel effect but also the controllability of the device characteristics will be crucial in future nanoscale device design. Acknowledgements This work was supported in part by the program for the “Promotion of Leading Researches” in the Special Coordination Funds for Promoting Science and Technology from the Ministry of Education, Culture, Sports, Science and Technology in Japan. The device simulator (MediciTM ) has been supplied through VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys Inc. References [1] International Technology Roadmap of Semiconductors (ITRS) http://public.itrs.net/ [2] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” Technical Digests of International Electron Devices Meeting (IEDM), pp.978–980, 2003. [3] S. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe, N. Hirashita, and T. Maeda, “Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs,” Technical Digests of International Electron Devices Meeting (IEDM), pp.57–60, 2003. [4] T. Tezuka, S. Nakaharai, Y. Moriyama, N. Hirashita, E. Toyoda, N. Sugiyama, T. Mizuno, and S. Takagi, “A new strained-SOI/GOI dual CMOS technology based on local condensation technique,” Technical Digests of VLSI Technology Symposium, pp.80–81, 2005. [5] S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T.J. Phillips, D. Wallis, P. Wilding, and R. Chau, “85 nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications,” Technical Digests of International Electron Devices Meeting (IEDM), pp.783–786, 2005. [6] G. Tsutsui, M. Saitoh, and T. Hiramoto, “Experimental study on superior mobility in (110)-oriented UTB SOI pMOSFETs,” IEEE Electron Devices Lett., vol.26, no.11, pp.836–838, 2005. [7] H.-S.P. Wong, D.J. Frank, P.M. Solomon, C.H.J. Wann, and J.J. Welser, “Nanoscale CMOS,” Proc. IEEE, vol.87, no.4, pp.537–570, 1999.
HIRAMOTO et al.: DEVICE DESIGN OF NANOSCALE MOSFETS CONSIDERING THE SUPPRESSION OF SHORT CHANNEL EFFECTS
841
[8] T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, “A 0.9 V, 150-MHz, 10-mW, 4 mm2 , 2D discrete cosine transform core processor with variable thresholdvoltage (VT) scheme,” IEEE J. Solid-State Circuits, vol.31, no.11, pp.1770–1779, 1996. [9] T. Hiramoto, T. Saito, and T. Nagumo, “Future electron devices and SOI technology—Semi-planar SOI MOSFETs with sufficient body effect,” Jpn. J. Appl. Phys., vol.42, no.4B, pp.1975–1978, 2003. [10] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” Digests of International Solid-State Circuits Conference (ISSCC), pp.422–423, 2002. [11] T. Hiramoto and M. Takamiya, “Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias,” IEICE Trans. Electron., vol.E83-C, no.2, pp.161–169, Feb. 2000. [12] T. Ohtou, T. Nagumo, and T. Hiramoto, “Variable body effect factor fully depleted silicon-on-insulator metal oxide semiconductor field effect transistor for ultra low-power variable-threshold-voltage complementary metal oxide semiconductor applications,” Jpn. J. Appl. Phys., vol.43, no.6A, pp.3311–3314, 2004. [13] T. Ohtou, T. Nagumo, and T. Hiramoto, “Short channel characteristics of variable body factor FD SOI MOSFETs,” Jpn. J. Appl. Phys., vol.44, no.6A, pp.3885–3888, 2005. [14] T. Nagumo and T. Hiramoto, “Design guideline of multi-gate MOSFETs with substrate bias control,” IEEE Trans. Electron Devices, vol.53, no.12, pp.3025–3031, 2006. [15] T. Ohtou, T. Saraya, K. Shimokawa, Y. Doumae, Y. Nagatomo, J. Ida, and T. Hiramoto, “Experimental demonstrations of superior characteristics of variable body-factor (γ) fully-depleted SOI MOSFETs with extremely thin BOX of 10 nm,” International Electron Devices Meeting (IEDM), pp.877–880, 2006.
Toshiro Hiramoto received B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo in 1984, 1986, and 1989, respectively. In 1989, he joined Device Development Center, Hitachi Ltd., Ome, Japan, where he was engaged in the device and circuit design of ultra-fast BiCMOS SRAMs. In 1994, he joined Institute of Industrial Science, University of Tokyo, Japan, as an Associate Professor. He was also an Associate Professor in VLSI Design and Education Center, University of Tokyo, from 1996 to 2002. He has been a Professor in Institute of Industrial Science, University of Tokyo since 2002. His research interests include low power and low voltage design of advanced CMOS devices, SOI MOSFETs, device/circuit cooperation scheme for low power VLSI, quantum effects in nano-scale MOSFETs, and silicon single electron transistors. Dr. Hiramoto is a member of IEEE and Japan Society of Applied Physics. He has been an Elected AdCom Member of IEEE Electron Devices Society since 2001. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003, and the Program Chair in 1997, 1999, and 2001. He also served on Program Subcommittee on Integrated Circuits of IEEE International Electron Devices Meeting (IEDM) in 1993 and 1994 and on Program Subcommittee on CMOS Devices of IEDM in 2003 and 2004, and has served on Program Committee of Symposium on VLSI Technology since 2001. He was the Subcommittee Chair of CMOS Devices of IEDM in 2005. He is the Asian Arrangement Co-Chair of IEDM in 2006 and 2007.
Toshiharu Nagumo received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 2001, 2003, and 2006, respectively. He was engaged in research on multi-gate MOSFETs and the body effect for low-power LSIs. In 2006, he joined NEC Corporation, Sagamihara, Japan. He is currently working on research and development of advanced CMOS technologies.
Tetsu Ohtou received the B.S. degree in environmental information from Keio University, Fujisawa, Japan, in 2002 and the M.S. degree in electronic engineering from University of Tokyo, Japan, in 2004. He is currently working toward the Ph.D. degree at University of Tokyo. He is currently engaged in studies on the fully depleted SOI MOSFETs with an extremely thin BOX, and particularly on their back-bias effect.
Kouki Yokoyama received the B.S. and M.S. degrees from Chuo University, Japan, in 2004 and 2006, respectively. He was also with the Institute of Industrial Science, University of Tokyo, Japan. In 2006, he joined Canon Inc., Tokyo, Japan.
