Digital Control of a Three Phase 4 Wire PWM Inverter for PV Applications Said El-Barbari and W. Hofmann CHEMNITZ UNIVERSITY OF TECHNOLOGY Department of Electrical Machines and Derives D-09107 Chemnitz, Germany Tel: ++49 371 531 3319 / Fax: ++49 371 531 3324 e-mail:
[email protected] URL: http://www.infotech.tu-chemnitz.de/~ema/staff/el-barbari.html Keywords: Control, Design, Harmonics, Simulation, Three phase system, Renewable energy system, Solar cell system, UPS
ABSTRACT The Microcontroller based digital control of a three phase 4 wire PWM inverter for simultaneously supply of three phase and single phase load in transformerless stand alone photovoltaic application with battery energy storage (BES) and LC output filter is described. An observer is implemented to estimate the load current and to predict the space states for one step ahead. A control method based on the dead beat control algorithm is described to regulate the output voltage of the LC filter so that disturbance of the output voltage due to load unbalances is eliminated. Simulation results for various operation conditions are presented to verify the validity of the control method. PV G e n e r a to r
D C /D C 2
B a ttery Storage
DC
D C /D C 1
DC L in k
3Φ 4 W ire In v e r t e r
O u tp u t F ilte r
DC
DC S DC
LC F ilte r
L oad
AC
DC
Z in t
Fig.1: stand alone photovoltaic system with 3 phase 4 wire PWM voltage source inverter In the system illustrated in figure 1 this is provided by the DC/DC2. In this way the battery will be always charged at the Maximum Power Point. The goal of the system illustrated in figure 1 is to supply three as well as single phase loads of any art with constant amplitude sinusoidal voltage and constant frequency. For this propose the neutral point of the LC output filter and load is connected to the midpoint of the DC link capacitor bank. Due to load unbalances an intruding current flows throw the impedance between the neutral point and midpoint and a voltage drop occurs which distorts the symmetrical output voltage. To solve this problem the following measurements were taken • a zero sequence current and voltage control is implemented • a DC/DC converter is used to control the DC link voltage according to load unbalances In this way the symmetry of the output voltage is achieved and the linear region of the PWM
1. INTRODUCTION Nowadays more attention is paid to PV systems and their related technology for domestic applications as well as in large central power stations. PV systems are advantageous because they are abundant, pollution free and distributed through the earth. The only draw back is that the initial installation cost is considerably high. Since the power generated by an array of PV panels is direct-current, it may be transformed, either into a power with constant voltage for dc applications or into ac power. In both cases it is important to draw as much energy as possible from the PV panel. The output power of PV generators vary extensively with the weather conditions such as solar insulation, temperature and cloudy skies. To obtain the maximum power from such an array under any weather condition, it is necessary to connect the PV array to a converter that can adapt itself to the changing V-I characteristic of the PV generator (MPPT).
1
modulator of the DC/AC VSI (Voltage Source Inverter) is extended. For three phase inverters the dead beat control based on space vector was discussed in [3]. In [4] the disturbance observer, state variable observer and the dead beat control were combined to improve the transient and overall behaviour of the system. The digital control of the current minor loop for UPS applications to achieve quick and exact current response and to provide low THD of the output voltage waveform was described in [5]. The decoupling dead beat control of three phase inverter in dq-frame was explained in [1] and [2]. In [1] the voltage and current equations were discretised separately, thus the final discrete inverter model is simplified whereas in [2] the voltage and current equations were combined during the discretisation and thus a precise full inverter discrete model is provided. In this paper the dead beat control in [1] and [2] is adopted and extended to match for three phase four wire VSI. In addition, an observer is also implemented. The observer has the following tasks. • Estimation of the load currents which act as disturbance on the plant •
R vd
w
2Cb
Zw Zv Zu
id-
vN 0
vu
vCu
iN 0
RN0
Fig.2: main circuit
C
L
d
V = I − IL dt C d dt
vN 0 = RN 0 (iu + iv + iw ) R
iu vu
(2)
I = −IR + V − VC − v N 0
where
L
(3) (4)
iLu
≈ ≈
C
≈
vN0
vCu
≈
Fig.3: average model of three phase four wire inverter with output LC filter The block diagram of phase u is illustrated in figure 4. The block GPWM describes the nonlinear behaviour of the PWM modulators. As it can be seen from this figure, the reference voltages of all three phases must stay within the linear region. In the conventional three phase inverter with balanced load and without fourth wire neutral connection the linear region will never be exceeded because the average of vN 0 = (d u + d v + d w )vd / 6 is equal zero. Whereas in three phase four wire inverter with unbalanced load the average value of vN0 in equation (4) is not equal zero, therefore the control output du must increase to compensate this value.
Figure 2 illustrates the basic circuit of the VSI. The reference vector to be synthesised by the SPWM (Sinus Pulse Width Modulation) is given by the output of the control loop. For three phase four wire PWM inverter, the voltages and currents can be obtained by using the average circuit model of fig. 2 shown in figure 3. In figure 3 the voltages and the currents are given by
V = [vu vv vw ] , VC = [vCu vCv vCw ] , T
I = [iu iv iw ] , I L = [iLu iLv iLw ] , T
du
T
where V = vd / 2 ⋅ d
iLu
C
In system proposed the neutral point of the output LC filter and the load are connected directly to the midpoint of the capacitor bank.
d = [d u d v d w ]
iu
v
Vb
2. SYSTEM MODELING
T
L
u
2C b Rb
One step ahead prediction of the VSI voltages and currents
T
i d+
ib
vu
Vd 2 Ad
(1)
iLu
vN0
GPWM
1 sL+R
iu
1 Zu 1 sC
vCu
Fig.4: block diagram of the sine PWM inverter
and du ,dv and dw are the line to neutral duty cycles. The voltages and currents equations of the inverter and the output filter are given by
This component is the main reason for the saturation of the PWM modulator and therefore it must stay within a certain region [9].
2
From the figure one can see that a low voltage ripple (ku
