Digital dual-loop DLL design using coarse and fine loops

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Digital dual-loop DLL design using coarse and fine loops

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Jul 30, 2002 - U.S. Patent. Aug. 10, 2004. Sheet 6 6f 20. US 6,774,690 B2. 0* .0E. 30x40 c530. 3830. @0269: 38:0 Evjo. 58:0. 295. 5:0 ...

US006774690B2

(12) Unlted States Patent

(10) Patent N0.:

Baker et al.

(45) Date of Patent:

(54) DIGITAL DUAL-LOOP DLL DESIGN USING

(56)

(73)

U_S_ PATENT DOCUMENTS

Inventors: R. Jacob Baker, Meridian, ID (US);

5,109,394 A

Feng Lin, Boise, 1]) (Us)

5,355,037 A

Assigneez Micron Technology’ Inc” Boise, ID (Us)

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Primary Examiner—Dinh T. Le

Prlor Pubhcatlon Data

(74) Attorney, Agent, or Firm—SchWeg1nan, Lundberg, Woessner & Kluth, PA

(57) Related US. Application Data

ABSTRACT

A dual-loop digital delay locked loop (DLL) is provided.

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References Cited

COARSE AND FINE LOOPS (75)

US 6,774,690 B2

The DLL includes a coarse loop to produce a ?rst delayed signal and provides a Wide frequency lock range. The DLL further includes a ?ne loop connected to the coarse loop to

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produce a second delayed signal and provides a tight lock ing. This dual-loop architecture can provide robust operation

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