Digitally Controlled Low-Harmonic Rectifier Having Fast Dynamic Responses Aleksandar Prodic, Jingquan Chen, Robert W. Erickson and Dragan Maksimovic Colorado Power Electronics Center Department of Electrical and Computer Engineering University of Colorado at Boulder Boulder, CO 80309-0425, USA
[email protected] Abstract – This paper describes a completely digitally controlled low-harmonic rectifier. It is shown that the dynamics of the outer voltage loop can be significantly improved using a digital notch filter. Low input current harmonics and fast voltage response are experimentally verified using a 200W universal-input boost power supply operating at the switching frequency of 200KHz.
A typical power-factor-corrected rectifier based on a boost converter is shown in Fig.1. Current loop is designed so that the converter input current follows the waveform of the input voltage. In the ideal case these two waveforms have the same waveshape and are in phase: thus the rectifier presents a resistive load to the system. The outer loop regulates the voltage across the energy-storage capacitor. This voltage always has ripple at twice the line frequency 2 L. To maintain low input current harmonics output of the voltage regulator u(t) must not have significant line frequency harmonics [9]. Consequently, to avoid distortion of the ac line current through feedback, the capacitor voltage ripple in conventional designs the bandwidth of the voltage loop is limited to frequencies significantly lower than the line frequency (typically 1020Hz). In Section II design of a high-performance digitallycontrolled PFC rectifier that provides very low distortion of input current is described. Section III presents a technique that improves transient response of the output voltage. Several approaches to improving the dynamic response of the voltage loop in analog PFC controllers have been proposed [10-13]. The method presented here is based on implementation of a digital notch filter in the feedback loop. Additionally, the problem of the controller design to obtain fast voltage loop is addressed. Finally, experimental results and conclusions are given.
I. INTRODUCTION Digital controllers offer advantages over analog controllers such as flexibility, additional processing options, low sensitivity to external influences (aging, temperature variation) and less expensive manufacturing. In the past, digital controllers were considered slower than analog controllers. Also, digital control was restricted to relatively high-power applications owing to high cost of digital signal processors. In recent years use of digital controllers is increasing even in low-to-medium power applications [1-7]. The purpose of this paper is to describe a simple and efficient method for implementation of a digital controller for a PFC (power factor correct) rectifier that exhibits very low harmonic distortion of the input current and extended bandwidth of the outer voltage loop. As a test bed an evaluation board based on Analog Devices processor ADMC401 [8] was used for implementation. This structure shows that a complete controller can be implemented with a fairly simple dedicated hardware structure based on 8-bit digital arithmetic. vg(t)
L +
Input Line Voltage 85-260Vrms 50-60Hz
C
vou(t)
Load
-
ig(t)
-
K
+
KVg(t)
+
Current Loop Regulator
HVout(t)
ei(t) ev(t)
Voltage Loop Regulator
Multiplier
u(t)
Fig.1. PFC rectifier based on a boost converter This work was supported by Phillips Research through the CoPEC (Colorado Power Electronics Center). The authors would like to thank Analog Devices for providing Development Kits used in the experiment.
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H
PWM and driver
Rsig(t)
476
-
+
+ Vref
II. DIGITAL PFC CONTROLLER
the transition, and to obtain values approximately equal to the average of input current during one switching cycle the sampling instants are selected using adjustable delay tD from the time when the switch is turned on. This delay depends on the current discrete duty cycle value d[n] as follows:
Fig.2 shows the block diagram of a complete digital controller for a 200 W boost-based PFC operating in continuous conduction mode at a switching frequency of fs= 1/T s= 200 kHz. It is designed for universal input (ac line voltage between 85 and 260 V,rms) and the DC output voltage is regulated at 385 V.
tD
d [ n] Ts if d[n] 2
tD
1 d [ n] Ts if d[n] < 0.5 2
Selection of switching frequency and resolution of digital pulse width modulator (DPWM) In the design of digital controllers for switching converters, a trade off exists between resolution of the digital pulse width modulator (DPWM) and the operating frequency. To obtain smaller components and faster control, it is desired to operate the converter at higher switching frequency. As the switching frequency increases, the resolution of a conventional DPWM whose design is based on a counter decreases [8]. This type of DPWM is often used for digital control of switching converters. Hence, to maintain good resolution of the DPWM, the switching frequency is usually restricted to low values. In this design we decided to use a DPWM whose resolution is only 6 bits. This choice allows operation at a high switching frequency, with consequent implementation of a high-bandwidth current regulator using a simple computational unit. In the prototype system, 8-bit arithmetic for the computational unit and analog-to-digital converters is used; this choice contributes to our objective of implementing a high-performance PFC using relatively simple hardware structure.
To find dependence of the input current on the control variable (duty cycle variation d(t), Ig(t)
L
Ts
+
Vg(t)
+
(1-d(t))Vout
Ts
Fig.3 Linearized model describing boost converter input characteristics
the average model of Fig.3 is employed [14]. This model predicts that control-to-input-current transfer function is ^
i g ( s) ^
d ( s)
V sL
(2)
where V is the output capacitor voltage. The current loop regulator design is based on digital redesign, using the poles-zeroes matched transformation technique [15].
The input current and input voltage are sampled at the switching frequency. To avoid sampling the noise around
L +
750uH
input line voltage Vg(t) 85-260V,rms 50-60Hz
(1)
Current loop regulator design
Selection of sampling instant
vg(t)
0.5 and
C K
Vout(t)
47uF
Load
-
ig(t)
H
KVg(t)
Rsig(t)
DPWM Delay 200KHz
freq. div.
120Hz
HVout(t)
A/D KVg[n]
A/D
d[n]=aid[n-1]+Ki(bie[n]-cie[n-1]) A/D
Rsig[n]
++
Current loop regulator
-
ei[n] Voltage loop regulator
ev[n]
Multiplier
u[n]=avu[n-1]+Kv(bvev[n]-cvev[n-1])
Fig.2. Completely digitally controlled low-harmonic rectifier
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-
HVout[n]
+
+
Vref
It was found that the digital PI regulator can be described with following discrete-time control law:
frequency; the capacitor must be allowed to store and release energy as necessary to interface the pulsating power of the single-phase ac input to the constant power drawn by the dc load. Removal of the second-harmonic voltage through feedback would cause constant distortion of the reference for the input current signal, and would consequently create serious distortion of the ac line current. For the voltage loop digital controller presented in Fig.2, concept described in [9,16] based on sampling at twice the line frequency is used. Sampling at this frequency provides filtering of the second harmonic component. This low sampling frequency also limits the bandwidth of the voltage loop to frequencies lower than the ac line frequency. To design regulator for the voltage loop of the system shown in Fig.2 low frequency model, based on the averaging over a half of the line period [14] was used. As a result, the following control-to-output transfer function was derived.
(3)
d [n] d [n 1] 0.875 ei [n] 0.85ei [n 1]
Magnitude and phase asymptotes of the system with implemented controller are given in Fig.4. 200 150 100
Magnitude [dB]
50 0 -50 -100 -150
Phase [deg]
^
v( s)
-200
^
100
1k
10 k
u c ( s)
100 k (Hz)
Fig.4 Magnitude and phase asymptotes of the loop gain
1 Vout 2 U H 1 sC Rout 2
where U is the steady-state value of the control variable at the output of the voltage regulator. Using the digital redesign method again, we designed a slow PI regulator that provides 20Hz bandwidth.
It can be seen that applied digital regulator provides sufficient phase margin (about 45°) and a crossover frequency of 12KHz. Design of a low-bandwidth voltage loop The current loop regulator forces the input current to follow the input voltage waveshape, and as the result the input port of an ideal rectifier behaves as an emulated resistor Re. The power apparently “consumed” by this emulated resistor is actually transferred to rectifier DC output. Based on this, the equivalent model of the ideal rectifier is derived [14] and illustrated in Fig.5. Ts
Re
C
load
Vg(t)
Fig.5 Equivalent circuit of the ideal low-harmonic rectifier
In this model, the output port is represented with a controllable power source. If the input voltage is sinusoidal, the instantaneous power delivered to the power source pac(t) is pac (t )
2Vg2, rms Re
sin 2
L
t
Vg2, rms Re
1 cos 2
L
t
(4)
As the result, the voltage across the output energy-storage capacitor must have ripple at 2fL, where fL is the line frequency. To regulate the output voltage, additional feedback is needed. This feedback cannot attempt to remove the capacitor voltage ripple at the second harmonic of the line
(5)
Fig.6 Input current waveform (500 mA/div) and its harmonic content. Top: Spectrum 200 mA/div. Bottom: Magnified view of the spectrum, 1 mA/div.
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The discrete control law of this regulator is (6)
u[n] u[n 1] 8 ei [n] 0.275ei [n 1]
In the experimental system based on the diagram in Fig.2: THD of the input current below 3%, and unity power factor over universal input range (85-260Vrms) were measured. The input current waveform and its harmonic content are shown in Fig.6. From the measurements it can be seen that amplitudes of higher harmonics are negligible in comparison with the fundamental. III. DIGITAL CONTROLLER WITH IMPROVED VOLTAGE DYNAMIC RESPONSE Because of the low bandwidth of the output voltage feedback loop, components within the rectifier and downstream converter must be designed to handle substantial transients in the capacitor voltage induced by low current or ac line voltage transients. Voltage dips can cause loss of regulation in downstream converters or reduced hold up time, while over-voltages require increased voltage rating of energy storage capacitor and other elements. These issues require that conventional designs operate over an increased dynamic range leding to increased cost and reduced efficiency. A faster voltage loop would provide smaller variations of the output voltage, and consequently greater optimization of the design of the low–harmonic rectifier and following stages. As shown bellow, these benefits can be realized through use of a digital notch filter.
For the case when the center frequency of the notch filter is equal to the second harmonic of the line frequency, the component at the frequency of 2 L is eliminated and signal e1(t) contains only the difference between the reference voltage and HV1(t) e1 ( t ) Vref
(9)
HV1 ( t )
Equation (9) shows that the emulated resistance Re is not influenced by the second harmonic of the line frequency. Therefore, the bandwidth of the voltage loop can be expanded to frequencies higher than 2fL. It is difficult to implement an ideal notch filter that satisfies characteristics listed above, using an analog structure [9]. Reasons for this include variations of the component values caused by change of temperature, aging, tolerance of component values, and non-ideal characteristics of physical components. The discrete transfer function of a digital notch filter [17] is given by: H ( z ) b0
1 2 cos 1 2r cos
Discrete center frequency 2
0
0
0 0
z
z
1 1
z
2
2
r z
(10)
2
is defined as
f0 f sv
(11)
where f0 is the filter center frequency (2fL), fsv is the sampling frequency of the output voltage and parameter r varies in the range 0 < r < 1.
Digital notch filter The characteristics of the ideal notch filter are:
Magnitude and phase characteristics of the filter for several values of the parameter r are given in Fig.8. It can be seen that for higher values r, the characteristics of the filter approach those of an ideal notch filter.
Infinite attenuation at the center frequency Unity gain at all other frequencies No influence on phase of the signal Insensitive to external influences Fig.7 shows the equivalent circuit of a low-harmonic rectifier that incorporates the notch filter in the voltage loop. The attenuated output voltage is compared with a reference voltage to generate the following error signal:
p( t )
Ts
Vg(t)
+
Io(t)
Re
Vout(t) Load
C
H
_
e( t )
(7)
HVout( t ) Vref
K1/u(t)
The output voltage Vout(t) can be expressed as the sum of voltage ripple at the second harmonic of the line frequency and the remaining component V1(t):
Vout (t ) V1 (t )
Pload sin( 2 2 CVC , rms
L
t
PI u(t) Regulator
e1(t)
Notch filter
e(t)
+
Fig.7. Equivalent circuit of low-harmonic rectifier with notch filter implemented in the voltage loop
) (8)
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Vref
Design of a high-bandwidth voltage loop
100
Magnitude [dB] 0
Using Eq. (4), we can see that is possible to separate the power source into two sources as shown in Fig. 9. The instantaneous powers of both of these sources depend on the time-varying value u(t), which controls the emulated resistance Re.
-100 -200 -300
Io(t)
-400
+
150 P1 ( t )
100 50
Vg 2r ,rms
P2 ( t )
R e ( U ( t ))
Vg 2r ,rms R e ( U ( t ))
cos( 2
L
t)
Phase [deg]
Vo(t)
C
Load
_
0 Fig.10 Equivalent circuit of the output port for high-bandwidth voltage loop
-50 -100 15
150
1.5k (Hz)
Although the component at the second harmonic frequency is eliminated by the filtering of the digital notch filter, we can see that, in a wide-bandwidth voltage loop, components at frequencies higher than 2fL will be created due to fast change of emulated resistance. One consequence of the wide-bandwidth of the control system is that the low frequency models [14], traditionally employed in design of low-frequency voltage loops, cannot be employed here. Moreover, Fig.10 shows that, for the higher bandwidth, this circuit behaves as non-linear, timevarying system and hence the tools of conventional control theory developed for linear time-invariant systems cannot be used. To implement the regulator with minimal hardware structure we decided to use a single non-adjustable structure that provides fast response on load transient. The regulator is designed to provide bandwidth between 120Hz and 240Hz for the worst case in the circuit, where the worst case was considered to be the moment when, the instantaneous input power and output load have maximum values. The resulting regulator is described with following discrete control law:
Fig.8 Magnitude (top) and phase characteristic (bottom) of the digital notch filter
Filter implementation To implement the filter of Eq.(10), the output voltage sampling frequency is selected based on two considerations: The objective to increase the voltage loop bandwidth, Limitation of the achievable values of the filter and controller parameters imposed by the use of the 8-bit fixed-point processing In the prototype system with the notch filter inserted before the voltage loop regulator (Fig.9), the sampling frequency is 4 kHz, the center frequency 120 Hz and r = 0.975. The resulting notch filter transfer function is H ( z)
1 1.96 z 1 z 2 1 1.91z 1 0.9502 z
(12)
2
vg(t)
power stage
switch
Rsig(t)
vou(t)
DPWM
freq. div.
Delay 200KHz
A/D vg[n]
A/D
d[n]=aid[n-1]+Ki(bie[n]-cie[n-1]) A/D
Rsig[n]
Multiplier
++
4kHz
-
Current loop regulator
ei[n]
u[n]=avu[n-1]+Kv(bvk[n]-cvk[n-1])
k[n]
digital notch filter
Voltage loop regulator
ev[n]
vou[n]
-
+ + Vref
Fig.9. Digital controller with a notch filter and wide-bandwidth voltage regulator
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480
u[n] u[n 1] 0.875 ei [n] 0.9685ei [n 1]
(13)
In this example, the bandwidth of the voltage loop was limited to 240Hz, due to constant presence of 4th and higher harmonics in the reference for input current. IV. TEST SYSTEM AND EXPERIMENTAL RESULTS The experimental system was designed around an ADMC401 DSP [8], which offers higher performance than needed for controller implementation described in Sections II and III. In the prototype realization, we purposely limited resolution of A/D, DPWM and performed all processing in fixed-point, 8-bit arithmetic to show it would be possible to realize system using even simpler lower cost hardware. Fig. 11 shows step load (100W to 200W) load transient response measured for two cases: a) with the prototype that has standard, slow voltage loop as described in Section II, and b) with the notch filter and redesigned voltage regulator as described Section III. It can be observed that filter implementation yields significantly improved dynamic response. Fig.12 compares input current harmonic for the widebandwidth voltage loop with and without digital notch filter. Without notch filter wide-bandwidth voltage regulator results in significant input current harmonic distortion (THD of more than 20%), while with the notch filter input current THD is about 4.3%.
Fig.12.Harmonic content (1st-7th harmonics) of the input current with wide-bandwidth voltage regulator: (1) without the notch filter, THD > 20%, and (2) with the notch filter, THD < 5%.
V. CONCLUSIONS This paper describes the practical design of a high-quality low-harmonic rectifier using relatively simple digital control hardware. It is shown how the output voltage dynamic response can be significantly improved by adding a digital notch filter in the feedback loop. Improved voltage loop dynamics potentially enables the use of smaller tank capacitor at the output, operation at a smaller output voltage, and use of smaller, not over-designed components in the following dc/dc converter stage. Low input current harmonics and fast load transient response are experimentally verified on a 200 W boost high power factor rectifier. VI. REFERENCES
Fig.11. Transient response for the change of load from 100W to 200W, with a standard voltage loop with crossover frequency of 20Hz (top) and for the expanded bandwidth loop with the notch filter (bottom). Ch.1 – output voltage, Ch-2 load transient, Ch-4 input current
[1] A.H. Mitwalli, S. B. Leeb, G.C. Verghese, V.J. Thottuvelil, “An Adaptive Digital Controller for a Unity Power Factor Converter,” IEEE Trans. on Power Electronics, Vol. 11, No.2, pp.374-382, March 1996. [2] S. Buso, P. Mattavelli, L. Rossetto, G. Spiazzi, “Simple Digital Control for Improving Dynamic Performance of Power Factor Preregulators,” IEEE Trans. on Power Electronics, Vol.13, pp.814-823, September 1998. [3] J. Zhou, Z. Lu, Z. Lin, Y. Ren, Z.Qian, Y. Wang “A Novel DSP Controlled 2 kW PFC Converter with a Simple Sampling Algorithm,” IEEE Applied Power Electronics Conference 2000, pp. 434-437. [4] M. Fu, Q. Chen, “A DSP Based Controller for Power Factor Correction (PFC) in a Rectifier Circuit,” IEEE Applied Power Electronics Conference 2001, pp. 144149. [5] S. Bibian, H. Jin, “Digital Control With Improved Performance for Boost Power Factor Correction Circuits,” IEEE Applied Power Electronics Conference 2001, pp. 137-143.
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[6] Y. T. Feng, G. L. Tsai and Y.Y. Tzou, “Digital Control of a Single-Stage Single-Switch Flyback PFC AC/DC Converter With Fast Dynamic Response,” IEEE Power Electronics Specialists Conference, 2001, pp. 1251-1255. [7] S. Wall and R. Jackson “Fast Controller Design For Single-Phase Power-Factor Correction System” IEEE Transactions on Industrial Electronics, Vol.44, pp 654-660, October 1997. [8] Analog Devices, Inc., ADMC-401 Single-Chip, DSPBased High Performance Motor Controller, rev B, 2000. [9] Robert Erickson, Michael Madigan, and Sigmund Singer, ”Design of a Simple High Power Factor Rectifier Based on the Flyback Converter,” IEEE Applied Power Electronics Conference 1990, pp. 792801. [10] J.B. Williams, “Design of Feedback Loop in Unity Power Factor AC to DC Converter,” IEEE Power Electronics Specialists Conference 1989, pp. 959-967. [11] S. Wall, R. Jackson, “Fast Controller Design for Practical Power-Factor Correction Systems,” IECON 1993, pp. 1027-1032.
[12] Mohmed O. Elissa, Steven B. Leeb, Georege C. Varghese and Aleksandar M. Stankovic, "Fast Controller for a Unity-Power-Factor PWM Rectifier,” IEEE Transactions on Power Electronics, Vol.11, No.1, January 1996, pp. 1-6. [13] G. Spiazzi, P. Mattavelli, L. Rossetto, "Power Factor Preregulator With Improved Dynamic Response,” IEEE Power Electronics Specialists Conference, 1995 pp. 150-156. [14] Robert W. Erickson and Dragan Maksimovic, Fundamentals of Power Electronics – Second Edition, Kluwer 2000. [15] G. F. Franklin, J. D. Powell and M. L. Workman, Digital Control of Dynamic Systems, III Edition Addison-Wesley 1998, pp. 187-209 [16] G.Spiazzi, P.Mattavelli, L.Rossetto “Methods to Improve Dynamic Response of Power Factor Preregulators: An Overview” European Power Electronics Conf. (EPE), 1995, Vol.3, pp.754-759. [17] John. G. Proakis and Dimitris G. Manolakis, Digital Signal Processing Principles, Algorithms and, Applications, III Edition, Prentice-Hall, Inc. Company: 1996, p. 345 –3 48.
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