Directed Self-Assembly Process Integration Fin Patterning
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Directed Self-Assembly Process Integration Fin Patterning
DIRECTED SELF-ASSEMBLY PROCESS INTEGRATION FIN PATTERNING APPROACHES & CHALLENGES SAFAK SAYAN ROEL GRONHEID, KIM MIN-SOO, BT CHAN, FRIEDA VAN ROEY LANCE WILLIAMSON, PAUL NEALEY
MOTIVATION: Directed Self Assembly (DSA) offer alternative ways to extend optical lithography cost-effectively for sub-10nm nodes.
Pushing the limits of 193 nm immersion lithography
DSA pattern transfer to commonly used device integration materials such as silicon, silicon nitride, and silicon dioxide have been demonstrated
DSA integration to CMOS process flows, including cut/keep structures to form fin arrays, is yet to be demonstrated on relevant film stacks (front-end-of-line device integration).
Demonstration will confirm and reinforce its viability as a candidate for sub-10nm technology nodes.
PITCH DIVISION METHODS FOR FIN PATTERNING PITCH DIVISION has been achieved by; ▸ Double Patterning Pitch Division (DPPD) ▸ Spacer Based Pitch Division (SBPD) - Hard mask image transfer methods (Double, Triple, Quadruple)
FIN PATTERNING VIA LINE FLOW AT IMEC: SI-ETCH TEM RESULTS ▸ TEM analysis on DSA pattern transfer with encapsulation process. ▸ Result: Trenches get deeper with increasing silicon etch time
IMEC N7 ASSUMPTION ▸ Referring to the design rule of (N7) 7nm technology node, the fin patterning has smaller pitch requirement at sub-30nm. ▸ IMEC assumption is 4-FIN, 3-GATE structures ▸ DSA could offer solution with BCP of 28nm (L0) that would fit into the 7nm technology node requirement. GATES
PLACEMENT ERROR STUDY Reticle is designed with programmed overlay errors for cut structures to study process window. Inverter, AND2, AIO structures are included based on N7 assumption
SUMMARY & OUTLOOK We were able to successfully demonstrate: ▸ DSA integration to CMOS process flows, including cut/keep structures to form fin arrays, is demonstrated on relevant film stacks (front-end-of-line device integration). ▸ DSA integration and developed flow for fin patterning consistent with IMEC N7 assumptions
A cut-1st-HM approach, alternative to a conventional cut-last approach, is proposed to address a very probable alignment accuracy issue, and to eliminate the need of a zero mark layer.
Quantify overlay capability and fin profiles for both approaches
