Integration of dry etching steps for Double Patterning and Spacer Patterning processes S. Barnola*, C. Lapeyre, I. Servin, C. Arvet1, P.Maury1, L. Mage CEA-LETI-Minatec, 17, rue des Martyrs, 38054 Grenoble Cedex 9, France. 1 STMicroeletronics assignee ABSTRACT Double patterning (DP) is today the accepted solution to extend immersion lithography to the 32 nm node and beyond. Pitch splitting process and spacer process have been developed at CEA-LETI-Minatec. This paper will focus on the optimization of dry etching process to achieve these two patterning techniques. For each approach, we first discuss the choices of the starting integration flows based on the requirements to etch the final devices. Then, we develop how the etching steps were optimized to get a good step by step CD control for 45nm/45nm features. Keywords: Double patterning, spacer patterning, etching, integration, CD control
1. INTRODUCTION Although only added to the ITRS Roadmap in 2006, Double Patterning (DP) is now considered the key enabling technology for 32nm lithography [1]. Double Patterning differs from Double Exposure (DE) in that with DP the wafer is removed from the lithography scanner’s chuck after the first pattern exposure. It is then developed and undergoes a hard mask etch before returning to the scanner for exposure of the remaining portion of the same layer. While very effective in enhancing imaging capabilities for fine pitch patterns, there are drawbacks associated with DP technology. Increased costs due to the additional process steps required is a significant concern for many; and as two lithography steps are used, tool overlay and image placement will impact the pattern quality and can be translated into critical dimension (CD) errors [2]. Furthermore, multiple lithography and etching steps can induce heightened processing challenges, in particular due to change in the shape of the wafer substrate. Moreover, CD uniformity becomes increasingly critical at 32nm and beyond, with the ITRS Budget requirements being 2.6nm (3σ) for the 32nm node (year 2013). Controlling the final CD of each line produced by patterning steps #1 and #2 independently is one of the main challenges of the Litho-Etch-Litho-Etch process (LELE), making this a vital area of investigation. Double patterning using spacer (also called spacer patterning) is another emergent technique, especially for the memory devices manufacturing. The main interest is the good control of the CD uniformity, as there is no additional overlay error compared to LELE process : the final CD uniformity is mainly driven by the spacer deposition uniformity. For each technique, we will first discuss the integration scheme and materials we used to achieve a realistic strategy. Then, we will describe the optimized etching process utilized to achieve good CD control.
2. ETCH DEVELOPMENT FOR LELE PROCESS 2.1 Discussion on the integration scheme & materials In order to fulfil the requirements of the most advanced FEOL applications, we decided to choose a flexible strategy that was as much independent as possible from the materials where the final dimensions would be transferred to (Poly-Si for gate, nitride on Si for STI). A multi-layer approach (two hard masks over a carbon based mask as described on figure 1) is well adapted to most of the applications; carbon based materials are commonly used for critical levels [3]. In this multi layer approach, the first hard mask (HM1) is patterned by LITHO1 (line/space=1/2.8) and ETCH1, stopping on the second hard mask (HM2). The resist is stripped; then, the second hard mask is patterned by LITHO2 (line/space=1/2.8) and ETCH2. The final pitch (line/space=1/1) is then transferred into the carbon layer that will be used as the final mask
*
[email protected];phone +33-4-3878-2921 Optical Microlithography XXII, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 7274, 72741X · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.814856
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for the devices. The main advantage of this strategy is that the mask budget to etch the final device only relies on the carbon layer thickness, and does not depend on the two hard masks thicknesses. For the DP line approach, we need two hard masks in order to transfer the two lithography features. We had first to select the most adapted materials for both the etching and integration needs. The multi layer stack is based on the use of a carbon layer deposited at relatively low temperature (whatever the process: PECVD or spin coating). To avoid any damage to this carbon layer, the first constraint is to deposit the hard mask materials at relatively low temperature, so amorphous materials are good candidates. The two materials used as hard masks must allow to get a good selectivity towards HM2 when etching HM1, but also a good selectivity towards HM1 when etching HM2. Several candidates were available: Si3N4/SiO2, Si/SiO2 and others. The patterning of the Carbon layer is commonly done with a SiOx on top of it, as it is easy to get a good selectivity towards Carbon by using HBr/O2 chemistry (selectivity~30:1). Thus, we decided to use SiOx as hardmask#2 and SiNx as hardmask#1. 30nm of SiNx (HM1) and 20nm of SiOx (HM2) can be considered as reasonable values, as they minimize the topography and allow robust etching processes. Lithography and etching for Double Patterning were developed on 300mm wafer at CEA-LETI-Minatec using the tools detailed on table. 1.
LITHO1
ETCH 1
LITHO2
ETCH2
Carbon Layer
Carbon Layer
BARC HM2
Carbon Layer Ei-iH
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Fig. 1. Selected integration scheme for DP line
Table. 1. Tools used for DP development Track ArF dry Scanner Plasma Etching Top view CD-SEM X section SEM
SOKUDO RF3 NIKON NSR-S307E (0.85NA) LAM VERSYS Kiyo and Flex Hitachi CG4000 Hitachi 5000
2.2 Lithography conditions
The double patterning lithography technology has been developed using an ArF resist (177nm) on top of 32nm of AR26 BARC (RHEM). All exposures have been performed using phase shift masks 6% att-PSM. We focused the development on 180nm pitch with a CD target in litho1 and litho2 of 65nm using polarized dipolar illumination. Using these conditions, the litho performances are pretty good. Comfortable PW have been obtained with DOF of 430 nm at 5% exposure latitude (EL) at litho1 and DOF of 350 nm at 5%EL at litho2. The intra-field CD uniformity is around 2.6nm at litho1 and 3.3nm at litho2 , thus well below ITRS requirements. PW reduction and CDU increase at litho2 are due to topography effects as discussed in another paper, where more details about litho performances are given [4]. The final CD target of 45nm is achieved thanks to a resist trimming step included in the etching sequence. 2.3 Etch process optimization ETCH1 optimization to increase the resist budget Both ETCH1 and ETCH2 process steps are a combination of many steps that include BARC opening and hard mask etching steps. One of the critical point is the profile control to target the final dimensions in the hard mask features. Getting enough remaining resist after opening the hard mask is a good guaranty of the features’ integrity (no faceting).
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As BARC and resist are both organic based materials, the BARC opening step is the one that consumes the biggest amount of photo resist. Thus, one way to reduce the resist consumption is to decrease, the thickness of the BARC layer; another way is to use carbon based plasma chemistry. Fig 2 is comparing the resist profiles of different chemistries used to open 82nm of AR19 (on Si), which was the BARC material/thickness selected initially for the DP process. The CF4 chemistry gives the best results in terms of resist profile and line width roughness (LWR).
CF4
ThlOOnm Fig. 2. Top view SEM and cross-section SEM images : remaining resist thickness after BARC etch with several chemistries used to open 82nm AR19
In order to keep on increasing the resist budget margin, we decided: to reduce the thickness of the BARC layer (32nm AR26 instead of 82nm AR19) and to add a Plasma cure step (HBr chemistry), well known to harden the ArF photo resist [5]. These two changes enhanced the amount of remaining resist at the end of the HM1 etching, avoiding any faceting of the SiNx features. The CD drop between lithography (target=65nm) and post etch (final target=45nm) is controlled by adding a plasma trimming step in the etching sequence. This extra step is mostly isotropic (no ion bombardment) to consume the resist features laterally. By using HBr/O2/CHF3 chemistry, it is possible to get trim rate of about 2nm/sec, which is sufficient to smoothly achieve about -20nm CD bias between lithography and etching. The last key point to minimize the resist consumption is the SiNx hard mask etching step. This sequence controls the HM1 profile while getting enough selectivity to oxide. One step or two steps can be used to achieve these goals. With a two steps strategy, the first step ensure a straight profile while the second one has the highest selectivity towards oxide (SiNx/SiOx>5:1). This last one is generally based on CHxFy/O2 chemistries [6], which consume quite a lot of resist. We finally performed a single step to both control the SiNx HM1 profile and selectively stop on oxide (SiNx/SiOx~2:1). A summary of the ETCH1 sequence with the achievement is presented on Fig 3. Fig 4 shows the straight profiles of the patterned SiNx HM1 after ETCH1.
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Fig. 3. Summary & achievements of the ETCH1 sequence
Ii I Fig. 4. X section SEM pictures after ETCH1 without faceting
ETCH2 optimization to minimize the HM1 consumption The specificity of the ETCH2 sequence is that it requires to transfer two kinds of features in the HM2 (Fig. 5): the features printed in the resist during the LITHO2 step and the features printed in the HM1 during the ETCH1. Controlling the final CDs in the HM2 is real challenge, especially the CD of the features transferred from LITHO1 to HM1 and then to HM2.
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Fig. 5. Summary of the ETCH2 sequence
The key challenge is to minimize the impact of the ETCH2 sequence on the CD defined after ETCH1, in order to get a final CD1 that is, as much as possible, independent from ETCH2. This is possible if each step of the ETCH2 sequence
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(BARC, trim & HM2 etch) has a minimum impact on the SiNx feature defined after ETCH1. For the BARC etching step, Cl2/O2 chemistries give the highest selectivity towards SiNx (Table. 2), thus the SiNx feature will be preserved during the AR26 opening. Concerning the trimming step, used to decrease the CD of the resist feature from 65nm to 45nm, an isotropic plasma etching (HBr/O2/CHF3 chemistry) was optimized. This step is selective to SiNx, when using a low CHF3 ratio. Last but not least, the SiOx etching should be selective to the SiNx feature as well. Two chemistries have been tried: CF4/CH2F2/He and C4F8/O2/Ar. As shown on figure 6, the SiNx HM1 is completely consumed when using the CF4 based chemistry (SiOx start to be consumed as well), whereas the HM1 is much less consumed when etching the SiOx in C4F8 based plasma.Theses results are in agreement with the SiOx/SiNx selectivity that is proven to be much higher with CxFy chemistries [6]. Table. 2. BARC/SiNx selectivity vs BARC chemistry BARC chemistry Selectivity BARC/SiNx
CF4 1.3:1
XtOeK
Cl2/O2 55:1
HBr/O2/CHF3 6:1
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Oxide
CF4/O2/Ar 0.1:1
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me
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Fig. 6. X section SEM after ETCH2 in CF4/CH2F2/He (top) and C4F8/O2/Ar (Bottom)
Final CD results We compared the impact of two etching processes on the average CD values after each step (Fig. 7). The non-optimized process refers to a process where the ETCH2 step is not optimized in terms of SiNx HM1 consumption (SiOx etching in CF4 based plasma). The optimized process refers to a process where the SiOx etching is done in C4F8 based plasma. In the non-optimized case, the impact of the HM1 consumption is pretty clear on the CD values: the average CD after ETCH1 is further decreased by 12nm after ETCH2. Therefore to compensate for such a CD loss during the ETCH2 and to reach the final 45nm value, we need to target a wider CD after ETCH1. In the optimized case, the average CD after ETCH1 is only decreased by 3nm during ETCH2, which is consistent with the cross-section SEM pictures presented above (Fig. 6) Concerning the CD uniformity across the wafer, the etching steps do not induce additional non uniformity during the DP line sequence [4]. The final achieved values fits with the 45nm & 32nm ITRS requirements
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Non-optimized U Optimized
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Fig. 7. Average CD values of line 1 and line 2 after each step for optimized & non-optimized DP line process
2.4 Conclusion By carefully choosing the integration scheme and the materials, we succeeded to develop a 45nm/45nm double patterning sequence at CEA-LETI-Minatec. Top view pictures of the features after each step are presented on Fig. 8. By optimizing the etching steps, we achieved a independent control of the CDs: a first feature is defined by LITHO1+ETCH1, a second feature is defined by LITHO2+ETCH2 and the first feature is almost not impacted by the ETCH2 (-3nm). Moreover the final CD uniformities are within the 32nm node ITRS requirement, which make this DP line process extendable to this technology node [4].
Litho1
200K
Etch1
200K
Litho2
200K
Etch2
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Fig. 8. Top view CD-SEM pictures after each process step
3. ETCH DEVELOPMENT FOR SPACER PATTERNING 3.1 Spacer patterning process integration Fig. 9 describes the process flow used to develop the spacer patterning strategy. This integration flow is composed of several steps: • Carbon layer and SiOx deposition • Lithography with a CD target of 65nm (pitch 180nm) • Resist trimming, SiOx etching and Carbon layer opening to achieve 45 nm post etch CD • SiOx removal by wet etching • 45nm thick Nitride Spacer deposition • SiNx Spacer etching • Carbon layer stripping
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The remaining SiNx spacers (CD~45nm, pitch 90nm) can be used as hard masks to etch the final devices (Active, Gate…). Such integration enables to reduce the pitch by a factor 2.
UI ,I.I uU
B
SiOx SINX spacer Uthography Transf& In & Carbon mask deoosition
SINX spacer each
removal
Fig. 9. Spacer patterning process integration flow
The main points of optimization in etching were: • The SiOx & Carbon layer patterning using resist trimming to achieve CD of 45nm with vertical profiles • The SiNx spacer etching with minimum impact on the spacers’ width Resist trimming and Carbon layer open As the lithography target was set to 65nm and as the final dimensions should be 45nm, the CD was reduced during the etch step. The etch sequence includes: • HBr resist curing step to harden the photoresist • Resist trimming step to reduce the CD to 45nm • DARC opening step selective to the carbon layer in CF4/CH2F2/He • Carbon layer etching step in HBr/O2 The resulting carbon lines are showed in Fig. 10. Cross section CD-SEM picture is showing very straight profiles at this stage.
Fig. 10. Top view & Cross section SEM after trimming and APF open
Spacer Etching The remaining DARC layer is removed right after the carbon layer etching in order to make the carbon stripping easier after the spacer etching. The DARC layer is removed in a wet clean tool. Another option would have been to remove this layer after spacer etching. In this last case, it is more complicated as oxide removal need to be done selectively to nitride. The spacer deposition is a key step of the integration as it partially drives the final CD of the lines. The requirements of the deposition process were the followings: •
Deposition process compatible with the carbon
•
Acceptable conformity to reach 45nm deposition on the sidewall
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•
Acceptable uniformity (3sigma
