IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
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A 43-Gb/s Full-Rate-Clock 4 : 1 Multiplexer in InP-Based HEMT Technology Yasuhiro Nakasha, Toshihide Suzuki, Hideki Kano, Kouji Tsukashima, Akio Ohya, Ken Sawada, Kozo Makiyama, Tsuyoshi Takahashi, Masahiro Nishi, Tatsuya Hirose, Member, IEEE, Masahiko Takikawa, and Yuu Watanabe, Member, IEEE
Abstract—This paper describes a full-rate-clock 4 : 1 multiplexer (MUX) in a 0.13- m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of 5.2 V. Index Terms—Clock distributor, fiber optical communication, full-rate architecture, HEMT, InP, muliplexer, phase adjuster, retimer.
I. INTRODUCTION
T
HE DEMAND for increased transmission capacity is accelerating the development of next-generation time-division-multiplexing (TDM) systems, for instance, synchronous optical fiber network (SONET) and synchronous digital hierarchy (SDH). In such systems, data signals with a bit rate of more than 40 Gb/s propagate through optical fibers. Several digital [1]–[6] and analog [7], [8] components have been demonstrated for these systems. One possible configuration of a transmitter for the systems is illustrated in Fig. 1. The multiplexer (MUX) converts N-channel low-bit-rate parallel data streams into a one-channel high-bit-rate serial data stream and sends it on to an optical modulator driver (MOD DRV) and an optical modulator (MOD). The MUX is thus one of the key components. There are several requirements for the MUX. First, it must operate at 43 Gb/s or higher in systems with forward error correction (FEC). Second, the jitter of its output signals has to be suppressed enough to meet the strict SONET specification. Third, it should be low in cost, considering its use in wavelength-division-multiplexing (WDM) systems, which use as many MUXs as multiplexed wavelengths. A multichip architecture, shown in
Fig. 1. Possible configuration of transmitter in 40-Gb/s optic-fiber system with FEC.
Fig. 1, is a promising way to meet these requirements. Highspeed InP-based technologies can be used for the 4 : 1 MUX, which has a highest operating speed, while low-cost and highdensity Si-based technologies can be used for the slower N : 4 MUX. Silicon MOS technologies can now be used to produce commercial digital components for 10-Gb/s systems [9], [10]. A full-rate clock and a retimer are needed to suppress the jitter. Since the retimer aligns all data transitions to either the rising or falling edge of the full-rate clock, it eliminates deterministic jitter due to the duty-cycle distortion of the clock. The quality of the clock provided to the retimer is the dominant factor in determining the output jitter from the MUX. The most difficult problem in achieving a MUX with a fullrate-clock architecture is precise alignment of the clock edge with the center of the time slot for incoming data at the retimer. This is because the phase margin of the retimer is small [155 (10 ps) at 43 Gb/s] and because the alignment must be robust to variations in the supply voltage, temperature, and fabrication process. Little has been reported on how to deal with clock-and-data alignment at the retimer in 40-Gb/s or faster MUXs. Moreover, all monolithic over-40-Gb/s 4 : 1 MUXs reported so far use heterojunction bipolar transistor (HBT) technologies [1]–[4], whereas, to the best of our knowledge, 4 : 1 MUXs using FETs have not yet been reported. In this paper, a full-rate-clock 4 : 1 MUX in a 0.13- m InP-based HEMT technology is described. The 4 : 1 MUX contains a building block to adjust the timing of the data and clock in the retimer. II. CIRCUIT DESIGN A. Circuit Architecture
Manuscript received April 29, 2002; revised July 9, 2002. Y. Nakasha, T. Suzuki, H. Kano, K. Sawada, K. Makiyama, T. Takahashi, T. Hirose, M. Takikawa, and Y. Watanabe are with Fujitsu Laboratories, Ltd., Atsugi 243-0197, Japan (e-mail:
[email protected]). K. Tsukashima, A. Ohya, and M. Nishi are with Fujitsu Quantum Devices, Ltd., Nakakoma-gun 409-3883, Japan. Digital Object Identifier 10.1109/JSSC.2002.804357
A block diagram of the 4 : 1 MUX is shown in Fig. 2. The main circuit components are three 2 : 1 MUX blocks connected in a tree structure, a retimer in the final stage, a phase adjuster, a clock distributor, two frequency dividers (T-FF , T-FF ), four data input circuits, and a data output circuit. The circuit
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Fig. 2.
Fig. 3.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002
Block diagram of full-rate-clock 4 : 1 MUX.
Schematic diagram of SCFL-based D-FF used as retimer in 4 : 1 MUX.
also has two auxiliary output ports (M and M ) to monitor the internal waveforms. Each of the 2 : 1 MUX blocks consists of a master–slave flip-flop (M–S FF), a master–slave–slave FF (M–S–S FF), and a selector (SEL). This circuitry provides the maximum timing margin between the data and clock at the selector. T-FF supplies the half-rate clock for the 2 : 1 MUX block in the second stage, and T-FF supplies the quarter-rate clock for the 2 : 1 MUX blocks in the first stage. The data input circuits and the clock distributor each contain a single-ended to differential converter (S-D Conv.) because the input data and clock are single-ended for packaging simplicity. The output data are differential. On-chip 50- terminations are provided for input and output ports. Three building blocks, the retimer, the phase adjuster, and the clock distributor, are the keys to achieving over 43-Gb/s multiplexing. They will be described in more detail in the following subsections. B. Retimer A schematic diagram of the D-type FF based on source-coupled FET logic (SCFL) that is used as the retimer is shown in Fig. 3. It is composed of a master latch and a slave one, each of which forms a Gilbert cell. Two devices are introduced to improve the operating speed: a speed-up capacitor and a peaking inductor. The speed-up capacitor compensates for the loss of the level-shift diodes in the source follower. The inductor in the load produces peaking in the gain at more than 40 GHz, producing steeper rise and fall transitions.
Fig. 4. Symmetric layout and schematic diagram of SCFL buffer. Only half of the layout is shown. The symmetric layout reduces differential coupling. Significant ground couplings and spacing are denoted as C (n: 1–4) and s, respectively.
Since parasitic coupling capacitors significantly degrade the performance of the retimer, a physical layout that eliminates them is essential. Both differential coupling and ground coupling are dominant. Differential coupling occurs where the differential pairs are close together, while ground coupling occurs where the circuit elements are close to the ground. To reduce the differential coupling, a symmetric layout, where all differential elements are placed completely symmetrical with respect to the ground, is used. Fig. 4 shows an example for an SCFL buffer. The ground couplings on the critical path, which are denoted ( : integer) in Fig. 4, were estimated using a multiconas ductor transmission lines simulator (LINPAR). The circuit elements couple more strongly to the neighboring ones and to the ground layer than to the backside of the substrate because the spacing ( 10 m) is much smaller than the substrate thickness (600 m). Therefore, optimization of the spacing is important. The simulated spacing dependencies of the coupling capacand the frequency bandwidth of the SCFL buffer are itance shown in Fig. 5. The schematic cross section used in the simulation is shown in the inset. Since the effect of the lowest order surface-wave spurious mode starts to appear, the maximum operating frequency of a microstrip line with a substrate thickness of 600 m is limited to about 50 GHz, which is given by
where is in gigahertz, is a substrate thickness and is in millimeters, and is a relative permittivity constant of the substrate (12.5 for InP) [11]. The thickness can be thus treated as a microstrip mode at up to 50 Gb/s. The situation discussed here, however, should be dealt with as a micro-coplanar strip mode rather than a microstrip mode because the coupling between the circuit element and the neighboring ground layer is much stronger. Since the neighboring ground layer was treated not as real ground but as a conductor in the simulation, the coupling capacitance estimated was larger than the real value. It is, however, preferable in terms of circuit design with a larger margin. Al) was though each of the coupling capacitances ( only a few femtofarads, the sum of them degrades the circuit performance. When the spacing was larger than about 10 m, the coupling capacitance increased only slightly as the spacing
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Fig. 7. Block diagram of the phase adjuster.
Fig. 5. Simulated spacing dependencies of coupling capacitance, C , and frequency bandwidth of SCFL buffer. Schematic cross section considered in multiconductor transmission lines simulation is shown in the inset. C is a summation of the two coupling capacitances.
Fig. 8.
(a)
Functionality of the phase adjuster.
dividers and clock input circuits in the MUX. The phase margins of the re-timer test chip were measured using the sampling oscilloscope. They were 155 (10 ps) at 43 Gb/s, 100 (6 ps) at 48 Gb/s, and 70 (4 ps) at 50 Gb/s. C. Phase Adjuster
(b) Fig. 6. (a) Block diagram of retimer test circuit. (b) Input and output eye diagrams measured at 50 Gb/s.
decreased. The bandwidth did not degrade significantly. Therefore, the minimum spacing was set at 10 m. Based on the concepts described above, the retimer was designed and fabricated as an element of a test group. A schematic diagram of the retimer test circuit is shown in Fig. 6(a). The input and output eye diagrams of the test chip at a bit rate of 50 Gb/s are shown in Fig. 6(b). A commercial multiplexer unit (SHF 4005A) and a pulse pattern generator (Anritsu MP1748A) were used for the input signal source. A sampling oscilloscope (Agilent 86 100A) was used for the waveform monitor. The performance demonstrates that the design concepts are valid for constructing digital circuits that operate at more than 43 Gb/s. The design concepts were thus also used to design the frequency
The phase alignment of the incoming data and clock at the retimer is essential for reliable operation. A delay created by a string of clock buffers gives the correct timing for the clock to drive the retimer. However, it increases power consumption because the fastest clock buffer must be in the clock path to the retimer and because the number of clock buffers needed is large (typically 4–6). Phase alignment at a narrow range of bit rates can be made by adding a couple of buffers and/or adjusting the length of the interconnects. Although this method reduces power consumption, it is unsuitable for multibit-rate operation because the phase margin of the retimer is small and because the timing deviates from the optimum at any other clock rate. To give a correct timing with the simplest architecture and to facilitate multiclock-rate operation, a phase adjuster is implemented in the 4 : 1 MUX. The phase adjuster, as shown in Fig. 7, is composed of an exclusive OR and a delay switch. The exclusive OR functions as a buffer or an inverter according to an external signal, PC1. The exclusive OR effectively doubles the phase margin of the retimer. The delay switch selects one of two delays according to PC2. The delay difference is . Both PC1 and PC2 are a binary signal and set to open (1) or ground level (0) externally and manually. Fig. 8 shows the functionality of the phase adjuster. In the eye diagrams shown in the figure, the phase margin, or operating area of the retimer, and the time slot of the nonreturn-to-zero
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Fig. 9. condition under which the phase adjuster covers the entire time slot and gives correct timing to clock and data.
(a)
(b) Fig. 10.
Full-rate clock distributors. (a) Conventional. (b) New.
(NRZ) data are denoted as and , respectively. If the down edge of the input clock is in the time region of C, both PC1 and PC2 are set to 0. The data and clock pass through the phase adjuster because the correct timing is already given. If the clock edge is in A or E, PC1 is set to 1, and the clock is inverted at the exclusive OR. If the clock edge is in B, PC2 is set to 1, and the data are led by . If the clock edge is in D, both PC1 and PC2 are set to 1, and the clock is inverted, and the data are led by . under which the phase adjuster covers The condition on the entire time slot is illustrated in Fig. 9. It can be formulated as
The lower limit is given when the down edge of the input clock is at the boundary between A and B. In contrast, the upper limit is given when the clock edge is at the boundary between B and C. at 43 Gb/s are 23.3 and 10 ps, respectively, Since and can be set between 1.6 and 10 ps. Here, it was set to 5.6 ps, which 5.6 ps, the corresponds to the delay time of a buffer. When condition on expressed above is kept, even if both and vary by up to 28% due to variations in the supply voltage, temperature, and fabrication process. Therefore, the phase adjuster gives a robust and reliable timing alignment with a simple architecture. D. Clock Distributor The clock distributor provides a clock for both the phase adjuster and frequency divider. It therefore needs a splitter. Conventional circuits using an active splitter, like that shown in
Fig. 11. Simulated voltage gain versus frequency characteristics of new and conventional clock distributors.
Fig. 10(a), are not suitable for splitting an over-40-GHz clock into two clocks with high gain because it is difficult to keep the layout symmetrical and to minimize the couplings. Moreover, an active splitter consumes much power. A simple wired splitter was thus used in the clock distributor as shown in Fig. 10(b). It divides the clock equally and consumes no power. A peaking inductor was also introduced in the front of the single-ended to differential converter. It resonates with the input capacitance of the single-ended to differential converter, which increases the gain. The simulated voltage gains of the new and a conventional clock distributor are shown in Fig. 11. The new circuit produced a gain of 17 dB at 43 GHz, while the conventional one produced a gain of 12 dB. The dissipated current was 85 mA for the new circuit and 100 mA for the conventional one. The new clock distributor with a wired splitter thus has a higher gain and consumes less power. III. FABRICATION The 4 : 1 MUX was fabricated using 0.13- m InAlAs–InGaAs–InP HEMTs [12]. Both the gate and recess structure of the HEMTs were formed by using electron beam lithography. The maximum transconductance and current cutoff frequency were 920 mS/mm and 175 GHz, respectively. The threshold was 0.63 V with a standard deviation of 13 mV. voltage The InP etching-stop layer used to precisely control the recess depth at the gate of the HEMTs produced this level of uniformity, which is sufficient for the integration level of the 4 : 1 MUX. Two levels of Au layers and low-permittivity benzocy2.8) were used for the highclobutene interlayer films ( propagation-speed microstrip lines. Metal–insulator–metal capacitors made from SiN and NiCr resistors with a sheet resistance of 50 were formed on the InP substrate. A chip micrograph is shown in Fig. 12. The chip measures 4 mm 4.5 mm and integrates 1355 transistors, 790 resistors, and 190 capacitors. The transistor count is, to the best of our knowledge, the highest yet reported for ICs fabricated in InPbased HEMT technologies. IV. EXPERIMENTAL RESULTS AND DISCUSSION Measurements were first made on a wafer using four-channel 1 pseudorandom bit stream (PRBS) data generated by the 2 pulse pattern generator (Anritsu MP1748A) and an ac-coupled
NAKASHA et al.: 3-Gb/s FULL-RATE-CLOCK 4 : 1 MULTIPLEXER IN InP-BASED HEMT TECHNOLOGY
Fig. 12.
Chip micrograph; the die size is 4 mm
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2 4.5 mm. Fig. 14. Functionality of the phase adjuster at 43 Gb/s. Waveforms and phase relations between clock and data are shown. Horizontal: 10 ps/div; vertical: 150 mV/div.
(a)
Fig. 13. Input and output eye diagrams measured at 43 Gb/s. Waveform for input clock at 43 GHz is also shown. Jitters observed for output data and the input clock were 1.40 and 1.04 ps rms, respectively.
clock generated by the Anritsu 69 097A synthesizer. The amplitude of both the input data and clock was 0.6 V. Fig. 13 shows the waveforms of the input and output data at 43 Gb/s and the waveform of the input clock at 43 GHz. They were observed by using the sampling oscilloscope (Agilent 86 100A). The accumulation time was about 3 min. The output data have an amplitude of 0.75 V, which is large enough to drive an optical modulator driver. The functionality of the chip was confirmed by using known data patterns instead of the PRBS data. The peak-to-peak jitter of the output signal observed at 43 Gb/s was 8.9 ps with an rms of 1.40 ps, while the rms jitter of the clock was 1.04 ps. Therefore, the jitter generated in the MUX is esti0.94 ps. Since the phase noise mated to be of the clock measured was low and less than 100 dBc/Hz at an offset frequency of 100 kHz, the large jitter of the clock was due to the sampling oscilloscope, which has a time-base jitter of about 1 ps rms. The total power consumption of the chip was 7.9 W for a single supply of 5.2 V. Circuit simulation demonstrated that the output buffer for 43-Gb/s data and the auxiliary output buffers for the monitor dissipated 1.4 W, about 18% of the total power. Fig. 14 shows the test results for the functionality of the phase adjuster. The timing was matched in three of the four combinations of PC1 and PC2 at 43 Gb/s. The lowest jitter was obtained when PC1 and PC2 were both set to 0. Each of the phase relations between the data and clock at the retimer as derived from the test results is also shown in Fig. 14. These results demonstrate that the phase adjuster operated correctly at 43 Gb/s.
(b) Fig. 15. (a) Photograph of test module. (b) Output eye diagrams of a 4 : 1 MUX mounted in a test module and operating at 47 Gb/s.
TABLE I FEAUTRES OF THE FULL-RATE-CLOCK 4 : 1 MUX
The MUX chip was next mounted in a test module using standard wire bonding. Fig. 15(a) shows a photograph of the module. The size of the module, excluding connectors, is 30 mm 43 mm 9 mm. The four parallel channels of data entered via K-connectors, while the clock entered and the serialized data exited via a V-connector. The mounted chip operated at up to 47 Gb/s. The output eye diagrams are shown in Fig. 15(b). Table I summarizes the chip’s features.
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V. CONCLUSION A full-rate-clock 4 : 1 MUX in a 0.13- m InP-based HEMT technology has been demonstrated. Three building blocks, the retimer, the phase adjuster, and the clock distributor, are the keys to achieving a high-performance circuit. Introducing a fully symmetric layout with optimized spacing to the ground minimizes the differential and ground couplings. A retimer test chip designed using this layout operated at 50 Gb/s. A simple phase adjuster using external control signals aligned the clock and data in the retimer at 43 Gb/s. The clock distributor with a wired splitter provided a clock with a high gain of 12 dB, while consuming only 85 mA. The chip mounted in a test module operated at up to 47 Gb/s. The jitter generated in the MUX, determined by subtracting the clock jitter of 1.04 ps rms from the overall one of 1.40 ps rms, was 0.94 ps rms at 43 Gb/s. The experimental results clearly show the feasibility of using InP-based HEMT technology for extremely high-speed digital applications. ACKNOWLEDGMENT The authors wish to thank M. Sato and N. Yoshida for their help in verifying the design and S. Yamaura for his useful discussion on the circuit design. They are grateful to H. Imai, M. Ono, H. Ohnishi, and S. Kuroda for their encouragement. REFERENCES [1] T. Masuda, K. Ohhara, N. Shiramizu, E. Ohue, K. Oda, R. Hayami, H. Shimamoto, M. Kondo, T. Harada, and K. Washio, “40 Gb/s 4 : 1 multiplexer and 1 : 4 demultiplexer IC module using SiGe HBTs,” in IEEE MTT-S Dig., 2001, pp. 1697–1700. [2] M. Meghelli, A. Rylyakov, and L. Shan, “50Gb/s SiGe BiCMOS 4 : 1 multiplexer and 1 : 4 demultiplexer for serial-communication systems,” in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 260–261. [3] J. P. Mattia, R. Pullela, G. Georgieu, Y. Baeyens, H. S. Tsai, Y. K. Chen, C. Dorschky, T. Winkler Von Mohrenfels, M. Reinhold, C. Groepper, M. Sokolich, L. Nguyen, and W. Stanchina, “High-speed multiplexers: A 50Gb/s 4 : 1 MUX in InP HBT technology,” in IEEE GaAs IC Symp. Tech. Dig., 1999, pp. 189–192. [4] K. Runge, R. L. Pierson, P. J. Zampardi, P. B. Thomas, J. Yu, and K. C. Wang, “40 Gbit/s AlGaAs/GaAs HBT 4 : 1 multiplexer IC,” Electron. Lett., vol. 31, pp. 876–877, 1995. [5] T. Suzuki, H. Kano, Y. Nakasha, T. Takahashi, K. Imanishi, H. Ohnishi, and Y. Watanabe, “40-Gbit/s D-type flip-flop and multiplexer circuits using InP HEMT,” in IEEE MTT-S Dig., 2001, pp. 595–598. [6] H. Kano, T. Suzuki, S. Yamaura, Y. Nakasha, K. Sawada, T. Takahashi, K. Makiyama, T. Hirose, and Y. Watanabe, “A 50-Gbit/s 1 : 4 demultiplexer IC in InP-based HEMT technology,” in IEEE MTT-S. Dig., 2002, pp. 75–78. [7] H. Shigematsu, M. Sato, T. Suzuki, T. Takahashi, K. Imanishi, N. Hara, H. Ohnishi, and Y. Watanabe, “49-GHz preamplifier with a transimpedance gain of 52 dB using InP HEMTs,” IEEE J. Solid-State Circuits, vol. 36, pp. 1309–1313, Sept. 2001. [8] H. Shigematsu, N. Yoshida, M. Sato, N. Hara, T. Hirose, and Y. Watanabe, “45-GHz distributed amplifier with a linear 6-Vp-p output for a 40-Gb/s LiNbO modulator driver circuit,” in IEEE GaAs IC Symp. Tech. Dig., 2001, pp. 137–140. [9] M. Green, A. Momtaz, K. Vakilian, X. Wang, K. Jen, D. Chung, J. Cao, M. Caresosa, A. Hairapetian, I. Fujimori, and Y. Cai, “OC-192 transmitter in standard 0.18m CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 248–249. [10] J. Cao, A. Momtaz, K. Vakilian, M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, and A. Hairapetian, “SONET OC-192 receiver in standard 0.18m CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 250–251. [11] I. J. Bahl and D. K. Trivedi, “A designer’s guide to microstrip line,” Microwaves, vol. 16, pp. 174–182, May 1977.
[12] T. Takahashi, M. Nihei, K. Makiyama, M. Nishi, T. Suzuki, and N. Hara, “Stable and uniform InAlAs/InGaAs HEMT IC’s for 40-Gbit/s optical communication systems,” in Proc. 2001 IPRM, pp. 614–617.
Yasuhiro Nakasha was born in Aichi, Japan, in 1964. He received the B.E. and M.E. degrees in electrical engineering from Nagoya University, Nagoya, Japan, in 1987 and 1989, respectively. In 1989, he joined Fujitsu Laboratories Ltd., Kanagawa, Japan, where he is engaged in research and development on high-speed ICs using compound semiconductor heterostructure devices for communication systems. Mr. Nakasha is a member of the Institute of Electronics, Information and Communication Engineers of Japan.
Toshihide Suzuki was born in Okayama, Japan, in 1969. He received the B.S. and M.S. degrees in electronic engineering from Osaka University, Osaka, Japan, in 1991 and 1993, respectively. In 1993, he joined Fujitsu Laboratories, Ltd., Kanagawa, Japan. There he has been engaged in research and design of high-speed digital ICs using GaAs-HBTs and InP-based HEMTs. Mr. Suzuki is a member of the Institute of Electronics, Information and Communication Engineers of Japan.
Hideki Kano was born in Aichi, Japan, in 1969. He received the B.S. and M.S. degrees in physics from Tohoku University, Sendai, Japan, in 1993 and 1995, respectively. In 1995, he joined Fujitsu Ltd., Kanagawa, Japan, where he worked on the design of high-speed and high density DRAMs. In 2000, he was transferred to Fujitsu Laboratories, Ltd., Kawasaki, Japan, where he has been engaged in research and design of high-speed digital ICs for fiber-optic communications.
Kouji Tsukashima received the B.S. degree in electronic engineering from Osaka Institute of Technology, Osaka, Japan, in 1992. In 1992, he joined Fujitsu Quantum Devices Ltd., Yamanashi, Japan. Since then, he has been engaged in design and development of compound semiconductor ICs for communication systems.
Akio Ohya received the B.S. and M.S. degrees in electronic engineering from Osaka Institute of Technology, Osaka, Japan, in 1998 and 2000, respectively. In 2000, he joined Fujitsu Quantum Devices Ltd., Yamanashi, Japan. Since then, he has been engaged in development of compound semiconductor MMICs for communication systems.
Ken Sawada was born in Osaka, Japan, in 1973. He received the B.S. and M.S. degrees in electronic science and engineering from Kyoto University, Kyoto, Japan, in 1996 and 1998, respectively. In 1998, he joined Fujitsu Laboratories Ltd., Kanagawa, Japan. Since then, he has been studied and developed InP-based HEMT devices and their fabrication techniques. Mr. Sawada is a member of the Japan Society of Applied Physics.
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Kozo Makiyama received the B.S. and M.S. degrees in electrical engineering from Osaka Institute of Technology, Osaka, Japan, in 1986 and 1988, respectively. In 1988, he joined Compound Semiconductor Laboratory in Fujitsu Laboratories, Ltd., Atsugi, Japan, where he has been engaged in research and development of HEMT technologies. Mr. Makiyama is a member of the Japan Society of Applied Physics.
Tsuyoshi Takahashi was born in Tochigi, Japan, in 1963. He received the B.E. and M.E. degrees from the University of Tsukuba, Ibaraki, Japan in 1985 and 1987, respectively. In 1987, he joined the Fujitsu Laboratories Ltd., Kanagawa, Japan. There he has been engaged in research on fabrication technology for InP-based HEMTs and InGaP-emitter HBTs. Mr. Takahashi is a member of the Japan Society of Applied Physics and the Institute of Electronics, Information and Communication Engineers of Japan.
Masahiro Nishi was born in Kanagawa, Japan, in 1966. In 1985, he joined Fujitsu Laboratories Ltd., Kanagawa, Japan. In 1999, he was transferred to Fujitsu Quantum Devices, Ltd., Yamanashi, Japan. Since then, he has been engaged in the development of process technologies for compound semiconductor ICs.
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Tatsuya Hirose (M’01) received the B.E. degree from Tokyo Denki University, Tokyo, in 1987 and the M.E. degree from Hokkaido University, Sapporo, Japan, in 1989. In 1989, he joined Fujitsu Laboratories, Ltd., Kanagawa, Japan, where he has been engaged in research on design and modeling of HEMTs and the development of MMICs based on their technologies. His current research interest includes high-speed and high-frequency integrated circuits for optical and wireless communication systems.
Masahiko Takikawa was born in Osaka, Japan, in 1952. He received the B.E., M.E., and Ph.D. degrees from the University of Tokyo, Tokyo, Japan, in 1975, 1977, and 1981, respectively. In 1981, he joined Fujitsu Laboratories Ltd., Kanagawa, Japan, where he has been engaged in high-speed device development. Dr. Takikawa is a member of the Japan Society of Applied Physics.
Yuu Watanabe (M’87) received the B.S. and M.E. degrees from Kyoto University, Kyoto, Japan, in 1980 and 1982, respectively, and the Ph.D. degree from Osaka University, Osaka, Japan in 1997. In 1982, he joined Fujitsu Laboratories Ltd., Atsugi, Japan, where he has been engaged in the research and development of heterostructure devices and their circuit applications. His current research interests covers high-speed and high-frequency devices and circuits. Dr. Watanabe has served on the committees for the International Electron Devices Meeting, the Symposium on VLSI circuits, and IEEE Electron Devices Society Japan Chapter. He is a member of Institute of Electronics, information and Communication Engineers, Japan.
