1985 Abstracts - CiteSeerX - Penn State

ICCAD85 – 1A.1, Pages 2-4

A Parallel Implementation of MOS Digital Circuit Simulation Hiroshi Uno, Hisao Kinoshita, Sadatoshi Kumagai, Isao Shirakawa, Shinzo Kodama Department of Electronic Engineering, Osaka University, 2-1 Yamada-Oka, Suita, Osaka, 565 Japan

ABSTRACT A high speed MOS digital circuit simulation program PNAP-1 (Parallel Network Analysis Program) implemented on a special-purpose parallel computer system LINKS-1 is described. In LINKS-1, 64 node computers are linked radially to a root computer through a very fast memory swapping unit. The task of the root computer is to control node computer and to store waveforms. Each node computer solves assigned subcircuit with standard circuit simulation techniques. PNAP-1 adopts a block-type waveform relaxation technique as a vehicle of the parallel computation of required waveforms. The slow convergence or more serious non-convergence problem inherent to relaxation-based methods is alleviated by analyzing tightly coupled portions in direct manner in conjunction with exploiting the overall quasi-unidirectional property of MOS digital circuits. A number of experimental results show that PNAP-1 can achieve a substantial speed improvement in the cost-effective analysis of VLSI circuits. REFERENCES [1] E. Lelarasmee "The waveform relaxation method for time domain analysis of large scale integrated circuits: Theory and applications" Ph.D. dissertation, Univ. of California, Berkeley, 1982. [2] J. White and A. Sangiovanni-Vincentelli, "RELAX2: A new waveform relaxation approach for the analysis of LSI MOS circuits" Proc. 1983 ISCAS, pp. 756-759, 1983. [3] H. Nishimura et al. "Links-1: A parallel pipelined multimicrocomputer system for image creation" Proc. 10th Annual Int. Symp. Computer Architecture, pp. 387-394, 1983. [4] H. Deguchi et al. "A parallel processing scheme for three-dimensional image generation" Proc. 1984 ISCAS, pp. 1285-1288, 1984


Accelerating Relaxation Algorithms for Circuit Simulation Using Waveform Newton, Iterative Step Size Refinement, and Parallel Techniques Jacob White, Resve Saleh, A. Sangiovanni-Vincentelli, A. R. Newton Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley

Abstract Two techniques are considered for accelerating relaxation-based circuit simulators. First, a new algorithm that attempts to combine the advantages of the Waveform Relaxation algorithm and Iterated Timing Analysis relaxation algorithm for moderately coupled multirate systems is presented. The algorithm is based on the extension to function spaces of the relaxation-Newton methods popular for solving algebraic systems. This Waveform Relaxation-Newton(WRN) technique is combined with an iterative stepsize refinement scheme which improves the accuracy of the numerical integration as the relaxation iterations approach convergence. As a second approach to accelerating relaxation algorithms, two techniques for parallelizing the classical WR algorithm are described, one based on mixed Gauss-Seidel/Gauss-Jacobi techniques, and the other on pipelining the computation. Finally, a technique for parallelizing WRN is described. REFERENCES [1] L. W. Nagel "SPICE2: A computer program to simulate semiconductor circuits" Electronics Research Laboratory Rep. No. ERL-M520, University of California, Berkeley, May 1975. [2] B. R. Chawla, H. K. Gummel, and P. Kozak "MOTIS - an MOS timing simulator" IEEE Trans. Circuits and Systems, Vol. 22, pp. 901-909, 1975 [3] C. F. Chen and P. Subramaniam "The Second Generation MOTIS Timing Simulator -- An Efficient and Accurate Approach for General MOS Circuits" Proc. 1984 Int. Symp. on Circ. and Syst., Montreal, Canada, May 1984. [4] K. Sakallah and S.W. Director "An activity-directed circuit simulation algorithm" Proc. IEEE Int. Conf. on Circ. and Computers, October 1980, pp. 1032-1035 [5] R. A. Saleh, J. E. Kleckner and A. R. Newton "Iterated Timing Analysis and SPLICE1" ICCAD '83 Digest, Santa Clara, CA., 1983. [6] E. Lelarasmee, A. E. Ruehli, A. L. Sangiovanni-Vincentelli, "The waveform relaxation method for time domain analysis of large scale integrated circuits" IEEE Trans. on CAD of IC and Syst., Vol. 1, n. 3, pp.131-145, July 1982. [7] J. White and A. Sangiovanni-Vincentelli "Relax2.1 - A Waveform Relaxation Based Circuit Simulation Program" Proc. 1984 Int. Custom Integrated Circuits Conference Rochester, New York, June 1984. [8] E. Lelarasmee. Private Communication, October, 1981 [9] M. Guarini and O. A. Palusinski "Integration of Partitioned Dynamical Systems using Waveform Relaxation and Modified Functional Linearization" 1983 Summer Computer Simulation Proceedings, vancouver, Canada, July 1983.

[10] W. M. G. van Bokhoven "An Activity Controlled Modified Waveform Relaxation Method" 1983 Conf. Proc. IEEE ISCAS, Newport Beach, CA, May 1983. [11] J. T. Deutsch "Algorithms and Architecture for Multiprocessor-Based Circuit Simulation" Ph.D. dissertation, U. C. Berkeley, Electronics Research Laboratory, 1985. [12] J. M. Ortega and W. C. Rheinbolt. Iterative Solution of Non-linear Equations in Several Variables. Academic Press, 1970. [13] J. White, F. Odeh, A. Sangiovanni-Vincentelli, A. Ruehli "Waveform Relaxation - Theory and Practice" Trans. on Computer Simulation, To appear.

ICCAD85 – 1B.1, Pages 10-12

Derivation and Refinement of Fanout Constraints to Generate Tests in Combinational Logic Circuits Ki Soo Hwang, M. Ray Mercer Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Tx 78712

ABSTRACT In this paper, we analyze combinational logic circuits using "fanout constraints" to generate tests for single stuck-at faults. A method of circuit transformation from a nontree type circuit to a pseudo tree type circuit is employed to explicitly derive the "fanout constraints" for controllability (the fanout constraints for controlling every node in the circuit to a logic value "0" and "1".) Then the fanout constraints for the detection of a given fault are generated and refined to obtain a test. This approach differs from earlier work in that information about the circuit is accumulated and refined as the test generation process proceeds. In this test generation algorithm, the dependencies among fanout nodes are ordered and solved in a hierarchical fashion so that the computation time for generating tests can be greatly reduced. References [1] J.P. Roth "Diagnosis of Automata Failure: a Calculus and a Method" IBM J. Research Develop., Vol. 10, July 1966, pp. 278-291. [2] P. Goel "An Implicit Enumeration Algorithm to Generate Tests for Combinational Circuits" IEEE Trans. Comput., Vol. C-30, Mar. 1981; pp. 215-222. [3] H. Fujiwara, and T. Shimono "On the Acceleration of Test Generation Algorithms" IEEE Trans. Comput., Vol. c-32, No. 12, Dec. 1983, pp. 1137-1144. [4] F.F. Sellers, M.Y. Hsiao, and L.W. Bearnson "Analyzing Errors with the Boolean Difference" IEEE Trans. Comput., Vol. EC-17, July 1968, pp. 676-683.


RFSIM: Reduced Fault Simulator Takao Nishida, Shunsuke Miyamoto, Tokinori Kozawa Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan

Katsuya Sato Kanagawa works, Hitachi Ltd., 1 Horiyamashita Hatano, Kanagawa 244, Japan

ABSTRACT This paper describes the algorithm, implementation and evaluation results of a new fault simulator called RFSIM. RFSIM is designed for combinational circuits, and is more than 10 times faster than a conventional concurrent fault simulator. Blocking gate information is newly introduced to achieve a drastic reduction in the number of faults to be simulated. REFERENCES [1] E.B. Eichelberger and T.W. Williams "A Logic Design Structure for LSI Testability" Proc. 14th DA Conf., 1977, pp. 462-468. [2] D. Komonytsky "LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis" Proc. Int. Test Conf., 1982, pp. 414-424. [3] M. Abramovici et al. "Critical Path Tracing - An Alternative to Fault Simulation" Proc. 20th DA Conf., 1983, pp. 214-220. [4] S.K. Jain and V.D. Agrawal "STAFAN : An Alternative to Fault Simulation" Proc. 21th DA Conf., 1984, pp. 18-23. [5] E.G. Ulrich et al. "Fault-test analysis techniques based on logic simulation" DA workshop, 1972, pp. 111-115. [6] S.J. Hong "Fault simulation strategy for combinational logic networks" Proc. FTCS-8, 1978, pp.96-99. [7] P. Goel et al. "PODEM-X : An Automatic Test Generation System for VLSI Logic Structure" Proc. 18th DA Conf., 1981, pp. 260-268. [8] E.G. Ulrich et al. "The concurrent simulation of nearly identical digital networks" Proc. 10th DA Conf., 1973, pp. 145-150. [9] S. Goshima, T. Kozawa et al. "Diagnostic System for Large Scale Logic Cards and LSI's" Proc. 18th DA Conf., 1981, pp. 256-259.

ICCAD85 – 1C.1, Pages 18-20

The ICD Design Management System T. G. R. van Leuken P. van der Wolf Department of Electrical Engineering, Delft University of Technology, The Netherlands

ABSTRACT To organize the design process of VLSI circuits and the design evolution involved, a design data management system is needed that supports reliable storage, concurrency control, hierarchical decomposition, multilevel design and version control. A design system data scheme can be based on a semantic (object oriented) data model, where objects are used for modeling the structures imposed on the design data. Using the basic constructs of the data model a data scheme can be defined that reflects the object types and their relationships encountered in VLSI designs. A dominant part of the design data management system is the transaction manager, supporting versions and concurrency control. In our version mechanism some of the versions of each cell have a special status, thereby allowing automated selection of the right version on a certain request. This version mechanism offers the user a clear conceptual picture and supports the evolutionary development of a design in a highly automated fashion. REFERENCES [1] R. H. Katz, S. Weiss "Design transaction Management" Proc. 21st DAC, Alburquerque NM, 1984, pp. 692-693. [2] P. Lyngbaek "Information Modeling and Sharing in Highly Autonomous Database Systems" PhDDissertation Univ. of Southern California, Aug. 1984. [3] D. W. Shipman "The Functional Data Model and the Data Language DAPLEX" ACM Trans. on Database Systems, Vol. 6, No. 1, March 1981, pp. 140-173. [4] G. Wiederhold, A. Beetem, G. Short "A Database Approach to communication in VLSI design" IEEE Trans. on CAD vol. 1, no. 2, April 1982. [5] T. Vogel, P. v.d. Wolf, P. Dewilde "Conceptual database model ICD" Internal Report, Delft. Univ. of Techn., 1984.


CLIB - A Database Management System Designed for Standard Cell Applications Ed Lechner Harris Corporation, Semiconductor Sector, P. O. Box 883, Melbourne, FL 32901

ABSTRACT CLIB is a specialized data base management system (DBMS) which solves the problems associated with creating, maintaining, and controlling multiple standard cell libraries in a multi-user, multi-computer environment. While CLIB was primarily created with standard cell and gate array applications in mind, it can be used in many other applications utilizing time dependent, cell oriented data. The result of CLIB is a DBMS around which a comprehensive and evolving Design Automation system involving time dependent cellular data has been implemented. REFERENCES [1] Date, C. J. An Introduction to Data Base Systems, 3rd ed. Addison-Wesley, 1982. [2] Hollaar, L., Nelson, B., Carter, T., and Lorie, R. "The Structure and Operation of a Relational Database System in a Cell-Oriented Integrated Circuit Design System". Proceedings of The 21st Design Automation Conference, pp 117-125, 1984. [3] Kim, W. CAD Database Requirements - Revision 0.5. Microelectronics and Computer Technology Corporation. Database Program Document No. (mcc/db/ddb/72/Rev.0/850430), 1985. [4] Kim, W. and Banerjee, J. Support of Abstract Data Types in a CAD Database System. Microelectronics and Computer Technology Corporation. Database Program Document No. (mcc/db/ddb/76/Rev.1/850506), 1985.


A New Robust Relaxation Technique for VLSI Circuit Simulation M.E. Mokari-Bolhassan, D. Smart, T.N. Trick Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University of Illinois at Urbana, Illinois 61801

ABSTRACT A new robust relaxation technique based on overlapped partitioning of VLSI circuits is presented. Each partition consists of a subcircuit with its immediate fanout circuits. Only the variables beyond the adjacent fanout circuits are relaxed, while the couplings between the subcircuit and its fanout circuits are left intact. In the analysis of each partition, the solutions for the variables of the subcircuit is retained but the solutions for the fanout circuits are discarded. The next partition overlaps the previous partition and contains one of the fanout circuits along with its fanout circuits. This overlapped relaxation method has better convergence properties due to smaller error introduced at each step compared to standard relaxation techniques. Furthermore, the method has been used to successfully analyze bipolar circuits. Typically accurate waveforms can be obtained with only one iteration. Thus, the additional computational overhead which results from overlapping the partitions appears to be justifiable. REFERENCES [1] W. Nagel "SPICE2, A Computer Program to Simulate Semiconductor Circuits" Univ. of California, Berkeley, Memo No. ERL-M520, May 1975. [2] Ping Yang "An Investigation of Ordering, Tearing, and Latency Algorithms for the Time Domain simulation of Large Circuits" Coordinated Science Laboratory, University of Illinois, Champaign-Urbana, Report R-891, 1980. [3] E. Lelarasmee, A.E. Ruehli and A.L. Sangiovanni-Vincentelli "The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits" IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, No. 3, July 1982. [4] R. Saleh and A.R. Newton "Iterated Timing Analysis in SPLICE1" Proceedings of the IEEE ICCAD, Santa Clara, CA, September 1983, pp. 139-140. [5] W.K. Chia, T.N. Trick and I.N. Hajj "Stability and Convergence Properties of Relaxation Methods for Hierarchical Simulation of VLSI Circuits" Proceedings of the IEEE International Symposium on Circuits and Systems, Montreal, Canada, pp. 848-851, May 1984. [6] M.E. Mokari-Bolhassan and T.N. Trick "A New Iterative Algorithm for the Solution of Large Systems" Proceedings of the 28th Midwest Symposium on Circuits and Systems, University of Louisville, Kentucky, August 19-20, 1985. [7] J. White and A.L. Sangiovanni-Vincentelli "Partitioning and Parallel Implementations of Waveform Relaxation Algorithms for Circuit Simulation" Proceedings of the IEEE Symposium on Circuits and System, Kyoto, Japan, pp. 221-224, June 1985.


WASIM: A Waveform Based Simulator for VLSICs Sani R. Nassif, Stephen W. Director Electrical and Computer Engineering Department, Carnegie-Mellon University, Pittsburgh, Pennsylvania 15213

Abstract A new approach for simulation of cell-based digital MOS designs has been developed which is aimed at achieving circuit level accuracy with logic level speed. This approach exploits the regularity which is typical of large VLSI designs by building macromodels of individual cells. These macromodels are generated from parameterized analytical models which characterize the waveforms produced by typical device-level output stage topologies. Inputs of these macromodels are designable parameters such as layout, as well as circuit parameters such as fan-out. An event-driven, waveform-based simulator, called WASIM has been developed which employs these macromodelled cells. References [1] B.R. Chawla, H.K. Gummel and P. Kozak. MOTIS- An MOS timing simulator. IEEE Trans. Circuits Syst, CAS-22(12):901-909, December, 1975. [2] M.D. Matson. Macromodeling of Digital MOS VLSI Circuits. Technical Report VLSI Memo 84-212, MIT, 1984. [3] K. Okazaki, T. Moriya and T. Yahara. A Multiple Media Delay Simulator for MOS LSI Circuits. In Proceedings of 1983 DA Conference, IEEE, 1983. [4] J.K. Ousterhout. Switch-Level Delay Models for Digital MOS VLSI. In Proceedings of 1984 DA Conference. IEEE, 1984. [5] K.A. Sakallah. Mixed Simulation of Electronic Integrated Circuits. PhD thesis, Carnegie-Mellon University, November, 1981. [6] T. Taki. Approximation of JFET Characteristics by a Hyperbolic Function. IEEE Journal of Solid-State Circ. SC-13(5), October, 1978. [7] T. Tokuda et. al. Delay-Time Modeling of ED MOS Logic LSI. IEEE Trans. CAD CAD-2(3), July, 1983.


Waveform Relaxation and Dynamic Partitioning for the Transient Simulation of Large Scale Bipolar Circuits Guy Marong, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley

ABSTRACT Relaxation methods have been extensively applied to the transient analysis of MOS digital circuits, but, so far, they have given poor results for bipolar circuits. In this paper we show that Waveform Relaxation techniques (WR) can be successfully extended to bipolar circuits. This is possible by introducing a new technique called dynamic partitioning. Partitioning is essential to obtain fast convergence of relaxation-based simulation. In the MOS case, partitioning is a pre-processing step aimed at recognizing strongly coupled nodes. The resulting decomposition obtained is maintained throughout the entire simulation interval. In the bipolar case, this technique cannot be applied because the coupling between the nodes of the circuits vary by orders of magnitude depending on the region of operation of the devices in the circuit. Thus, the circuit has to be re-partitioned whenever part of the circuit has changed its region of operation. Dynamic partitioning implements this policy. Experimental results with bipolar circuits of various technologies (ECL, TTL, STTL) show that this technique makes WR significantly faster than standard circuit simulation techniques. REFERENCES [LEL82] E. Lelarasmee, A.E. Ruehli, A.L. Sangiovanni-Vincentelli "The waveform relaxation method for time domain analysis of large scale integrated circuits" IEEE Trans. on CAD of IC and Sys., vol. 1, no. 3, pp. 131-145, July 1982. [NAG75] L.W. Nagel "SPICE2: A computer program to simulate semiconductor circuits" Electronics Research Laboratory Rep. No. ERL-M520, University of California, Berkeley, May 1975. [WHI84] J. White and A. Sangiovanni-Vincentelli "Relax2.1 - A Waveform Relaxation based Circuit Simulation Program" Proc. 1984 Int. Custom Integrated Circuits Conference Rochester, New York, June 1984. [WHI85] J. White and A. Sangiovanni-Vincentelli "Partitioning algorithms and parallel implementations of Waveform Relaxation algorithms for circuit simulation" Conf. Proc. IEEE ISCAS, June 1985.


Multiple-Fault Test Sets for MOS Complex Gates F. Joel Ferguson, John P. Shen Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA. 15213

Abstract This paper characterizes test sets that detect multiple faults in MOS circuits guided by the observation that such circuits are implemented as a network of switches. First the sufficient conditions for a test set that detects all multiple faults in an nMOS complex gate are described. We show that this test set exists for any fanout free, irredundant circuit and derive bounds on its length. Then two special classes of complex gates are considered and optimal test sets are shown for them. The paper then describes tests for circuits with fanout and shows that, with moderate fanout, very good multiple fault coverage is provided. Finally, the circuit model and the test set results are shown to be applicable to CMOS circuits and to larger circuits containing multiple complex gates. References [1] P. Banerjee & J.A. Abraham. "Fault Characterization of VLSI MOS Circuits". In Proc. FTCS. 1982. [2] N.K. Jha & J.A. Abraham. "Testable CMOS Logic Circuits under Dynamic Behavior". In Proc. ICCAD. 1984. [3] S.M. Reddy, V.D. Agrawal & S.K. Jain. "A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection". In Proc. DAC. 1984. [4] K. Chiang & Z.G. Vranesic. "Test Generation for MOS Complex Gate Networks." In Proc. FTCS. 1982. [5] K. Chiang & Z.G. Vranesic. "On Fault Detection in CMOS Logic Networks". In Proc. DAC. 1983. [6] S.K. Jain & V.D. Agrawal. "Modeling & Test Generation Algorithms for MOS Circuits". IEEETC, May, 1985. [7] Y.M. El-Ziq & S.Y.H. Su. "Fault Diagnosis of MOS Combinational Networks". IEEETC, Feb., 1982. [8] J.P. Shen, W. Maly & F.J. Ferguson. "Inductive Fault Analysis of nMOS and CMOS Integrated Circuits". Technical Report, ECE Dept. Carnegie-Mellon University, Aug., 1985. [9] R.L. Wadsack. "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits". BSTJ, May-June, 1978.


Towards A Switch-Level Test Pattern Generation Program Scott H. Robinson, John P. Shen Department of Electrical and Computer Engineering, Carnegie-Mellon University, Schenley Park, Pittsburgh, PA. 15213

Abstract A switch-level automatic test pattern generation algorithm targeted for static CMOS combinational circuits is presented. The algorithm employs a combination of algebraic and circuit topology techniques. A circuit is partitioned into a network of subcircuits, each of which is modeled as an arbitrarily connected relay-switch network with a set of control inputs and primary terminals. A Boolean transmission function is generated for every pair of primary terminals. Several cube tables, many analogous to those used in the D-Algorithm, for each subcircuit are precomputed, stored, and referenced during test generation. References [1] M.A. Breuer & A.D. Friedman Diagnosis & Reliable Design Of Digital Systems. Computer Science Press, Inc., 1976. [2] S.K. Jain & V.D. Agrawal Modeling and Test Generation Algorithms for MOS Circuits. IEEETC, May, 1985. [3] S.M. Reddy, V.D. Agrawal, & S.K. Jain A Gate Level Model For CMOS Combinational Logic Circuits with Application To Fault Detection. In Proc. DAC. June, 1984. [4] R.L. Wadsack Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits. BSTJ, May-June, 1978. [5] J.P. Roth, W.G. Bouricius, & P.R. Schneider Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits. IEEETC, October, 1967. [6] R. Bryant MOSSIM: A Switch-Level Model and Simulator for MOS Digital Systems. IEEETC, February, 1984. [7] M. Kawai & J.P. Hayes An Experimental MOS Fault Simulation Program CSASIM. In Proc. DAC. June 1984. [8] H.H. Chen, R.G. Mathews, & J.A. Newkirk Test Generation For MOS Circuits. In Proc. ITC. October, 1984. [9] Y.M. El-ziq & R.J. Cloutier Functional-Level Test Generation For Stuck-Open Faults In CMOS VLSI. In Proc. ITC. 1981. [10] P. Agrawal Test Generation At Switch Level. In ICCAD. 1984. [11] K.W. Chiang & Z.G. Vranesic Test Generation For MOS Complex Gate Networks. In Proc. FTCS. June, 1982.

[12] F.E. Hohn & L.R. Schissler Boolean Matrices and the Design of Combinational Relay Switching Circuits. BSTJ, January, 1955.


Effect of Supply Voltage on Circuit Propagation Delay and Test Applications K.D. Wagner, E.J. McCluskey Center for Reliable Computing, Computer Systems Laboratory Depts. of Electrical Engineering and Computer Science, Stanford University, Stanford, CA. 94305

ABSTRACT Theoretical models were developed to predict the propagation delay of circuit elements for a range of supply voltages in different technologies. The models were verified by circuit simulation using the SPICE2 program. Results indicate that circuits in a number of technologies are quite sensitive to their supply voltage levels. This behavior can be exploited for testing integrated circuit timing. These suggested test applications reduce the precision requirements of delay testing and allow for the simulation of stresses encountered in the normal machine environment. REFERENCES [AlHussein82] Al-Hussein, H., and R. W. Dutton "Path Delay Computation for Integrated Systems" in Proc. ICCC-82, pp. 426-430, 1982. [Hsieh77] Hsieh, E., R. Rasmussen, L. Vidunas, and W. Davis "Delay Test Generation" in Proc. 14Th D.A. Conf., pp. 486-491, 1977.


An MOS Fault Simulator with Timing Information Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham Computer System Group, Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield Ave. Urbana, IL 61801

ABSTRACT This paper describes an MOS fault simulator which produces output waveforms for circuits under realistic physical failures. The basic primitives of the fault model for this simulator are node-short faults and line-open faults. This simulator uses a table lookup of the transistor I-V characteristics as well as a newly proposed static concurrent fault simulation technique to simulate both the fault-free circuit and many faulty circuits in one pass. Both single and multiple faults can be inserted into each faulty circuit. The simulator can either plot the voltage waveforms, or extract both the logic and delay values for both the fault-free circuit and the faulty circuits from the waveforms. This is intended as a powerful tool for characterizing the behavior of circuits under realistic physical failures. REFERENCES [1] E. W. Thompson, S. A. Szygenda, N. Billawala, and R. Pierce "Timing Analysis for Digital Fault Simulation Using Assignable Delays" Proc. 11th Design Automation Workshop, Denver, CO, June 1974. [2] Yu-Huei Jea and Hsi-Ching Shih "A Digital Fault Simulation System Based on Three-Value PreciseDelay Model" Proceedings of International Computer Symposium 1980 (Vol. II), Taipei, Taiwan, Republic of China, pp. 1158-1170. [3] Randal E. Bryant and Michael D. Schustor "Fault Simulation of MOS Digital Circuits" VLSI DESIGN, Oct. 1983, pp. 24-30. [4] Prithviray Banerjee and Jacob A. Abraham "Fault Characterization of VLSI MOS Circuits" IEEE International Conference On Circuits and Computers (ICCC '82), New York, pp. 564-568. [5] A. K. Bose, P. Kozak, C-Y Lo, H. N. Nham, E. Pacas-Skewes, and K. Wu "A Fault Simulator for MOS LSI Circuits" Proceedings of the 19th Design Automation Conference, 1982, Las Vegas, NV, pp. 400-409. [6] J. Galiay, Y. Crouzet, and M. Vergniault "Physical versus Logical Fault Models MOS LSI Circuits: Impact on their Testability" IEEE Transactions On Computers, vol. C-29, no.6, June 1980, pp. 527-531. [7] William A. Rogers and Jacob A. Abraham "CHIEFS: A Concurrent, Hierarchical and Extensible Fault Simulator" IEEE International Test Conference, Philadelphia, PA, November 1985. [8] Ramachandra P. Kunda, Michael McDonald, Jacob A. Abraham, and Edward S. Davidson "Hierarchical Design Rule Checking and Circuit Extraction Techniques" Computer System Group Working Paper 84-36, Univ. of Illinois, Urbana, IL, December, 1984. [9] P. Banerjee "A Model for Simulating Physical Failures in MOS VLSI Circuits" M. S. Thesis, Tech. Rept. CSG-13, Coordinated Science Laboratory, Univ. of Illinois, Urbana, IL, Jan. 1983.


Schema An Architecture for Knowledge Based CAD G. C. Clark Harris GSS, P. O. Box 37, Melbourne, FL 32902, USA

R. E. Zippel MIT Laboratory for Computer Science, Cambridge, MA 02139, USA

Abstract Schema provides an integrated environment for all aspects of the synthesis and analysis of electronic designs from PC boards through circuit and mask design of VLSI devices. It simplifies the development of synthesis and analysis tools by using uniform data structures and by making available libraries of standard routines and advanced control structures appropriate for CAD tool development. Because all tools in the Schema environment utilize the same abstract data structures it is easy for tools to interchange data about a design or even pieces of the design itself. Schema also permits much of the design to be done in a technology independent fashion by allowing the designer to delay implementation decisions until the last possible moment. The information associated with a particular component of a design is organized as a module. Modules contain schematics, icons, topologies, layouts, simulation results, and other descriptive information for this component. The descriptions contained in modules are implemented as procedures which utilize other modules in a hierarchical fashion. Schema is under joint development by MIT and Harris Corporation. References [1] J. Batali and A. Hartheimer "The Design Procedure Language Manual" MIT Artificial Inteligence Laboratory Report 598, 1980. [2] M. Rose A Datapath Generator. B. S. Thesis, Dept. EECS, Massachusetts Institute of Technology, June 1982. [3] G. J. Sussman "SLICES: At the Boundary between Analysis and Synthesis" Proc: Artificial Intelligence and Pattern Recognition in Computer Aided Design, IFIP WG 5.2, Grenoble, France, 1978. [4] D. L. Weinreb and D. A. Moon Lisp Machine Manual. MIT Artificial Intelligence Laboratory, Cambridge, MA, 1981. [5] R. Zippel "Capsules" SIGPLAN Bulletin, vol. 18, no. 6, pp. 166-169, 1983.


Using a Database System and UNIX to Author CAD Applications Martin Hardwick, Nisar Yakoob Department of Electrical Engineering/Computer Science, Texas Tech University, Lubbock, Texas 79409

INTRODUCTION Authoring systems help software developers to build applications. Computer aided instruction applications have been built using authoring systems for a number of years. Recently, several authoring systems for expert systems have been announced. [10] In this paper we describe an experiment which used an engineering database system and an operating system to author a CAD application. Engineering database systems manage and maintain the data of engineering applications. [6] An engineering database system can be used in an authoring system for CAD applications to manage the data of a CAD application. Operating systems allow processes to communicate. An operating system can be used in a CAD application to manage the communication between the components of an application. A sophisticated operating system will allow the components to be written as a set of re-usable software tools. The experiment described in this paper used the UNIX operating system and a locally developed engineering database system [4] to author an integrated circuit layout application. The experiment showed that these tools can be used to construct CAD applications of reasonable complexity. The result is important because a new database system for CAD will not have any client applications. These applications must be produced by either modifying existing applications or constructing new applications. An authoring system will make it easier to construct new applications. REFERENCES [1] J.R. Breiland and T.J. Thompson "Designer's Workbench: Delivery of CAD tools" Proc. 19th Design Automation Conf., IEEE Computer Society. [2] J.D. Crawford "EDIF: A mechianism for the exchange of design information" IEEE Design & Test of Computers, Feb. 1985, IEEE Computer Society. [3] A. Guttman "New features for a relational database system to support computer aided design" Ph.D. thesis, Univ. of California-Berkeley (1984). [4] M. Hardwick "Extending the relational database datamodel for design applications" Proc. 18th Design Automation Conf., IEEE Computer Society (1984). [5] M.N. Haynie "The relational network model for design automation databases" Proc. 18th Design Automation Conf., IEEE Computer Society (1981). [6] R.H. Katz "Managing the chip design database" IEEE Computer, Dec. 1983.

[7] R.A. Lorie "Issues in databases for design applications" File Structures and Databases for CAD, J. Encarnacao (ed.), North Holland (1982). [8] A.R. Newton, et al. "Design aids for VLSI: The Berkeley Perspective" IEEE Trans. on Circuits and Systems, July 1981. [9] C. Mead and L. Conway "Introduction to VLSI Systems" Addison-Wesley, New York. [10] K. Paul "Software tools speed expert system development" High Technology, March 1985. [11] W. Plouffe, et al. "A database system for engineering design" 19th Design Automation Conf., IEEE Computer Society (1982). [12] J.L. Sanborn "Evolution of the engineering design system database" Proc. 19th Design Automation Conf., IEEE Computer Society (1982). [13] G. Sinha "Optimization of engineering design databases" M.S. thesis, Texas Tech Univ., Lubbock, TX. [14] M. Stonebraker, et al. "Application of abstract data types and abstract indices to CAD databases" Engineering Design Applications, Database Week, IEEE Computer Society, 1983. [15] P. Winston "Artificial Intelligence" 2nd Ed., Addison-Wesley, New York, p. 39.


A VLSI Cell Synthesizer with Structural Constraint Considerations Meng-Lin Yu, William J. Kubitz Department of Computer Science, University of Illinois at Urbana-Champaign, 1304 W. Springfield Ave. Urbana, IL 61801-2987

Abstract A cell synthesizer, which uses a Gate Matrix or a Weinberger Array as the synthesis model and produces a layout under structural constraints, along with its topology cleanup phase algorithm is presented. Two different optimizations are used in the cell synthesizer. On the abstract level, linear time algorithms based on interval graph minimization for a one-dimensional array linear ordering problem which are design rule independent are used. The topology optimization algorithm used in the cleanup phase for generating devices and interconnect on the virtual grid and sharing features on a grid line is technology dependent. I/O Constraints are modeled as pseudo logic which is optimized simultaneously with the real logic gates. Pass transistors are similarly modeled such that a uniform interval graph optimization method can be used. The cell synthesizer is part of a random logic module generator for the automated chip design system described in [1]. References [1] M.-L. Yu. Automatic Random Logic Layout Synthesis - A Module Generator Approach. Ph.D Thesis Proposal, 1985. [2] Y.-C. Hsu, W.J. Kubitz. Automatic Placement Using Wavefront Compaction. Proc. of ICCD, 1985. [3] S. Healey, W.J. Kubitz. Abstract Partitioning of Logic Networks for Custom Module Generation. Digest of ICCAD, 1985. [4] M.-L. Yu, W.J. Kubitz. Linear-Time Heuristics for Cell Layout Synthesis Under Constraints. Digest of ICCAD, 1985. [5] A. Lopez, and H.F. Law. A Dense Gate Matrix Layout Method for MOS VLSI. IEEE JSSC, Vol. SC15, No.4., August 1980, pp. 736-740. [6] I. Shirakawa. A Layout System for the Random Logic Portion of an MOS LSI Chip. IEEE Transactions on Computers, Vol. C 30, No.8, August 1981, pp.573-581. [7] J. Luhukay. Automatic Layout for NMOS Gate Cells. University of Illinois at Urbana-Champaign, Department of Computer Science, Report UIUCDCS-R-83-1099, 1983. [8] C. Lursinsap, and D. Gajski. Cell Compilation with Constraints. Proc. of 21st DAC, June 1984, pp.103108. [9] T. Ohtsuki, et al. One-Dimensional Logic Gate Assignment and Interval Graphs. IEEE Transactions on CAS, Vol. CAS-26, No. 9, September 1979, pp.675-684. [10] O. Wing. Interval-Graph-Based Layout. Digest of IEEE ICCAD, 1983, pp.84-85. [11] J.-T. Li. Algorithms for Gate Matrix Layout. Proceedings of IEEE ISCAS, July 1983.

[12] F.D. Brewer. HCL - A System for Hierarchical Layout. University of Illinois at Urbana-Champaign, Department of Computer Science, Report UIUCDCS-R-84-1194, 1984.


Cell Libraries for Silicon Compilers Jon A. Solworth Department of Computer Science, Cornell University, Ithaca, New York 14853

Abstract A cell generator system called Flexcell is described. This system produces extremely high quality cells in terms of both speed and layout. Moreover, layout can be optimised not only for minimum area but also to meet constraints such as "the cell should be as wide as possible up to 20 lambda". The Flexcell system uses a mechanism for specifying cells called templates. Templates are layout schemas which produce stylized layouts (roughly equivalent to sticks diagrams) which are generated under program control. Layout produced from templates may be modified by both general and special purpose layout tools including compactors, aspect ratio modifiers and routers. One goal of the Flexcell system is to make maximal use of general purpose mechanisms thereby employing as little special purpose code as possible. Flexcell relies critically on its implementation language GENERIC. GENERIC is a language for VLSI design which provides operator based, design rule embedded and connectivity maintaining layout specification and manipulation. A GENERIC layout begins with a circuit description, from which a layout is derived. References [Joha79] D. Johansen "Bristle Blocks: a silicon compiler" Proceedings of the Sixteenth Design Automation Conference, June 1979, pp. 310-313. [SSC82] J. M. Siskind, J. R. Southard and K. W. Crouch "Generating custom high performance VLSI designs from succinct algorithmic descriptions" MIT Conference on Advanced Research in VLSI, Jan 2527 1982, pp. 28-40. [Shro82] H. E. Shrobe "The data path generator" MIT Conference on Advanced Research in VLSI, Jan. 2527 1982, pp. 175-181. [BRLK83] W. A. Barrett, B. Rogers, R. Lathrop, and A. Kuchinsky "An extensible data path generator" ICCAD-83. [MaNe84] J. Newkirk and R. Mathews. The VLSI designer's nMOS library. Addison-Wesley, 1984. [NSDK84] S. Nance, C. Starr, B. Duyn, M. Kliment "Cell-layout compilers simplify custom IC design" EDN Magazine, Sept. 15 1983. [WNM83] W. Wolf, J. Newkirk and R. Mathews "Dumbo, a schematics to layout compiler" 3rd Caltech Conf. on Adv. Research in VLSI, pp. 379-393, 1983.

[Solw85] J. A. Solworth "The GENERIC programming language manual" CS Tech Report, Cornell University, Ithaca, N.Y., Aug. 1985. [Will80] J. Williams "Symbolic artwork systems" Lambda, Second Quarter, 1980.


Linear-Time Heuristics for Cell Layout Synthesis Under Constraints Meng-Lin Yu, William J. Kubitz Department of Computer Science, University of Illinois at Urbana-Champaign, 1304 W. Springfield Ave. Urbana, IL 61801-2987

Abstract In this paper two new efficient algorithms are presented which produce a layout for a digital VLSI circuit under structural constraints in the style of a Gate Matrix or a onedimensional gate array. By using the properties of circuit connectivity matrix sparsity and edge coherence, the time and space complexities are bounded by O(N), where N is the input size, compared with the best previous result, O(N2), obtained without consideration of any structural constraints. The algorithms are used by a cell synthesizer which is part of a module generator in an automated chip design system. Reference [1] T. Ohtsuki, et al. One-Dimensional Logic Gate Assignment and Interval Graphs. IEEE Transactions on Circuits and Systems, Vol. CAS-26, No. 9, September 1979, pp.675-684. [2] T. Kashiwabara, and T. Fujisawa. NP-Completeness of the Problem of Finding a Minimum-CliqueNumber Interval Graph Containing a Given Graph as a Subgraph. Proc. IEEE ISCAS, 1979, pp.657-660. [3] O. Wing. Automatic Gate Matrix Layout. Proc. of IEEE Circuits and Systems Symposium, 1982, pp. 681-685. [4] O. Wing. Interval-Graph-Based Layout. Digest of IEEE ICCAD, 1983, pp.84-85. [5] J.-T. Li. Algorithms for Gate Matrix Layout. Proceedings of IEEE ISCAS, July 1983. [6] D.D. Gajski. The Structure of a Silicon Compiler. Proceedings of the ICCC, October 1982, pp. 272276. [7] C. Lursinsap, and D. Gajski. Cell Compilation with Constraints. Proc. of 21st DAC, June 1984, pp.103108. [8] M.-L. Yu. Automatic Random Logic Layout Synthesis - A Module Generator Approach. Ph.D Thesis Proposal, 1985. [9] S. Goto. A Two-Dimensional Placement Algorithm for the Master Slice LSI Layout Problem. Proc. of 16th DAC, June 1979, pp.11-17. [10] M. Hanan, P.K. Wolff, Sr., and B.J. Agule. A Study of Placement Techniques. Design Automation & Fault-Tolerant Computing, 1979, pp.28-61. [11] M. Burstein. Partitioning of VLSI Networks. IBM Research Report, RC 9180, 1981.


Efficient Testing and Truth Table Verification of Unilateral Combinational Iterative Arrays E.M. Aboulhamid Dep. d'Informatique et de Rech. Operationnelle, Universite de Montreal, C.P. 6128, Succ. A, Que. H3C 3J7 Canada

ABSTRACT This paper considers the problem of reducing the number of tests for C-testable and PItestable one-dimensional unilateral iterative arrays. It also restates the conditions for obtaining truth table verification of an array [Dias1976] and, thus, corrects a theorem on the testing of adders. References [Aboulhamid 1984] ABOULHAMID E.M. "Contributions a la conception de circuits logiques a tests incorpores" these de Ph.D., Dep. IRO, Universite de Montreal, juillet 1984. [AboulhamidCerny1984] ABOULHAMID E.M., CERNY E., (1984) "Built-in-Testing of One-dimensional Unilateral Iterative Arrays" IEEE Trans. Comput., vol. C-33, no. 6, june 1984, 560-564. [Dias1976] DIAS F.J.O. (1976) "Truth-Table Verification of an Iterative Logic Array" IEEE Trans. Comput., vol. C25, no. 6, June 1976, pp. 605-613. [SridharHayes1979] SRIDHAR T., HAYES J.P. (1979) "Testing Bit-Sliced Systems Microprocessors" Proc. 9th Fault-Tolerant Computing Symp., VW1, 1979, pp. 211-218.


A Shortest Length Test Sequence for Sequential-Fault Detection in Ripple Carry Adders Wu-Tung Cheng, Janak H. Patel Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana, IL 61801

ABSTRACT It is known that a ripple carry adder composed of several full adder cells can be completely tested under single faulty-cell assumption, by a minimum test set of size 8 independent of the number of cells in the ripple carry adder. The fault model assumed is that faults in a cell can change the cell behavior in any arbitrary way, as long as the cell remains a combinational circuit. This assumption is valid for most faults. However, some faulty combinational circuits do have sequential behavior, for example, CMOS circuits with stuck-open faults and certain bridging faults. In this paper, we assume a more general fault model in which a fault in a cell can change the original one-state combinational cell to two-state sequential faulty cell. A shortest test sequence of length 57 which can detect arbitrary length ripple carry adders under this fault-model is presented. REFERENCES [1] W. H. Kautz "Testing for faults in cellular logic arrays" Proc. 8th Annu. Symp. Switching and Automata Theory, pp. 161-174, 1967. [2] A. D. Friedman "Easily testable iterative systems" IEEE Trans. Comput., Vol. C-22, pp. 1061-1064, Dec. 1973. [3] T. Sridhar and J. P. Hayes "Testing bit-sliced microprocessor" Dig. 9th Symp. Fault-Tolerant Comput., Madison, WI, pp. 211-218, June 1979. [4] R. Parthasarathy and S. M. Reddy "A testable design of iterative logic array" IEEE Trans. Comput., Vol. C-30, pp. 833-841, Nov. 1981. [5] R. L. Wadsack "Fault modeling and logic simulation of CMOS and NMOS integrated circuits" Bell System Tech. Journal, Vol. 57, no. 2, pp. 1449-1474, May-June 1978. [6] F. C. Hennie. Finite-State Models for Logical Machines. New York: John Wiley & Sons, Inc., 1968. [7] S. M. Reddy, M. K. Reddy, and J. G. Kuhl "On testable design for CMOS logic circuits" International Test Conference, Philadelphia, pp. 536-546, Oct. 1983.


C-Testability of Two-Dimensional Arrays of Combinational Cells Hasan Elhuni Dept. of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455

Anastasios Vergis Dept. of Computer Science, University of Minnesota, Minneapolis, MN 55455

Larry Kinney Dept. of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455

Abstract C-testable design of orthogonally connected two-dimensional arrays of combinational cells is considered under the single faulty cell model (SFCM). The design facilitates testing such arrays with a constant number of tests independent of the size of the array (C-testability). Sufficient conditions for C-testability are given. Methods to modify the basic flow table to facilitate C-testability are presented. A constant upper bound independent of the size of the array is given. REFERENCES [Elhu] H. Elhuni "Testing of Computer Systems" Ph.D. Thesis, in preparation. [Fr] A. D. Friedman "Easily Testable Iterative Systems" IEEE Trans. Comput., Vol. C-22, pp. 1061-1064, 1973. [FrMe] A. D. Friedman and P. R. Menon. Fault Detection in Digital Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1971. [Ka] W. H. Kautz "Testing for Faults in Cellular Logic Arrays" in Proc. 8th Ann. Symp. Switching Autom. Theory, 1967, pp. 161-174. [PaRe] R. Parthasarathy and S. M. Reddy "A Testable Design for Iterative Logic Arrays" IEEE Trans. Comput., Vol. C-30, pp. 833-841, 1981.


A Statistical Model for MOSFETS S. Liu AT&T Bell Laboratories, Murray Hill, New Jersey 07974

K. Singhal Dept. of System Design, University of Waterloo, Waterloo, Ontario N2L3G1, Canada

Abstract A compact statistical model for MOSFETs has been developed to simulate the statistical variations in the device characteristics resulting from parameter variations in the process. Seven critical process parameters are identified by applying statistical analyses to large samples of measured data. To represent the statistical variation in the process parameters a noise model is used. The observation residuals are modeled as normally distributed independent random variables. The deterministic part of the model parameters are related to the critical process parameters through a combination of expressions for long-channel devices, based on one-dimensional physical analysis, multi-parameter linear regression and single-parameter non-linear regression. The statistical variation in device performance predicted by this model agrees closely with actual measurements. References [1] M. E. Potter "Test Chip Strategy for High Volume VLSI Design Laboratories" IEEE VLSI Workshop on Test Structures, San Diego, CA, February 20, 1984, pp. 127. [2] P. Cox, P. Yang, S. S. Mahant-Shetti and P. Chatterjee "Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits" IEEE J. Solid-State Circuits, Vol. SC-20, No. 1, February, 1985, pp. 391-398. [3] SAS User's Guide, Basics and Statistics. SAS, 1982. [4] D. A. Divekar, R. W. Dutton and W. J. McCalla "Experimental Study of Gummel-Poon Model Parameter Correlation for Bipolar Junction Transistors" IEEE J. Solid-State Circuits, Vol. SC-12, No. 5, October 1977, pp. 552-559. [5] A. Sobczak "MOS IC Device Statistics - An Experimental Study" the 1981 European Conference on Circuit Theory and Design, The Hague, The Netherlands, August 25-28, 1981. [6] S. Liu and L. W. Nagel "Small-Signal MOSFET Models for Analog Circuit Design" IEEE J. SolidState Circuits, Vol. SC-17, No. 6, December 1982, pp. 983-998. [7] J. L. D'Arcy and R. C. Rennick "MOSFET Parameter Optimization for Accurate Output Conductance Modeling" CICC, Portland, OR, May 20-22, 1985. [8] C. Daniel and F. S. Wood. Fitting Equations to Data. John-Wiley & Sons, 1980. [9] Richard A. Becker and J. M. Chambers, S An Interactive Environment for Data Analysis and Graphics, the Wadsworth Statistics/Probability Series, Wadsworth Advanced Book Program, 1984.

[10] S. Freeman "Statistical Techniques for Calibrating Simulation Models of Analog Circuits and Devices" ISCAS 1984, pp. 684-688. [11] E. J. Prendergast and P. Lloyd "A Highly Automated Integrated Modeling System: MECCA" CICC, Portland, OR, May 20-22, 1985.


Statistical Modeling for Circuit Simulation of CMOS VLSI Norm Herr, John J. Barnes Motorola, Inc. Memory Products Group, 3501 Ed Bluestein Blvd., Austin, Texas 78721

ABSTRACT A methodology for characterizing the measured distribution of MOS transistor performance is described. A joint probability density function of device model parameters is generated including parameter correlation. The dependent parameter distribution is transformed by an independence producing transformation. Equidensity contours which contain the desired probability are used as design windows. An optimization algorithm selects unique parameter sets which lie within the equidensity contour based on desired circuit performance. REFERENCES [1] E. Lloyd. Handbook of Applicable Mathematics, Vol II: Probability. pp. 272-288, John Wiley & Sons, New York, 1980. [2] W. Maly and S. W. Director "Characterization of Random Behavior of the IC Manufacturing Process" European Conference on Electronic Design Automation, University of Sussex, 1 - 4 Sept., 1981. [3] Steven F. Arnold. The Theory of Linear Models and Multivariate Analysis. John Wiley & Sons, 1981. [4] J. H. Wilkinson. The Algebraic Eigenvalue Problem. Clarendon Press, Oxford, 1965.


A Meyer-Like Model for the M.O.S.T., Satisfying Gate Charge Conservation P. Prioretti, C. Turchetti, G. Masetti Dept. of Electronics, University of Ancona, Italy

E. Profumo, M. Vanzi SGS, Central R&D, Agrate B., Milano-Italy

ABSTRACT It is well known that the Meyer's model implemented in SPICE does not guarantee charge conservation, while the Ward's model seems a little bit complex to be used as a standard for the transient analysis of all the MOS circuits. In this work a new simple model for the gate charge of MOST to be used during transient analysis is presented. The model was developed by performing as a first step the numerical integration of the gate current without introducing the concept of a mean constant capacitance. The new model has been implemented in the program SGS-SPICE. All benchmark tests indicate that it conserves gate charge. REFERENCES [1] J.E.Meyer RCA Review, 32, p.42, 1971. [2] D.Ward,Rep. G201-11,Stanford Univ., 1981. [3] P.Yang et al IEEE JSCC,SC18, p. 128, 1983. [4] B.Sheu et al UCB/ERL M84/20, Berkeley. [5] C. Turchetti et al Solid-State Electron., 26, p. 941, 1983. [6] M.Bagheri et al IEDM, S.Francisco, 1984.


A Silicon Compiler System Based on Asynchronous Architecture Masaharu Hirayama Central Research Lab., Mitsubishi Electric Corp., 8-1-1 Tsukaguchi Honmachi, Amagasaki, Japan

Abstract In this paper a silicon compiler system based on an asynchronous architecture model is described. The behavior of the generated VLSI chip which consists of some asynchronous modules is controlled only by the local communication among these modules. By the fixation of the architecture model in the silicon compiler system, it is possible to realize the silicon compiler by a library of the asynchronous modules, which are generally defined with suitable parameters, and by the simple translation programs which analyze the functional description of the chip and extract the components and the control information from it. References [1] J.Werner "The Silicon Compiler: Panacea, Wishful Thinking, or Old Hat ?" VLSI Design Vol.3, No.5, 1982. [2] M.R.Barbacci, et al. "The ISPS Computer Description Language" Carnegie-Mellon Univ. Technical Report CMU-CS-79-137, 1977. [3] R.W.Hon and C.H.Sequin "A Guide to LSI Implementation" XEROX, Palo Alto Research Center, SSL79-7, 1980. [4] J.Batali and A.Hartheimer "The Design Procedure Language Manual" MIT A.I. Memo. No. 598, 1980. [5] C.G.Bell, et al. "Computer Engineering" Digital Press, Mass., 1979.


A Bit-Serial Silicon Compiler Jeffrey R. Jasica, Sharbel Noujaim, Richard Hartley, Michael J. Hartman General Electric Corporate Research and Development Center, P.O. Box 8, Schenectady, New York 12301

ABSTRACT This paper describes a silicon compiler for a bit-serial architecture. A high-level language is defined for the user interface. This language is used by a behavioral emulator and a compiler. The compiler translates high-level algorithmic circuit descriptions into an intermediate format containing instances of and interconnections among the cells defined in a cell library. The intermediate format provides an interface to a functional level emulator and a floorplanning and routing system. A library of 1.25 micron CMOS bitserial cells has been designed. The final output of the system is currently in CIF but will eventually be in EDIF. REFERENCES [1] Lyon, Richard F. "A Bit-Serial VLSI Architectural Methodology for Signal Processing" VLSI '81, Academic Press, 1981. [2] Denyer, Peter B. "An Introduction to Bit-Serial Architectures for VLSI Signal Processing" VLSI Architecture, Prentice Hall, 1982. [3] Bergmann, Neil "A Case Study of the FIRST Silicon Compiler" Third Caltech Conference on VLSI, 1983. [4] Kang, Sungho "Linear Ordering and Application to Placement" 20th DA Conference, pp. 457-464, 1983. [5] Reingold, Edward M. and Kenneth J. Supowit "A Hierarchy-Driven Amalgamation of Standard and Macro Cells" IEEE Transactions on CAD, Vol. 3, No. 1, January 1984, pp. 3-11. [6] Murray, Alan F. and Peter B Denyer "A CMOS Design Strategy for Bit-Serial Signal Processing" IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 3, June 1985, pp. 746-753.


Towards Designing, Testing, and Validating High Performance VLSI Signal Processors Robert M. Owens, Mary Jane Irwin Department of Computer Science, Penn State University, Univ. Park, PA

Introduction This paper overviews a high-level interactive system that allows a user, with only a rudimentary knowledge of VLSI, to generate a design at the layout level for performing various signal processing operations. The design process is completely automated and does not require the user to supply his own algorithms or their corresponding architectures. At the same time, the system is flexible enough to allow the user to compare several different possible design alternatives and to tailor his design according to his needs… Our architecture scheme is based on a set of algorithms [AgC] [Goo] [Wi] that need relatively few arithmetic operations and that have a general structure that lends itself well to highly parallel, pipelined designs. The speed-up obtained can be mathematically shown to be optimal [JaO]. For instance, preliminary simulation results lead us to believe that a discrete Fourier transform (DFT) processor can be constructed, on a very few VLSI chips, which is capable of performing about 64,000 pipelined 1024 point DFT's per second. Our basic cells are digit-on-line [IrO] digit serial adders, subtractors, multipliers, and delay elements that have been specifically designed for our system. These cells are quite compact with a very small gate delay. Since they are digit serial devices, they also have limited connection requirements but without an accompanying loss in speed because of their ability to pipeline at the digit level. These basic cells are connected to one another in a nearest neighbor fashion in our derived structures. The process of putting the cells together is completely automated and can be done by specifying the architecture type and the size. Our system produces designs which require no significant routing or placement and almost no control. References [AgC] Agarwal, R. and J. Cooley "New Algorithms for Digital Convolution" IEEE Trans. Acoust., Speech and Signal Proc., 25, pp. 392-410, 1977. [Goo] Good, I. "The Interaction Algorithm and Practical Fourier Analysis" J. Royal Stat. Soc., Ser. B, Vol. 20, pp. 361-372, 1958, Vol. 22, pp. 372-375, 1960. [IrO] Irwin, M. and R. Owens "Fully Digit Online Networks" IEEE Trans. on Computers, Vol. C-32, No. 4, pp. 402-406, April 1983. [JaO] Ja'Ja', J. and R. M. Owens "VLSI Architectures Based on the Small n Algorithms" Electrical Engineering, University of Maryland, 1984.

[OwI] Owens, R. and M. Irwin "Towards Designing, Testing and Validating High Performance VLSI SignalProcessors" CS-85-10, Computer Science, Penn State University, 1985. [Wi] Winograd, S. "On Computing the Discrete Fourier Transform" Math. Comp. 32, pp. 175-195, 1978.


The MEGA System: An Automated Methodology for Semi-Custom VLSI Chip Design U. G. Baitinger ITIV, POB 6380 D-7500 Karlsruhe West Germany

D. A. Mlynski ITM, POB 6380 D-7500 Karlsruhe West Germany

S. Dao Trong IBM, POB 800880 D-7000 Stuttgart 80 West Germany

ABSTRACT MEGA, the Modular Engineering System for Gate Arrays, is a decentralized low-cost stand-alone CAD system, which makes the gate array design experience available even to the unexperienced user. The comfortable graphic user interface starts at a highlevel flow chart type functional description of finite state machines. Novel algorithms generate automatically both the gate level logic circuits as well as the physical layout by directly taking into account typical gate array characteristics, such as limited fan-in/fan-out, geometrically pre-placed basic cells, and complex CMOS gates. REFERENCES [1] S. DAO TRONG "A Design Process for Multi-Stage Switching Circuits Under Gate Array Constraints" Ph.D. Thesis, ITIV, University of Karlsruhe (1984). [2] G.J. WIPFLER "A Placement Process for the Bottom-Up Design of VLSI Circuits" Ph.D. Thesis, ITM, University of Karlsruhe (1985). [3] G.J. WIPFLER, M. WIESEL, D.A. MLYNSKI "A Combined Force and Cut Algorithm for Hierarchical VLSI Layout" Proc. 19th Design Automation Conf., pp. 671-677 (1982). [4] H.J. ROTHERMEL "Routing Algorithms for VLSI Circuits" Ph.D. Thesis, ITM, University of Karlsruhe (1984).

ICCAD85 – 4B.1, Pages 102-104

Minimizing Extra Hardware for Fully Testable PLA Design Javad Khakbaz MOS Design, Semiconductor Devision, Data General Corporation, Sunnyvale, Ca 94086-4299

Saied Bozorgui-Nesbat Center for Reliable Computing, Computer Systems Laboratory, Stanford University, Stanford, Ca 94305

ABSTRACT This work presents an algorithm for finding a minimal amount of added logic to make programmable logic arrays (PLAs) fully testable. The design-for-testability method is based on the work presented in [BozorguiNesbat84]. However, the algorithm presented here is shown to drastically reduce the amount of additional logic required to make the PLA testable for all single and multiple stuck-at faults, crosspoint transistor faults, and many interesting bridging faults. The algorithm has been coded in PL/1. The superior performance of the algorithm is demonstrated by running this implementation on several PLAs that are designed for Data General Products. The results of these runs are also presented here. REFERENCES [BozorguiNesbat84] Bozorgui-Nesbat, S. & E.J. McCluskey "Lower Overhead Design for Testability for Programmable Logic Arrays" Proceedings, 1984 International Test Conference, pp. 856-865, November 1984. [Brayton, 84] Brayton, R.K., J.D. Hachtel, G.D. McMullen and A.L. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Hingham, MA, 1984. [Hechtel, 82] Hachtel, G.D. "Techniques for Programmable Logic Array Folding" Proceedings, 19th Design Automation Conference, pp. 147-155, Las Vegas, Nevada, June 1982. [Hong, 79] Hong, S.J. and D.L. Ostapko "Fault Analysis and Test Generation for Programmable Logic Arrays" IEEE Transactions on Computers, pp. 617-626, September 1979. [Hong, 80] Hong, and D.L. Ostapko "FITPLA: A Programmable Logic Array for Function-Independent testing" Digest, FTCS-10, pp. 131-136, October 1980. [Shen, 85] Shen, J.P., W. Maly, and F.J. Ferguson. Inductive Fault Analysis of MOS Integrated Circuits. Department of Electrical & Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213, April 1985. [Smith, 79] Smith, J.E. "Detection of Faults in Programmable Logic Arrays" IEEE Transactions on Computers, pp. 845-853, November 1979.

ICCAD85 – 4B.2, Pages 105-107

A New Approach to Design for Testability in an LSI Logic Synthesis System T. Masui, F. Niimi, M. Iwase Integrated Switching Development Division, NEC Corporation, Chiba, Japan

ABSTRACT In this paper, we deal with Design for Testability (DFT), mainly scan path approach, in the logic synthesis environment. This system automatically transforms logical description, which has little consideration for DFT, into the gate level circuit description with scan path. The transformation is carried out considering the target VLSI technology. It is the purpose of this paper to show how this system helps a logic designer more easily and efficiently generate a practical gate level circuit description with scan path. References [1] S. Funatsu, N. Wakatsuki, and T. Arima "Test Generation System in Japan" Proc. 12th Design Automation Conf., June 1975, pp. 114-122 [2] E. B. Eichelberger, and T.W. Williams "A Logic Design Structure for LSI Testing" Proc. 14th Design Automation Conf., June 1977, pp. 462-468 [3] I. Matsumoto, F. Niimi, M. Iwase, T.Sugimoto, K.Takahashi “Hierarchical Logic Synthesis System for VLSI" Proc. ISCAS '85, June 1985, pp. 651-654 [4] T. W. Williams "Design For Testability" in Computer Design Aids For VLSI Circuit, Sijthoff & Noodfoff, 1981, pp. 359-416

ICCAD85 – 4B.3, Pages 108-110

An Integrated Design for Testability System Francis C. Wang, Ghulam Nurie, Mike Brashler CAE Systems Division Tektronix, Inc., P.O. Box 4600, D/S 92-826 Beaverton, Oregon 97075

SUMMARY An Integrated Design for Testability (DFT) system is being developed by Tektronix as part of its computer-aided design product offering. The objectives of this system are as follows: * To develop an efficient testability-oriented CAD system to ease verification and testing for digital systems * To provide testability tools to solve end-to-end problems from design to test in EE * To implement major tools in the testability CAD products: the Testability-Measure Analyzer (TMA), the Test-Generation System (TGS), the Statistical Fault Analyzer (SFA), and various linkages to testers and debugging systems. With these objectives in mind, these DFT tools are being developed to aid circuit-design engineers address testing and verification problems early in the design cycle. Only if considered early in the design cycle and by using a systematic approach, can these problems associated with complex integrated circuits be solved. The DFT tools are being developed as an integrated system in terms of these factors: * From the user's point of view, commands used for the tools have the same syntax. * The output and responses from one tool are automatically used by a downstream tool. * The system is closely tied into the database for CAE 2000. * All tools share a common intermediate waveform format. REFERENCES [1] S.B. Akers and B. Krishnamurthy "A Test Counting Technique to Estimate Test Size" 5th Annual IEEE Workshop on Design for Testability, Vail, Colorado, April 1982. [2] Shelion Akers and Balaji Krishnamurthy "On the Application of Test Counting to VLSI Testing" 1985 Chapel Hill Conference on VLSI. [3] F.C. Wang "Testability Analysis: What Role Should It Play in IC Design?" Proc. 1984 Int'l. Test Conference, Oct. 1984. [4] F.C. Wang and A.C. Hung "A Method for Test Generation Directly from Testability Analysis" Proc. 1985 Int'l. Test Conference, November, 1985. [5] S.D. Jain and V.D. Agrawal "STAFAN: An Alternative to Fault Simulation" in Proc. 21st Design Automation Conference, June 1984.

[6] Robert S. Broughton and Michael G. Brashler "The Future Is Now: Extending CAE Into Test of Custom VLSI" Proc. 1984 Int'l. Test Conference, October 1984. [7] R. Zara, K. Rose, G. Nurie, and H. Sarin "An Abstract Machine Data Structure For Non-Procedural Functional Models" in Proc. 22nd Design Automation Conference, June 1985. [8] D. Holt and S. Sapiro "Interactive Logic Simulation in Distributed Engineering Workstation Environment" ICCS, 1983.

ICCAD85 – 4B.4, Pages 111-113

On the Masking Probability with One's Count and Transition Count Jacob Savir, William H. McAnney Data Systems Division, 265/926 International Business Machines Corporation, P.O. Box 950, Poughkeepsie, NY 12602

ABSTRACT This paper addresses the masking probability of two data compression techniques: one's count and transition count. It is shown that if the inputs are randomly applied, the masking probability of a fault asymptotically approaches (πN) -1/2, where N is the length of the input sequence. This indicates that for long input sequences the masking effect can be ignored. For the three most common data compression techniques, namely, signature analysis, one's count, and transition count, the masking probability is practically negligible, if the test length is already of modest size. Random pattern testable design for self-test should concentrate on assuring that all faults are detected at the primary outputs, and pay no attention to which of the three compression techniques is actually used, provided the test length is sufficiently long. Index terms: One's count, transition count, signature analysis, masking probability. REFERENCES [1] Z. Barzilai, J. Savir, G. Markowsky, and M.G. Smith "The weighted syndrome sums approach to VLSI testing" IEEE Trans. Comput., pp. 996-1000, Dec. 1981. [2] R.A. Frohwerk "Signature analysis: a new digital field service method" Hewlett-Packard Journal, May 1977. [3] B. Konemann, J. Mucha, and G. Zwiehoff "Built-in logic block observation techniques" Proc. 1979 International Test Conference, pp. 37-41, Oct. 1979. [4] J.L. Carter "The theory of signature testing for VLSI" Proc. 14th ACM Symp. Theory of Computing, May 1982, pp.66-76. [5] P.H. Bardell and W.H. McAnney "Self-testing of multichip logic modules" Proc. 1982 International Test Conference, pp. 200-204, Nov. 1982. [6] M.T.M. Segers "A self-test method for digital circuits" Proc. 1981 International Test Conference, Oct. 1981, pp. 79-85. [7] J. Savir, G.S. Ditlow, and P.H. Bardell "Random pattern testability" IEEE Trans. Comput., Vol. C-33, pp.79-90, Jan. 1984. [8] J. Savir and P.H. Bardell "On random pattern test length" IEEE Trans. Comput., Vol. C-33, pp. 467474, June 1984.

ICCAD85 – 4C.1, Pages 116-118

A Multiprocessor Implementation of a Logic-level Timing Simulator Jeffrey M. Arnold, Christopher J. Terman M.I.T. Laboratory for Computer Science, 545 Technology Square, Cambridge, MA 02139

Abstract This paper describes PRSIM, a multiprocessor algorithm for logic-level timing simulation which achieves a high degree of parallelism while making only modest demands on the interprocessor communication network. The circuit to be simulated is partitioned among the available processors; the partitions are chosen to balance the simulation load and minimize the amount of required interprocessor communication. Associated with each circuit partition is a history buffer which encodes the values of the partition's inputs for all time. Simulation of each partition proceeds independently, based on the assumption that the current contents of the history buffer are correct. When this assumption is proven wrong--i.e., a shared node changes value--messages are sent to the appropriate partitions. The receiving partitions use this information to update their history buffers and correct their simulations if necessary. A sequence of checkpoints is maintained by each partition which allows the simulation to be "rolled back" in time whenever necessary to reflect a change in the input history. References [1] T. L. Anderson. The Design of a Multiprocessor Development System. MIT Laboratory for Computer Science Technical Report TR-279, 1982. [2] J. M. Arnold. Parallel Simulation of Digital LSI Circuits. MIT Laboratory for Computer Science Technical Report TR-333, February 1985. [3] R. E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Transactions on Computers, Vol. C-33, No. 2, February 1984. [4] J. T. Deutsch and A. R. Newton "A Multiprocessor Implementation of Relaxation Based Electrical Circuit Simulation" Proceedings of the 21st Design Automation Conference, 1984. [5] R. H. Halstead, et al. "Concert: The Design of a Multiprocessor Development System" in preparation. [6] B. Randell "System Structure for Software Fault Tolerance" IEEE Transactions on Software Engineering, Vol. SE-1, No. 2, June, 1975. [7] D. L. Russell "State Restoration in Systems of Communicating Processes" IEEE Transactions on Software Engineering, Vol. SE-6, No. 2, March, 1980. [8] C. J. Terman "RSIM--A Logic-level Timing Simulator" Proceedings of ICCD 83, October 1983.

ICCAD85 – 4C.2, Pages 119-121

High-Speed Logic Simulation on a Vector Processor Nagisa Ishiura, Hiroto Yasuura, Tetsuro Kawata, Shuzo Yajima Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, Japan

Introduction Logic simulation is one of the most important tools in CAD for large scale logic design. Various software simulation techniques [1] [2] and hardware simulation engines [3] have been devised to reduce time spent for simulation. In this paper, we propose a new approach to accelerate simulation speed using vector processors. Vector processors are super computers with a pipeline architecture. Several types of vector processors have been developed in the past 5 years, which execute several hundred MFLOPS (Million FLoating-point Operations Per Second). Some of them not only have floating-point operations for numerical computation but also include logical and fixedpoint operations as well. This generally gives them a great potential for high-speed computation in the area of non-numerical computation, such as logic simulation, as well as numerical computation. However few results have been reported on the application of vector processors to non-numerical computation. We have implemented high-speed logic simulators on vector processors and found that the simulation speed comparable to those of hardware simulation engines. We have developed new simulation algorithms suitable for the pipeline architecture and we show that a vector processor can be a powerful tool in CAD for large scale logic design just as the hardware simulation engines. References [1] Ernst Ulrich "A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression" Proc. 20th DAC., pp.709\~712, (1983). [2] N. Ishiura, H. Yasuura and S. Yajima "Time First Evaluation Algorithm for High-Speed Logic Simulation" Proc. ICCAD84, pp.197\~199, (1984). [3] Tom Blank "A Survey of Hardware Accelerators Used in Computer-Aided Design" IEEE Design & Test of Computers, Vol.1, No.3, pp.21\~39, (1984). [4] N. Ishiura, H. Yasuura, T. Kawata and S. Yajima "High-Speed Logic Simulation Using a Vector Processor" Proc. VLSI85, (1985). [5] M. T. M. Segers "Testability in a VLSI Environment" VLSI archtecture, pp.175\~195, Prentice Hall International Inc., NJ. U.S.A, (1983). [6] M. A. Breuer and A. D. Friedman "Diagnosis & Reliable Design of Digital Systems” Computer Science Press, (1976).

ICCAD85 – 4C.3, Pages 122-124

CEMU - A Concurrent Timing Simulator Bryan D. Ackland, Sudhir R. Ahuja, Teri L. Lindstrom, Deborah J. Romero AT&T Bell Laboratories, Holmdel NJ 07733

ABSTRACT This paper describes the implementation of a concurrent timing simulator on a messagebased multiprocessor. MOS circuits are modelled in terms of a macro data flow graph. Simulation takes place on a virtual data flow machine constructed using the MEGLOS operating system on the S/NET multiprocessor. Preliminary results indicate almost linear speedup as processors are added to the system. REFERENCES [1] Pfister G. F. The Yorktown Simulation Engine: Introduction. 19th Design Automation Conference, ACM, 1982, pp. 51-54. [2] Breuer M. A. and Friedman A. D. Diagnosis and Reliable Design of Digital Systems. Computer Science Press, 1976. [3] ZyCAD LE-001 and LE-002 Product Description, ZyCAD, 1982. [4] Dally W. J. The MOSSIM Simulation Engine Architecture and Design. Caltech Report \# 5123:TR:84, 1984. [5] Deutsch J. T. and Newton A. R. A Multiprocessor Implementation of Relaxation-Based Electrical Circuit Simulation, 21st Design Automation Conference, 1984, pp. 350-357. [6] Ackland, B. and Weste, N. Functional Verification in an Interactive Symbolic IC Design Environment, Proc. of 2nd Caltech Conference on VLSI, Jan 1981, pp. 285-298. [7] Weste, N. Virtual Grid Symbolic Layout, Proc. 18th. Design Automation Conference, Nashville TN, June 1981, pp. 225-233. [8] Ahuja, S.R. S/NET: A High Speed Interconnect for Multiple Computers, IEEE Journal on Selected Areas in Communications, November 1983, pp. 751-756. [9] Chawla, B. R., Gummel, H. K. and Kozak, P. MOTIS - An MOS Timing Simulator, IEEE Trans. on Circuits and Systems, Vol. 22 No. 12, Dec. 1975, pp. 901-910. [10] Chen, C.F. and Subramaniam, P. The Second Generation MOTIS Timing Simulator - An Efficient and Accurate approach for General MOS Circuits, Proc. 1984 International Symposium on Circuits and Systems, Montreal Canada, May 1984. [11] Bryant, R.E. An Algorithm for MOS Logic Simulation, Lambda, Vol. 1, No. 3, 1980, pp. 46-53. [12] Gaglianello, R. D. and Katseff, H. P. Meglos: An Operating System for a Multiprocessor Environment, 5th International Conference on Distributed Computing Systems, Washington DC., May 1985, pp. 35-42.

ICCAD85

Panel Session 1: Intelligent CAD Software: Current Status, Future Prospects Moderator: A.C. Parker, University of Southern California Panelists: C. Tong, Rutgers University S.W. Director, Carnegie-Mellon University S. Rubin, Schlumberger Computer Aided Systems Laboratory B. Krishnamurthy, Tektronix S. Goto, NEC This panel addresses the question of program intelligence, particularly with respect to computer-aided design applications. The panelists will examine what constitutes an intelligent program, what it means for a program to learn and to reason, and what level of intelligence is possible in today's software. The future possibilities for intelligent CAD applications will also be discussed.

ICCAD85

Panel Session 2: Is There Life in Spice? Moderator: L.W. Nagel, AT&T Bell Laboratories Panelists: R.I. Dowell, Hewlett-Packard S. Hamm, Analog Devices A.R. Newton, University of California, Berkeley R.A. Rohrer, Carnegie-Mellon University A.E. Ruehli, IBM P. Yang, Texas Instruments The first version of SPICE was released by the University of California, Berkeley, in 1971. Since that time, thousands of copies have been issued to universities and companies around the world. Moreover, numerous adaptations and embellishments of the SPICE program have been developed and are being marketed. This suggests widespread use and manifold applications for the program. This panel will address how SPICE has fared in its 14 plus years of existence. Specifically, the following topics will be discussed: * For which applications is SPICE well suited? * For which applications is SPICE ill suited? * How does SPICE compare to other circuit simulators? * What research areas in the field of circuit simulation should universities and research institutions be addressing? * SPICE has attained a remarkable age for a computer program. Is it time for a replacement? If so, what capabilities that SPICE doesn't have should the replacement have?

ICCAD85 – 5A.1, Pages 130-132

Hardware Acceleration of Logic Simulation Using a Data Flow Architecture Gary Catlin, Bill Paseman Daisy Systems Corporation, 700 Middlefield Road, Mountain View, Ca., 94043

Current digital logic simulators running on engineering workstations lack capacity and speed. This paper discusses a hardware accelerator for a workstation simulator which addresses these problems. The accelerator runs 100x faster than its software counterpart and can simulate up to 1 million gates. The accelerator has been built and is being sold commercially. The architecture of the accelerator is similar to that of a classical dataflow machine. We describe the architecture of the machine and illustrate how it would simulate a simple circuit. We then briefly discuss the relationship between event driven simulation and dataflow. References [Krohn81] Krohn, Howard E. "Vector Coding Techniques for High Speed Digital Simulation." Proceedings of the 18th Design Automation Conference, June 1981. [Pfister82] Pfister Gregory F. "The Yorktown Simulation Engine: Introduction." Proceedings of the 19th Design Automation Conference, June 1982. [Abramovici83] Abramovici et al. "A Logic Simulation Machine." IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. CAD-2, No.2, April 1983. [Sasaki83] Sasaki et al. "Hal; A Block Level Hardware Logic Simulator" Proceedings of the 20st Design Automation Conference, June 1983. [Glazier84] Glazier et al. "Ultimate: A Hardware Logic Simulation Engine." Proceedings of the 21st Design Automation Conference, June 1984. [Paseman84] Paseman W.G. "Processing Data Flow Graphs on an Event Driven Simulator." Daisy Systems Corporation, February 1984. [Treleaven82] Treleaven P.C. et al. "Data Driven and Demand Driven Computer Architecture" Computing Surveys, Vol.14. No.1, March 1982. p114

ICCAD85 – 5A.2, Pages 133-135

Systolic Architecture for the Logic Design Machine Marek A. Perkowski Department of Electrical Engineering, Portland State University, P.O. Box 751, Portland, Oregon 97207

ABSTRACT We propose a new type of hardware accelerator for the next generation of CAE workstations, which will be used to solve efficiently the combinatorial problems of logical and topological design of VLSI circuits. We describe one of the co-processors of this computer - a systolic architecture for solving constraints problems. Application of this architecture to the satisfiability and graph coloring problems is presented. Two variants of the architecture are proposed. One of them uses special VLSI chip, while the other is based on the recently introduced general purpose systolic chip NCR45CG72 GAPP.

ICCAD85 – 5A.3, Pages 136-138

Parallel Routing on a Hardware Array Router Alexander Iosupovici SDSU, San Diego, CA 92182-0190

Ali Vahidsafa Amdahl Corp., Sunnyvale, CA 94088

Abstract We present a number of new procedures for the simultaneous routing of k nets, which are well tailored for parallel processing. A special purpose array processor the PRIAP, has been developed for effective implementation of these routing procedures. The time complexity of those procedures when implemented on the PRIAP is presented. References [1] T. Blank "A Survey of Hardware Accelerators Used in Computer-Aided Design" IEEE Design and Test of Computers, Vol. 1, No. 3, pp. 21-39, August 1984. [2] A. Iosupovici et al "A Hardware Interchange Placement Machine" Proc. 20th ACM/IEEE Design Automation Conference, pp. 171-174, June 1983. [3] A. Iosupovici "Design of an Iterative Array Maze Router" Proc. IEEE Int'l Conf. Circuits and Computers, pp. 908-911, October 1980. [4] M.A. Breuer et al "A Hardware Router" J. Digital Systems, Vol. 4, No. 4, pp 393-408, 1981. [5] C.Y. Lee "An Algorithm for Path Connections and Its Applications" IRE Transactions on Electronic Computers, Vol EC-10, pp. 346-365, 1961. [6] W.A. Dees et al "Automated Rip-Up and Reroute Techniques" Proc. 19th ACM/IEEE Design Automation Conference, pp. 432-439, June 1982. [7] D.S. Johnson "The NP-Completeness Column: An Ongoing Guide" J. of Algorithms, pp. 381-395, December 1982. 8] J. Soukup "Global Router" J. Digital Systems, Vol. 4, No. 1, pp. 58-69, 1980. [9] A. Vahidsafa "Global Hardware Router" M.S. Thesis, San Diego State University, San Diego, California, Spring, 1985.

ICCAD85 – 5B.1, Pages 140-142

Abstract Partitioning of Logic Networks for Custom Module Generation Steven T. Healey, William J. Kubitz Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801-2987

ABSTRACT This paper describes an improved module planner for decomposing random logic dependence graphs into abstract cells. The formation and the number of abstract cells produced as output from the planner are based on the graph structure, the module aspect ratio, and a module generator characterization file. With this approach the module planner is able to work in closer conjunction with the cell synthesizer in producing efficient geometric layouts. References [Breu77] M. A. Breuer "Min-Cut Placement" Journal of Design Automation and Fault-Tolerant Computing, Vol. 1, No. 4, October 1977, pp. 343-362. [Brew84] F. D. Brewer "HCL - A System For Hierarchical Layout" Department of Computer Science Report UIUCDCS-R-84-1194, 1984. [BuPe83] M. Burstein, R. Pelavin "Hierarchical Wire Routing" IEEE Transactions on Computer-Aided Design, Vol. CAD-2, No. 4, October 1983, pp. 223-234. [Corr79] L. I. Corrigan "A Placement Capability Based on Partitioning" Proceedings of the 16th Design Automation Conference, June 1979, pp. 406-413. [DuKe85] A. E. Dunlop, B. W. Kernighan "A Procedure for Placement of Standard-Cell VLSI Circuits" IEEE Transactions on Computer-Aided Design, Vol. CAD-4, No. 1, January 1985, pp. 92-98. [FiMa82] C. M. Fiduccia, R. M. Mattheyses "A Linear-Time Heuristic for Improving Network Partitions" Proceedings of the 19th Design Automation Conference, June 1982, pp. 175-181. [HeGa85] S. T. Healey, D. D. Gajski "Decomposition of Logic Networks Into Silicon" Proceedings of the 22nd Design Automation Conference, June 1985, pp. 162-168. [HsKu85] Y. C. Hsu, W. J. Kubitz "Automatic Placement Using Wavefront Compaction" Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers, October 1985. [KeLi70] B. W. Kernighan, S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" The Bell System Technical Journal, 49:2, pp. 291-307. [LoHC83] G. Louie, T. Ho, E. Cheng "The Micro VAX I Datapath Chip" VLSI Design, December 1983, pp. 14-21. [LuGa84] C. Lursinsap, D. Gajski "Cell Compilation with Constraints" Proceedings of the 21st Design Automation Conference, June 1984, pp. 103-108.

[MaBC83] T. G. Matheson, M. R. Buric, C. Christensen "Embedding Electrical and Geometric Constraints in Hierarchical Circuit-Layout Generators" Proceedings of the International Conference on ComputerAided Design, September 1983, pp. 3-5. [MeCo80] C. Mead, L. Conway "Introduction to VLSI Systems" Addison-Wesley Publishing Company, Massachusetts, 1980. [Schw76] D.G. Schweikert "A 2-dimensional Placement Algorithm for the Layout of Electrical Circuits" Proceedings of the 14th Design Automation Workshop, June 1976, pp. 408-415. [UeKH85] K. Ueda, H. Kitazawa, I. Harada "CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design"IEEE Transactions on Computer-Aided Design, Vol. CAD-4, No. 1, January 1985, pp. 12-22. [VeKi83] M. P. Vecchi, S. Kirkpatrick "Global Wiring by Simulated Annealing" IEEE Transactions on Computer-Aided Design, Vol. CAD-2, No. 4, October 1983, pp. 215-222. [YuKu85a] M. L. Yu, W. J. Kubitz "Linear-Time Heuristics For Cell Layout Synthesis Under Constraints" Proceedings of the International Conference on Computer-Aided Design, November 1985. [YuKu85b] M. L. Yu, W. J. Kubitz "A VLSI Cell Synthesizer With Structural Constraint Considerations" Proceedings of the International Conference on Computer-Aided Design, November 1985.

ICCAD85 – 5B.2, Pages 143-145

Mason: A Global Floor-Planning Tool David P. LaPotin, Stephen W. Director Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, Pennsylvania 15213

ABSTRACT A global floor-planning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based upon a combined min-cut and slicing paradigm, in an effort to ensure routability. The method allows modules to be specified as having a number of possible dimensions and orientations, and considers I/O pads as well as layout constraints. An in-place partitioning technique is discussed which provides a global improvement over previous min-cut and slicing based efforts. A computer program, Mason, is presented which efficiently implements the approach and provides an interactive environment for designers to perform floor-planning. References [1] C. M. Fiduccia and R. M. Mattheyses. A Linear-Time Heuristic for Improving Network Partitions. In Proceedings of 19th Design Automation Conference, pages 175-181. June, 1982. [2] W. R. Heller, G. Sorkin and K. Maling. The Planar Package Planner for System Designers. In Proceedings of the 19th Design Automation Conference, pages 253-260. June, 1982. [3] M. Hild and J. O. Piednoir. Efficient Placement Algorithms for VLSI. VLSI Design VI(4):46-50, April, 1985. [4] B. W. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning Graphs. Bell Systems Technical Journal 49:291-307, February, 1970. [5] U. Lauther. A Min-cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation. In Proceedings of 14th Design Automation Conference, pages 1-10. June, 1979. [6] R. H.J.M. Otten. Efficient Floorplan Optimization. In International Conference on Computers and Design, pages 499-501. October, 1983. [7] B. T. Preas. Placement and Routing Algorithms for Hierarchical Integrated Circuit Layout. PhD thesis, Stanford Electronics Laboratories, Department of Electrical Engineering, Stanford University, Stanford, CA, August, 1979. [8] K. J. Supowit and E. A. Slutz. Placement Algorithms for Custom VLSI. In Proceedings of 20th Design Automation Conference, pages 164-170. June, 1983. [9] A. A. Szepieniec and R. H.J.M. Otten. The Genealogical Approach to the Layout Problem. In Proceedings of the 17th Design Automation Conference, pages 535-542. June, 1980.

ICCAD85 – 5B.3, Pages 146-148

Custom CMOS Design Using Hierarchical Floor Planning and Symbolic Cell Layout M C Revett British Telecom Research Labs, Martlesham Heath, Ipswich, England

ABSTRACT A comprehensive CAD system, called ASTRA, has been developed for custom chip design. It is based on a design method that uses hierarchical floor plans and symbolic cell layouts to capture the design data, which is entered and edited via interactive graphical editors. From this design data the information required to check and simulate the design is extracted automatically, and the geometrical mask data used to fabricate the chip is generated automatically, using the spacing program for individual cells and the chip assembler for the complete chip. Connection between cells is mainly by abutment, with the chip assembler stretching cells where necessary to produce pitch and edge matching as defined in the floor plans. The CAD system is currently in use for the design of several custom CMOS chips. REFERENCES [1] M C Revett and P A Ivey "ASTRA - a CAD system to support a structured approach to design" Proc. Int. Conf. on VLSI, pp 413-422, Trondheim, Aug. 1983. [2] D J Myers and P A Ivey "STAR - A VLSI architecture for signal processing" Proc. Conf. on Advanced Research in VLSI, pp 179-183, MIT, Jan. 1984 [3] C Mead and L Conway. Introduction to VLSI Systems. Addison-Wesley, 1980. [4] N Weste "Virtual grid symbolic layout" Proc. 18th Design Automation Conf., pp 225-233, Nashville, June 1981.

ICCAD85 – 5C.1, Pages 150-152

Rule-Based Static Debugger and Simulation Compiler for VLSI Schematics A. Kolodny, R. Friedman, T. Ben-Tzur Intel Israel (74) Ltd., Haifa 31015, Israel

ABSTRACT A verification system, based on static analysis of MOS networks, is presented. The system consists of a static design-rule checker and a compiler for generating executable simulation models from schematics. The network analysis involves functional classification of transistors and nodes by their role in the circuit, and evaluation of timing-dependent information and other attributes. The static checker enables specification of design-methodology rules in the form of data-base queries. It uses pattern matching in conjunction with path analysis, delay modeling and other underlying algorithms, resulting in reports of schematic design-rule violations. The simulation compiler converts the analyzed network into an efficient source-code program, which simulates the hardware functionality. It uses switch-level combined with extracted logic expressions and macro-level models. REFERENCES [1] H. De Man et al. "A Debugging and Guided Simulation System for MOSVLSI Design" IEEE ICCAD83, pp.137-138, Santa Clara, 1983. [2] C. Lob, R. Spickelmier and A.R. Newton "Circuit Verification Using Rule-Based Expert Systems" IEEE Symposium on Circuits and Systems, 1985. [3] H. De Man, I. Bolsens and E. Vanden Meersch "An Expert System for Logical and Electrical Debugging of MOSVLSI Networks" IEEE ICCAD-84, pp.203-205, Santa Clara, 1984. [4] V.E. Kelly "The CRITTER System - Automated Critiquing of Digital Circuit Designs" Proc. 21th Design Automation Conf., pp.419-425, 1984. [5] C.F. Chen, C.Y. Lo, H.N. Nham and P. Subramanian "The Second Generation MOTIS Mixed-Mode Simulator" Proc. 21th Design Automation Conf., pp.10-17, 1984. [6] N. Jouppi "TV: An nMOS Timing Analyzer" Proc. 3rd Caltech VLSI Conf., pp.71-85, 1983. [7] C.Y. Lo, H.N. Nham and A.K. Bose "A Data Structure for MOS Circuits" Proc. 20th Design Automation Conf., pp.619-624, 1983. [8] A.R. Newton "Timing, Logic and Mixed-Mode Simulation for Large MOS Integrated Circuits" Computer Design Aids for VLSI Circuits, edited by Antognetti, D.O. Peterson and H. De Man, pp.175-239, Sijthoff & Noordhoff, 1981. [9] J.K. Ousterhout "Switch-Level Delay Models for Digital MOS VLSI" Proc. 21th Design Automated Conf., pp.542-548, 1984. [10] J. Katzenelson "VLSI Simulation and Data Abstraction" IEEE ICCAD-83, pp.67, Santa Clara, 1983.

[11] R. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Transactions on Computers, Vol. C-33, pp.160-177, 1984. [12] G.D. Hachtel and A. Sangiovanni-Vincentelli "A Survey of Third-Generation Simulation Techniques" Proc. IEEE, Vol. 69, pp.1264-1280, 1981. [13] J.K. Ousterhout "Crystal: A Timing Analyzer for nMOS VLSI Circuits" 3rd Caltech Conf. on VLSI, pp.57-69, 1983.

ICCAD85 – 5C.2, Pages 153-155

A Path Algebra for Switch-Level Simulation Ibrahim N. Hajj Coordinated Science Laboratory and The Department of Electrical and Computer, Engineering University of Illinois, Urbana, IL 61801

ABSTRACT This paper describes a path algebra for switch-level logic simulation of VLSI transistor circuits. The algebra is based on modeling the circuit as a weighted signal-flow graph. Using the graph representation, the equations describing the flow of the logical signals in the circuit are written in matrix form similar in structure to the nodal equations describing the original electrical model, except that ternary algebra is employed. The transistor strengths are incorporated into the matrix algebra, while the node strengths are taken into account by a node ordering scheme. Partitioning algorithms, Gaussian elimination and Gauss-Seidel solution techniques are then developed to perform logic simulation. The method can also be used to extract symbolic functional representations from the transistor level description. In addition, physical fault models can be easily incorporated into the matrix description to perform fault simulation. The approach has been applied to both MOS and bipolar digital circuits. REFERENCES [1] R. E. Bryant "A switch-level model and simulator for MOS digital systems" IEEE Trans. on Computers, vol. C-33, No. 2, February 1984, pp.160-177. [2] J. P. Hayes "A unified swiching theory with application to VLSI design" Proc. IEEE, vol. 70, No. 10, October 1982, pp. 1140-1151. [3] R. H. Byrd, G. D. Hachtel, M. R. Lightner and M. H. Heydemann "Switch-level simulation: Models, theory and algorithms" in Advances in Computer-Aided Engineering Design, vol. I, A. SingiovanniVincentelli, Editor, JAI press, Greenwich, CT, 1985. [4] I. N. Hajj and D. Saab "Fault modeling and logic simulation of MOS VLSI circuits based on logic expression extraction" IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 99-100, September 1983. [5] B. A. Carre. Graphs and Networks. Clarenon Press, Oxford, England, 1979. [6] I. N. Hajj "Sparsity considerations in network solution by tearing" IEEE Trans. on Circuits and Systems, vol. CAS-27, No. 5, pp. 357-366, May 1980.

ICCAD85 – 6A.1, Pages 158-160

Integration of a Hardware Simulator into an IC Design System William C. Diss, Randall Ott, Donald W. Nelson United Technologies Microelectronics Center, 1365 Garden of the Gods, Colorado Springs, CO 80907

Abstract This paper presents the results of a thorough integration of a hardware logic accelerator into an existing CAD system. This system is unique in that many of the users are scattered across the U.S., rather than at a single site. Issues of transparency between the hardware and a software simulator, efficient translators, and networking are addressed in this paper. Results comparing the throughput between the hardware and software simulations are presented. References [1] HIGHLAND is a servicemark of UTMC, ZYCAD is a trademark of the Zycad Corporation, TEGAS is a trademark of General Electric Calma, and DECSIM is a trademark of Digital Equipment Corporation. [2] Anderson, K.A., Powell R.E. "UTMC's LSI CAD System - HIGHLAND" Proc. 21st Design Automation Conference (1984, Albuquerque), pp. 580-586. [3] Roberts, K.A., et al. "Automatic Layout in the HIGHLAND System" Proc 1984 Int. Conf. CAD (Santa Clara), pp. 224-226. [4] Hess, R.D., et al. "Automated Test Program Generation for Semicustom Devices" VLSI Design, October (1983) pp. 51-61. [5] Rezac, R.R., Smith, L.T. "A Simulation Engine in the Design Environment" VLSI Design, November 1984, pp 96-102.

ICCAD85 – 6A.2, Pages 161-163

Circuit Partitioning for Hardware Simulation Engines Prathima Agrawal AT & T Bell Laboratories, Murray Hill, N. J. 07974

ABSTRACT This paper describes a partitioning scheme suitable for multiprocessor based hardware simulation machines implementing event driven simulation algorithms. It makes use of the circuit topology and the delay information available in simulation database. The optimization gained is not only in space as in conventional partitioning algorithms employed in physical design but also in time. This added dimension increases the processor utilization while minimizing the number of idle processors. Simple models are given for the concurrency achievable and the inter-partition communication during simulation. Experimental results using unit and multiple delay software simulators on real circuits are analyzed in the context of a multiprocessor environment. REFERENCES [1] T. Blank "A survey of Hardware Accelerators Used in Computer-Aided Design" IEEE Design and Test of Computers, Vol. 1, pp. 21-39, August 1984. [2] B. W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" Bell System Technical Journal, pp. 291-307, February 1970. [3] N. Van Brunt "The Zycad Logic Evaluator and Its Application to Modern System Design" Proceedings of the International Conference on Computer Design, Port Chester, NY, pp. 232-33, October 1983. [4] L. T. Smith and D. A. Gross "Preparing Large Networks for a Simulation Accelerator" Proceedings of the International symposium on Circuits and Systems, Kyoto, Japan, pp. 233-36, June 1985. [5] Y. H. Levendel, P. R. Menon, and S. H. Patel "Special Purpose Computer for Logic Simulation Using Distributed Processing" Bell System Technical Journal, Vol. 61, No. 10, pp. 2873-2909, December 1982. [6] V. D. Agrawal, A. K. Bose, P. Kozak, H. N. Nham, and E. Pacas-Skewes "Mixed-Mode Simulation in the MOTIS System" Journal of Digital Systems, Vol. V, No. 4, pp. 383-400, 1981.

ICCAD85 – 6B.1, Pages 166-168

PLA Compaction by Partition and Fusion Christos A. Papachristou Computer Engineering and Science Department Center for Automation and Intelligent System Research, Case Western Reserve University, Cleveland, Ohio 44106

A new technique of compaction of PLA data tables by partition and fusion is proposed. The partition exploits the data sparsity by splitting the PLA table along its columns. The fusion takes advantage of the data multiplicity by sharing common PLA fields. Significant PLA size reduction can be achieved. REFERENCES [1.] B. W. Fung, T. J. Macnee and G. Rungila "A High-Density PLA Macro and its Layout Generator" 1982 ISSCC, pp. 58-59, Feb. 1982. [2.] S. Powell, E. Iodice, E. Friedman "An Automated, High-Speed Complementary PLA Design System for VLSI Applications" ICCD-84, pp. 314-319, October 1984. [3.] R. K. Brayton, G. D. HAchtel, L. A. Hemachandra, A. R. Newton and A. L. M. SangiovanniVincentelli "A Comparison of Logic Minimization Strategies using EXPRESSO: an APL Program Package for Partitioned Logic Minimization” Proc. of IEEE Internat. Conf. on Circuits and Computers, Oct. 1982. [4.] G. Hachtel, A. Newton and A. Sangiovanni-Vincentelli "An Algorithm for Optimal PLA Folding" IEEE Trans. on CAD of IC's and Systems, Vol. CAD-1, No. 2, pp. 63-76, April 1982. [5.] J. R. Egan and C. L. Liu "Optimal Bipartite Folding of PLA" IEEE-ACM 19th Design Automation Conference, June 1982, pp. 141-145. [6.] V. Pulges and M. R. Lightner "A Recursive Bipartitioning Approach for PLA Partitioning and Layout" ICCD-84, pp. 320-323, October 1984. [7.] C. Papachristou and S. Gambhir "A Micro-sequencer Architecture With Firmware Support for Modular Microprogramming" Micro-15, 15th IEEE-ACM Microprogramming Workshop, pp. 105-113, October 1982.

ICCAD85 – 6B.2, Pages 169-171

An Intelligent Composition Tool for Regular and Semi-Regular VLSI Structures Hung-fai Stephen Law, John D. Mosby SDA Systems, 2461 Mission College Blvd. Santa Clara, California 95054

ABSTRACT A versatile tool that can be used to build module generators by designers is presented. An array-structure templates and a master cell library are the only components that a designer has to create to define a module generator. The array-structure template is both a block diagram ("floorplan") and a procedure for generating the module. All dimensional information is extracted from the library cells automatically. The composition tool can be used to build module generators even for modules consisting of multiple arrays and arrays of master cells of different heights and widths. In addition, a procedural mechanism is provided to allow the designer to modify and insert powerful optimization steps inside the module generators. Having graphical and procedural mechanisms in one tool, designers can easily create and modify module generators for structures such as RAMs, ROMs, PLAs, ALUs, shifters and array-multipliers without extensive programming. References [1] M.W. Stebnisky, M.J. McGinnis, J.C. Werbickas, R.N. Putatunda, and A. Feller "A Fully Automatic, Technology-independent PLA Macrocell Generator" Proc. of the IEEE International Conf. on Circuits and Computers, Sept. 1982, pp 156-161. [2] K-C. Chu and R. Sharma "A Technology Independent MOS Multiplier Generator" The 21st Design Automation Conf. Proceedings, Jun. 1984, pp 90-97. [3] H-F. S. Law and M. Shoji "PLA Design for the BELLMAC-32A Microprocessor" Proc. of the IEEE International Conf. on Circuits and Computers, Sept. 1982, pp 161-164. [4] C.S. Bamji, C.E. Hauck, and A. Jonathan "A Design by Example Regular Structure Generator" The 22nd Design Automation Conf. Proceedings, Jun. 1985, pp 16-22.

ICCAD85 – 6B.3, Pages 172-174

Sc2: A Hybrid Automatic Layout System Dwight D. Hill AT&T Bell Laboratories, Murray Hill, New Jersey 07974

ABSTRACT Sc2 (Silicon Converter version 2) is a system that accepts logic descriptions and automatically generates high-quality layouts. Its input consists of logic equations and/or logic diagrams, and its output consists of blocks of CMOS logic laid out in a style similar to "gate matrix." At the current time, the software has advanced to the point where Sc2 takes advantage of most of the more significant layout techniques, (e.g. cross-coupled devices, partially strapped transistors, via minimization, etc.) The tool has several advantages over standard cell systems. First, because it can deal with individually sized transistors, it can make use of circuit speedups provided by a timing evaluator optimizer such as TILOS[1]. Secondly, because it is not restricted to a fixed library of cells, any custom logic, including pass transistor logic and precharge circuits (e.g. domino logic), can be generated. This also eliminates the waste associated with "underutilized" standard cells. Third, because every aspect of the layout is adjustable, the smallest details can be tuned to meet the global needs. Sc2 is a hybrid system combining logic programming in PROLOG and conventional algorithms in C. The PROLOG section performs transformations from logic specifications to complementary, domino and zipper transistor connectivity sets. This transformation fit naturally into logic programming. The C language proved be more convenient than PROLOG for algorithms based on iterative improvements, such as placement and routing. Both sections make extensive use of heuristics that describe properties of CMOS circuit design. REFERENCES [1] Fishburn, J., and A. Dunlop "TILOS: A Posynomial Programming Approach to Transistors Sizing" ICCAD, 1985. [2] A.D. Lopez and H-F.S. Law "A Dense Gate Matrix Layout Method for MOS VLSI" IEEE Trans. on Elect. Devices, Vol. ED-27, Aug., 1980, pp. 1671-1675. [3] N. Weste "Virtual Grid Symbolic Layout" Proceedings of the 18th Design Automation Conference, Nashville, Tenn., 1981. [4] Hill, D. D. and S. Roy "PROLOG in CMOS Circuit Design" Spring COMPCON 85, San Francisco, CA. [5] Hill, D. D. "CAD Systems for VLSI Design" Proceedings of the National Electronics Conference, Chicago, Il., 1984, Vol. 38, pp. 673-676.

[8] S. C. Johnson "Hierarchical Design Validation Based on Rectangles" Proceedings of the Conference on Advanced Research on VLSI, MIT, January, 1982. [10.] Dunlop, A. E. and B. W. Kernighan "A Placement Procedure for Polycell VLSI Circuits" IEEE International Conference on Computer Aided Design, Santa Clara, CA. Sept 13-15 1983, pp. 51-52. [11] Johnson, S. Compiling Equations into Chips, private communications, Bell Laboratories, 1982.

ICCAD85 – 6C.1, Pages 176-178

STA: A Mixed-Level Timing Analyzer Bernard J. Murphy, James E. Kleckner, Ken K. Tam SDA Systems, 2461 Mission College Blvd. Santa Clara, California 95054.

Abstract A timing analyzer (STA) allowing mixed-level modeling of circuit or system designs is described. Timing may be estimated at the transistor level, using device and interconnect parasitics, or at the block level, where timing models may be defined by the user. The ability to mix levels of timing estimation extends the useful application of timing analysis to a wide range of design styles and to both early and late phases of the design cycle. Control and analysis in STA are programmable, enabling expression of the different test styles required for these applications. Performance measures for STA, applied to two designs, are included in this paper; these indicate that the program is both efficient and reasonably accurate. STA is integrated in a computer-aided design system. Input to the program may be taken from schematic or layout designs; critical path information is back-annotated to the design and may be viewed or used to guide other tools in the system. References [1] Robert B. Hitchcock Sr. "Timing Verification and the Timing Analysis Program" Proceedings of the 19th Design Automation Conference, 1982, pp. 594-604. [2] Lionel C. Bening and Thomas A. Lane "Developments in Logic Network Path Delay Analysis" Proceedings of the 19th Design Automation Conference, 1982, pp. 605-615. [3] Eiji Tamura, Kimihiro Ogawa and Toshio Nakano "Path Delay Analysis for Hierarchical Building Block Layout System" Proceedings of the 20th Design Automation Conference, 1983, pp. 403-410. [4] Norman P. Jouppi "Timing Analysis for nMOS VLSI" Proceedings of the 20th Design Automation Conference, 1983, pp. 411-418. [5] John K. Ousterhout "Crystal: A Timing Analyzer for nMOS VLSI Circuits" Proceedings of the third Caltech VLSI Conference, 1983. [6] Paul Penfield Jr and Jorge Rubenstein "Signal Delay in RC Tree Networks" Proceedings of the 18th Design Automation Conference, 1981, pp. 613-617. [7] John L. Wyatt Jr. and Qingjian Yu "Signal Delays in RC Meshes, Trees and Lines" Proceedings of the International Conference on Computer-Aided Design, 1984, pp. 15-17, and private communication. [8] John K. Ousterhout "Switch-Level Delay Models for Digital MOS VLSI" Proceedings of the 21st Design Automation Conference, 1984, pp. 542-548.

ICCAD85 – 6C.2, Pages 179-181

Polynomial Terminal Equivalent Circuits as Dormant Models in Event Driven Circuit Simulation Karem A. Sakallah Digital Equipment Corporation, HLO2-2/H13, 77 Reed Rd., Hudson, Ma. 01749

Abstract Event Driven Circuit Simulation (EDCS) [2] [3] is a new technique which is particularly suited to the simulation of large temporally sparse circuits. It is based on partitioning a large VLSI network into a set of loosely coupled subnetworks which are allowed to have different integration step sizes that reflect their "activity" levels. The time points when the equations of a given subnetwork are solved are identified as "events" at which the subnetwork is considered "alert". Between these events, the subnetwork is considered "dormant". A key element to the success of EDCS is the ability to accurately model the behavior of dormant subnetworks. This paper examines the original dormant model proposed in [2], and shows it to be inadequate in certain cases. It then extends that model by removing an unnecessary restriction and by using polynomial functions to approximate the terminal current-voltage characteristics. References [1] L. W. Nagel "SPICE2: A Computer Program to Simulate Semiconductor Circuits" Memorandum ERLM520, Electronics Research Laboratory, University of California, Berkeley, May, 1975. [2] K. A. Sakallah "Mixed Simulation of Electronic Integrated Circuits" Report DRC-02-07-81, Design Research Center, Carnegie-Mellon University, November, 1981. [3] K. A. Sakallah and S. W. Director "SAMSON: An Event Driven VLSI Circuit Simulator" In Proc. IEEE CICC, pp. 226-231. IEEE, 1984. [4] K. A. Sakallah and S. W. Director "SAMSON2: An Event Driven VLSI Circuit Simulator" accepted for publication in IEEE Trans. CAD. [5] W. M. G. Van Bokhoven "Linear Implicit Differentiation Formulas of Variable Step and Order" IEEE Trans. Circuits and Systems, CAS-22(2):109-115, February, 1975.

ICCAD85 – 6C.3, Pages 182-184

Switch Level Timing Simulation P.M. Dewilde, A.J. van Genderen, A.C. de Graaf Delft University of Technology, Department of Electrical Engineering, Mekelweg 4, 2628 CD Delft The Netherlands

ABSTRACT This paper describes a simulator that is capable of simulating a MOS circuit from switch level down to timing, in which the timing step is implemented as a direct extension of the switch level principle. To achieve this extension, a novel definition of the "state of a node" is expressed in terms of the parameters of a simple set of elementary approximating voltage functions. A proper selection of the state parameters allows eventdriven simulations based on simple electrical models for the actual transistor and interconnect properties. Experiments demonstrate that the simulator is a very valuable tool for quickly but accurately verifying MOS circuits, including their timing behavior, behavior of ratios, charge sharing, races and spikes. REFERENCES [1] R.E. Bryant "A switch-level model and simulator for MOS digital systems" IEEE Trans. Computers, vol. C-33, pp. 160-177, Feb. 1984. [2] J. Rubinstein, P. Penfield, Jr., and M.A. Horrowitz "Signal Delay in RC Tree Networks" IEEE Trans. Computer Aided Design, vol. CAD-2, pp. 202-211, July 1983. [3] J.L. Wyatt, Jr. "Signal Delay in RC Mesh Networks" IEEE Trans. Circuits and Systems, vol. CAS-32, pp. 507-510, May 1985. [4] T.M. Lin, and C.A. Mead "Signal Delay in General RC Networks" IEEE Trans. Computer Aided Design, vol. CAD-3, pp. 331-349, Oct. 1984. [5] G. Arnout and H.J. De Man "The Use of Threshold Functions and Boolean-Controlled Network Elements for Macromodeling of LSI Circuits" IEEE Journal Solid-State Circuits, vol. SC-13, pp. 326-332, June 1978.

ICCAD85 – 6C.4, Pages 185-187

A "Fast Timing" Simulation for Digital MOS Circuits David Tsao, Chin-Fu Chen AT & T Bell Laboratories, Murray Hill, New Jersey 07974

ABSTRACT An efficient and accurate algorithm has been developed for handling general MOS transistor circuits. The algorithm uses a switch level simulation technique to determine the steady state conditions, an E-LOGIC like technique to forward predict the delay between two adjacent voltage levels, a simplified timing simulation to correct this delay, and a novel approach for controlling the voltage step automatically. Finally, a table lookup model for determining the transistor current and a macro-model for evaluating a complex gate are also used to speed up the simulation. This algorithm has been implemented as a new mode of simulation called "Fast Timing" in the MOTIS3 multilevel mixed-mode simulator. Several production chips have been verified, and the results show that the fast-timing simulation can be three orders of magnitude faster than a conventional circuit simulator such as SPICE, one order of magnitude faster than MOTIS3 timing simulation, and only five times slower than MOTIS3 unit delay switch level simulation. The accuracy of the new simulator is within 10% of the circuit simulation. REFERENCES [1] C. F. Chen, C. Y. Lo, H. N. Nham, and P. Subramaniam "The Second Generation MOTIS Mixed-Mode simulator" Proceedings of 21st DA Conference, 1984, pp. 10-17. [2] C. F. Chen, and P. Subramaniam "The Second Generation MOTIS Timing Simulation - An Efficient and Accurate Approach for General MOS Circuits" Proceeding of the 1984 ISCS Montreal, Candana, May 7-10, 1984. PP. 538 - PP. 542. [3] Y. H. Kim, J. E. Kleckner, R. A. Saleh, A. R. Newton "Electrical-Logic Simulation" Proceedings of ICCAD-84, Santa Clara, Ca. NOV.12-15 1984, pp. 7-9. [4] H. N. Nham, A. K. Bose "A Multiple Delay Simulator For MOS LSI Circuits" Proceedings of 17th DA Conference, Minneapolis, Minnesota, June, 1980, pp. 610-617. [5] J. E. Kleckner "Advanced Mixed-Mode Simulation Techniques" Ph. D. Dissertation, U. C. at Berkeley. 1984 [6] P. Subramaniam "Table Models for Timing Simulation" Proceedings of the CICC, Rochester, N.Y. May 21-23, 1984, pp. 310-314. [7] A. J. de Geus "SPECS: Simulation Program For Electronic Circuits and System"Proceeding of the 1984 ISCS Montreal, Candana, May 7-10, 1984. PP. 534 - PP. 537

ICCAD85 – 7A.1, Pages 190-192

Connectivity Verification Using a Rule-Based Approach Rick L Spickelmier, A. Richard Newton Electronics Research Laboratory, University of California, Berkeley, California 94720

Abstract Connectivity verification is the process of comparing two circuit descriptions to make sure that they are topologically identical. This comparison is a one-to-one correspondence between elements and nodes in the two circuits, not some functional equivalence. The most common example of this is comparing a designer's simulation file (or schematic) with an extracted layout that is supposed to implement the designer's circuit. Almost all connectivity verifiers can handle the straightforward problem very efficiently. However, most of the time in these programs is spent handling the special cases, such as terminal permutability and parallel paths. A connectivity verification technique using a rule-based system has been developed that handles the above special cases with little performance penalty. The new rule-based system uses a global approach to the comparison, rather than the local techniques used in most conventional connectivity verifiers. An added advantage of this rule-based implementation is the ease with which new rules can be added by the user. References [AIE77] R. M. Allgair and D. S. Evans "A Comprehensive Approach to a Connectivity Audit, or a Fruitful Comparison of Apples and Oranges" The Proceedings of the Design Automation Conference 33 (1977), 312-321. [Ebe83] C. Eberling Gemini. Proceedings of ICCAD, November 1983. [For81] C. L. Forgy, OPS5 User's Manual, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, Pennsylvania, July 1981. [For82] C. L. Forgy "RETE: A Fast Algorithm for the Many Pattern Many Object Pattern Match Problem" Artificial Intelligence 19 (1982), 17-37. [MWE81] N. Miyahara, T. Watanabe, M. Endo and S. Yamada "A New CAD System for Automatic Logic Interconnection Verification" The Proceedings of the IEEE International Symposium on Circuits and Systems, 1981, 114-117. [SpN83] R. L. Spickelmier and A. R. Newton "WOMBAT: A New Connectivity Verification Program" Proceedings of ICCAD 83, November 1983, 170-171. [Spi83] R. L. Spickelmier "Verification of Circuit Interconnectivity" UCB Electronics Research Lab. M83 66, UC Berkeley Electronics Research Laboratory, October 21, 1983. [Tei83] W. Teitelman. Interlisp Reference Manual, October 1983.

ICCAD85 – 7A.2, Pages 193-195

A Parasitics Extraction Program for Closely-Spaced VLSI Interconnects Scott Powell, W. R. Smith, G. Persky Hughes Aircraft Company, Carlsbad, CA

INTRODUCTION In VLSI, circuit performance is heavily dependent on the parasitic resistance and capacitance of on-chip interconnect. As interconnect dimensions are reduced, the parallel line to line parasitic capacitance becomes increasingly important. The contribution of neighboring lines dominates loading for designs on insulating substrates or in submicron designs. Calculating line to line capacitance is difficult because of complicated interconnect geometries and wiring channel environments. A novel technique is presented below for accurately calculating the line to line capacitance associated with interconnect generated by an automatic router. This technique is imbedded within a CAD tool to provide back annotation for large scale designs. REFERENCES [1] Y. Wei "VLSI Parasitic Capacitance Extraction Based on Layout Information" Proc. ISCAS '84, pp. 697-700. [2] J. Reed and A. de Gues "RC Delay Extraction for Gate Array and Standard Cell Designs" Digest of Tech. Papers ICCAD '83, pp. 174-175. [3] J. Rubinstein, P. Penfield, and Mark Horowitz "Signal Delay in RC Tree Networks" IEEE Trans. on C.A.D., Vol. CAD-2, No. 3, July 1983, pp. 202-211. [4] T. Sakurai "Approximation of Wiring Delay in MOSFET LSI" IEEE J. Solid-State Circuits, Vol. SC18, No. 4, Aug. 1983, pp. 418-426. [5] R. Antonine and G. Brown "The Modeling of Resistive Interconnects for Integrated Circuits" IEEE J. Solid-State Circuits, Vol. SC-18, No. 4, 1983, pp. 200-203. [6] W. R. Smith and D. E. Snyder "Circuit Loading and Crosstalk Signals from Capacitance in SOS and Bulk-Silicon Interconnect Channels" Proc. IEEE VLSI Multilevel Interconnection Conference, 1984, pp. 218-227. [7] Peter Cottrell et. al. "Multi-Dimensional Simulation of VLSI Wiring Capacitance" IEDM Technical Digest, Dec. 1982, pp. 548-551. [8] M. Beaven, C. Enger, G. Persky, and J. Tsu "An Automated Layout System for VLSI Design" GOMAC, Nov. 1984, pp. 71-75.

ICCAD85 – 7A.3, Pages 196-198

Resistance Extraction in a Hierarchical IC Artwork Verification System Shojiro Mori Semiconductor Device Engineering Laboratory, Toshiba Corp., 1 Komukai-Toshiba-cho, Saiwai-ku, Kawasaki 210

James A. Wilmore Cupertino IC Division, Hewlett-Packard Company, 19420 Homestead Road Cupertino, CA 95014

Abstract A new resistance extraction module has been developed in a hierarchical artwork verification system to supplement to capacitance extraction module already developed. Efficient algorithms based on a scanline algorithm and a simple resistor model for a layout pattern provide high performance for LSI parasitic resistance analysis. Controllable accuracy is achieved by tailoring mask artwork and by tuning sheet resistance values to the mask patterns. Furthermore, the module is highly programmable, and can handle a lot of different IC technologies. Reference [1] Mori, S., Suwa I. and Wilmore. J. "Hierarchical Capacitance Extraction in an IC Verification System". Digest of Technical Papers, ICCAD - 1984. [2] Wilmore, James A. "The Design of the Database for the Sphinx IC Artwork Editing and Verification System". Digest of Technical Papers, ICCAD - 1984. [3] Kronmiller, T. and Lee, D.L. "The Sphinx IC Implementation Environment" Digest of Technical Papers, ICCAD - 1984. [4] McCormick, S.P. "EXCL: A Circuit Extractor for IC Designs" Proceeding of 21st DAC, June 1984, Pp. 616-623. [5] Horowitz M. and Dutton, R.W. "Resistance Extraction from Mask Layout Data" IEEE trans. on Computer-Aided Design Vol. CAD-2, NO. 3, July 1983 Pp. 145-150.

ICCAD85 – 7B.1, Pages 200-202

Simulated Annealing Controlled by a Rule-Based Expert System Timothy P. Moore, Aart J. de Geus General Electric Microelectronics Center, Research Triangle Park, North Carolina 27709

ABSTRACT Probabilistic Hill Climbing (PHC) algorithms are applied to the problem of PLA folding. To overcome the large CPU times associated with PHC approaches, a variant of Simulated Annealing is used in which the type of transformation is chosen as a function of the acceptance rate of the previous transformations. A Rule-Based Expert System adjusts the algorithm parameters as a function of the specific example being treated and dynamically controls the progress of the optimization. The results are on the average 10% better in area than those obtained by published heuristics with only two to three times the required CPU time. REFERENCES [1] S. Kirkpatrick, C. D. Gelatt, M. P. Vecchi "Optimization by Simulated Annealing" Science, Vol. 220, May 13 1983, pp. 671-680. [2] F. Romeo, A. Sangiovanni-Vincentelli "Probablistic Hill Climbing Algorithms: Properties and Applications" 1985 Chapel Hill Conference on VLSI, May 1985, pp. 393-417. [3] M.P. Vecchi, S. Kirkpatrick "Global Wiring by Simulated Annealing" IEEE Transactions on ComputerAided Design, Vol. CAD-2, October 1983, pp. 215-222. [4] C. Sechen, A. Sangiovanni-Vincentelli "The Timber Wolf Placement and Routing Package" Proceedings of the 1984 IEEE Custom Integrated Circuits Conference, May 1984, pp. 522-527. [5] R.K. Brayton, et al. ESPRESSO-IIC: Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Netherlands, 1984. [6] G. D. Hachtel, A. R. Newton, A. Sangiovanni-Vincentelli "An Algorithm for Optimal PLA Folding" IEEE Trans. CAD Int. Circ. Sys., April 1982, pp. 63-76. [7] G. De Micheli, A. Sangiovanni-Vincentelli "PLEASURE: A Computer Program for Simple and Multiple Constrained Folding of Programmable Logic Arrays" Proceedings of the 20th Design Automation Conference, June 1983. [8] G. De Micheli, M. Santomauro "Smile: A Computer Program for Partitioning of Programmed Logic Arrays" Computer-Aided Design, March 1983.

ICCAD85 – 7B.2, Pages 203-205

Simulated Annealing as a Tool for Logic Optimization in a CAD Environment H. Fleisher, J. Giraldi, D. B. Martin, R. L. Phoenix IBM Corporation, Poughkeepsie, N. Y.

M. A. Tavel Vassar College, Poughkeepsie, N. Y.

ABSTRACT Simulated Annealing (1) is found to be a useful strategy for optimizing multi-variable, multi-output Boolean logic functions for hardware implementation. Effective transformations such as decomposition [2] [3], bit partitioning [4] and minimization [5] can be applied (individually or in combination) to a function until a near-optimal form is reached. The entire process can be carried out in a CAD environment because the logic designer can readily modify the choice of transformation or optimization goals within the annealing process. REFERENCES [1] S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi "Optimization by Simulated Annealing" Science, Vol. 220, No. 4598, May 1983, p. 671. [2] J. Paul Roth "Minimization Over Boolean Trees" IBM Journal of Research and Development, Vol. 4, No. 5, November 1960, p. 543. [3] H. Fleisher, L. Maissel, and R. Phoenix "Extension Of The Two-Level Format For The Design of Multilevel Logic" IEEE 1984 Proceedings of the 4th Jerusalem Conference On Information Technology (JCIT), p. 658. [4] H. Fleisher and L. Maissel "An Introduction To Array Logic" IBM Journal of Research and Development, Vol. 19, No. 2, March 1975, p. 98. [5] S. J. Hong, R. G. Cain, and D. L. Ostapko "MINI: A Heuristic Approach For Logic Minimization" IBM Journal of Research and Development, Vol. 18, No. 5, September 1974, p. 443. [6] Steve R. White "Concepts of Scale In Simulated Annealing" IBM Research Report RC 10661 (\#47856), August 6, 1984.

ICCAD85 – 7B.3, Pages 206-208

A New Polynomial-Time Cooling Schedule E.H.L. Aarts, P.J.M. van Laarhoven Philips Research Laboratories, P.O. Box 80000, 5600 JA Eindhoven, the Netherlands.

ABSTRACT A new cooling schedule is presented which is, as opposed to more traditional schedules, based on a fixed Markov-chain length and a variable decrement of the cooling control parameter. Cooling algorithms governed by this schedule can be executed in polynomial time. Comparison with the more traditional cooling schedules shows that the new schedule yields better results requiring less computational effort. REFERENCES [1] Aarts, E.H.L. and P.J.M. van Laarhoven (Review Article) to be published. [2] Aarts, E.H.L. and P.J.M. van Laarhoven Philips Journ. Res. 40 (1985) 193. [3] Cerny, V.J. Opt. Th. and Appl. 45 (1985) 41. [4] Greene, J.W. and K.J. Supowit Proc. IEEE Conf. on Computer Design, Port Chester, 1984, p. 658. [5] Kirkpatrick, S., C.D. Gelatt Jr. and M.P. Vecchi Science 220 (1983) 671. [6] Metropolis, M. et al., J. Chem. Phys. 21 (1953) 1087. [7] Romeo, F. and A.L. Sangiovanni-Vincentelli University of Berkeley, Mem. No. UCB/ERL M 84/34, 1984. [8] Seneta, E. "Non Negative Matrices and Markov Chains" Springer Verlag, New York, 2nd edition, 1981.

ICCAD85 – 7C.1, Pages 210-212

A Knowledge-Based System for Analog Integrated Circuit Design Robert J. Bowman, David J. Lane Department of Computer Science and Electrical Engineering, The University of Vermont, Burlington, Vermont 05405

Abstract A knowledge-based design system (PROSAIC) has been developed to simplify analog integrated circuit design. PROSAIC applies expert system concepts to synthesize CMOS operational amplifier circuits to satisfy global performance specifications input by the human designer. References [1] M.G. Degrauwe and W.M. Sansen. "The Current Efficiency of MOS Transconductance Amplifiers" IEEE Journal of Solid-State Circuits, Vol. sc-19, No. 3, pp. 349-359, June 1984. [2] P.E. Allen, H. Nevarez-Lozano "Automated Design of Mos Op Amps" IEEE Symposium on Circuits and Systems, 1983, pp. 1286-1289. [3] G.G. Hendrix "Encoding Knowledge in Partitioned Networks," In “Associative Networks: Representation and Use of Knowledge by Computers" Academic Press, pp. 51-92, 1979. [4] A. Vladimirescu, K. Zhang, A.R. Newton, D.O. Pederson, A. Sangiovanni-Vincentelli "SPICE Version 2G - User's Guide" Department of Electrical Engineering and Computer Sciences, University of California, Berkeley CA 94720, 1981.

ICCAD85 – 7C.2, Pages 213-215

The Application of Knowledge-Based Design Techniques to Circuit Design Evangelos Simoudis , Stephen Fickas Computer Science Department, University of Oregon

Abstract The paper describes the framework of an integrated set of knowledge-based circuit design tools which provide an incremental, interactive style of design. In building the tools we have attempted to apply results from the area of knowledge-based software design. Our efforts concentrated around the issues of subsystem generation and reuse, and cell modification. The tools were developed using a new expert system language which facilitated the integration of our tools into a cohesive, expandable circuit design environment. Finally a prototype system, consisting of a rule-based cell-template layout tool, and a goal-directed rule-based layout editor, with a design rule checker operating in the background, is described. References [1] Brown, Harold, et al. "Palladio: An Exploratory Environment for Circuit Design" Computer, Vol. 16, No. 12, December 1983, pp. 41-56. [2] Mitchell, Thomas M., et al. "A Knowledge-Based Approach to Design" in Proc. IEEE Workshop on Principles of Knowledge-Based Systems, Denver, December 1984. [3] Steinberg, Louis I., Mitchell, Thomas M. "A Knowledge-Based Approach to VLSI CAD: the Redesign System" in Proc. IEEE 21st Design Automation Conf., 1984, pp. 412-418. [4] Swartout, W. and Balzer, R. "On the Inevitable Intertwining of Specification and Implementation" CACM, July 1982, pp. 438-440. [5] Fickas, S. "Automating Software Development: A Small Example" in Symposium on Applications and Assessment of Automated Software Development Tools, San Francisco, 1983. [6] Fickas, S. "Design issues in a Rule-Based System" in ACM Symposium on Programming Languages and Programming Environments Seattle, 1985. [7] Allen, E., Trigg, R., Wood, R. Maryland. Franzlisp Environment. TR 11226, Computer Science Dept., University of Maryland, Nov. 1983.

ICCAD85 – 7C.3, Pages 216-218

CLASS: A Chip Layout Assistant J. H. Kim, W. P. Birmingham, D. P. Siewiorek, R. Joobbani, G. York Dept. of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA 15213

Abstract Preliminary study for CLASS, a floorplanning tool is presented. The tool is aimed at helping system designers get quick feedback on the feasibility of realizing their design on silicon. CLASS emphasizes user interaction in order to improve the user's ability to complete a floorplan instead of generating the floorplan automatically. This emphasis is achieved by recognizing repetitive, well understood tasks and performing those tasks automatically. As the design progresses, new information allows CLASS to improve the design by propagating this information to appropriate parts of the design. References [1] C. L. Forgy. OPS5 User's Manual. Technical Report CMU-CS-81-135, Carnegie-Mellon University, 1981. [2] R. Joobbani, and D. P. Siewiorek. Weaver: A Knowledge-Based Routing Expert. In Proceedings of the 22nd Design Automation Conference, IEEE, June, 1985. [3] J. H. Kim, and J. McDermott. TALIB: An IC Layout Design Assistant. In Proceedings of the National Conference on Artificial Intelligence, pages 197-201. AAAI, August, 1983. [4] David Lapotin. Mason: A Tool for Integrated Circuit Floorplanning.

ICCAD85 – 8A.1, Pages 220-222

A Hardware Maze Router with Rip-Up and Reroute Support Tatsuo Ohtsuki, Masayoshi Tachibana, Kei Suzuki Department of Electronics and Communication Engineering, Waseda University, Tokyo, Japan

This paper presents a new parallel processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines which require N2 processors to implement the Lee algorithm on an N X N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 X 128 grid plane. The architecture of the machine is discussed together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute. REFERENCES [1] A. Isoupouicz "Design of an Iterative Array Maze Router" Proc. of ICCC, pp. 908-911, 1980. [2] M.A. Breuer, K. Shamsa "A Hardware Router" J. of Digital Systems, Vol. 4, pp. 393-408, 1981. [3] T. Blank, M. Stfik, W. vanCleempt "A Parallel Bit Map Architecture for DA Algorithms" 18th DA Conf., pp. 836-845, 1981. [4] S.J. Hong, R. Nair, E. Shapiro "A Physical Design Machine" in VLSI 81. London: Academic Press, 1981, pp. 257-266. [5] C. Sequin "Doubly Twisted Network for VLSI Processor Arrays" Proc. of 8th Ann. Symp. on Computer Architecture, pp. 471-480, 1981. [6] J. Soukup "Fast Maze Router" Proc. of 15th DA Conf., pp. 100-102, 1978. [7] M. Tachibana, S. Nakajima, T. Ohtsuki "An Architecture of Parallel Routing Processor" (in Japanese) TG CAS83-75 IECE of JAPAN, pp. 25-30, 1983.

ICCAD85 – 8A.2, Pages 223-225

Compacted Channel Routing David N. Deutsch Bell Communications Research, Inc., 435 South Street Morristown, N.J. 07960

Abstract Channel routing compaction is proposed as an obvious means to decrease routing area. Although the savings are very much dependent on specific values for various design rules and the terminal spacing, improvements of 15-20% can be achieved compared with the best "straight-track" results. The most critical feature seems to be the size of the contact "head" vis-a-vis the path width and separation. Compacted results for many different solutions to "Deutsch's Difficult Example" are given indicating both the value and the robustness of routing compaction. The effect of different design rules is also discussed. Compaction could be a post-processing step for many existing channel routers resulting in smaller area and better performance for a wide variety of design styles. A precise algorithm to accomplish channel routing compaction is presented. It is applicable to both one and two metal layer technologies and is suitable for both custom chips and gate arrays. A discussion of the benefits and limitations of routing compaction as well as suggestions for future work are also included. References [1] D.N. Deutsch "A 'Dogleg' Channel Router" Proc. 13th Design Automation Conference, pp. 425-433 (1976). [2] A. Hashimoto and J. Stevens "Wire Routing by Optimizing Channel Assignment within Large Apertures" Proc. 8th Design Automation Workshop, pp. 155-169 (1971). [3] B.W. Kernighan, D.G. Schweikert and G. Persky "An Optimum Channel-Routing Algorithm for Polycell Layouts of Integrated Circuits" Proc. 10th Design Automation Workshop, pp. 50-59 (1973). [4] T. Yoshimura and E.S. Kuh "Efficient Algorithms for Channel Routing" IEEF Trans. on CAD of ICs and Systems, Vol. CAD-1, No. 1, pp. 25-35 (1982). [5] T. Yoshimura "An Efficient Channel Router" Proc. 21st Design Automation Conference, pp. 38-44 (1984). [6] R.L. Rivest and C.M. Fiduccia "A 'Greedy' Channel Router" Proc. 19th Design Automation Conference, pp. 418-424 (1982). [7] M. Burstein and R. Pelavin "Hierarchical Channel Router" Proc. 20th Design Automation Conference, pp. 591-597 (1983). [8] A. Sangiovanni-Vincentelli and M. Santomauro "YACR: Yet Another Channel Router" Proc. Custom Integrated Circuits Conference, pp. 327-331 (1983). [9] A. Sangiovanni-Vincentelli, M. Santomauro and J. Reed "A New Gridless Channel Router: Yet Another Channel Router the Second (YACR-II)" Proc. of the IEEE International Conference on Computer-Aided Design, ICCAD-84, pp. 72-75 (1984).

[10] R.L. Rivest, A.E. Baratz and G. Miller "Provably Good Channel Routing Algorithms" Proc. CMU Conference on VLSI Systems and Computations, pp. 153-159 (1981). [11] D.J. Brown and R.L. Rivest "New Lower Bounds for Channel Width" Proc. CMU Conference on VLSI Systems and Computations, pp. 178-185 (1981). [12] F.T. Leighton "New Lower Bounds for Channel Routing" MIT VLSI Memo 82-71 (1982). [13] T.G. Szymanski "Dogleg Channel Routing is NP-Complete" IEEE Trans. on CAD of ICs and Systems, Vol. CAD-4, No. 1, pp. 31-40 (1985). [14] J.Y. Chen "Scaling CMOS to Submicron Design Rules for VLSI" VLSI Design, July 1984, pp. 78-83. [15] K. Sato, H. Shimoyama, T. Nagai, M. Ozaki, and T. Yahara "A 'Grid-free' Channel Router" Proc. 17th Design Automation Conference, pp. 22-31 (1980). [16] C. Mead and L. Conway. Introduction to VLSI Systems. Addison-Wesley Publishing Company, Reading, Mass. (1980). [17] W.E. Dickinson "Automatic Placement and Packed Wiring" IEEE Int. Conf. on Computer Design: VLSI in Computers, ICCD'84, pp. 742-744 (1984).

ICCAD85 – 8A.3, Pages 226-228

A Simulated-Annealing Channel Router. H. W. Leong, D. F. Wong, C. L. Liu Department of Computer Science, University of Illinois at Urbana-Champaign, 1304 W. Springfield, Urbana, IL 61801

Abstract In this paper we present the design and implementation of a channel router which employs the method of simulated annealing. Our research not only leads us to a better understanding of the capability and limitations of the method of simulated annealing as a general design methodology, and of some of the intricate technical aspects of the methodology when applied to the channel routing problem, but also produces a channel router that performs as well as several well-known channel routers and is potentially a powerful practical design tool. References [Ah74] Aho, A. V., J. E. Hopcroft and J. D. Ullman. The Design and Analysis of Computer Algorithms. (Addison Wesley), 1974. [BP83] Burstein, M. and R. Pelavin "Hierarchical Channel Router" Proc. 20th Design Automation Conf., IEEE (1983), 591-597. [Ki83] Kirkpatrick, S., C. D. Gelatt Jr. and M. P. Vecchi "Optimization by Simulated Annealing" Science Vol 220, (1983), 671-680. [RF82] Rivest, R. L. and C. M. Fidducia "A 'Greedy' Channel Router" Proc. 19th Design Automation Conf., IEEE (1982), 418-424. [VK83] Vecchi, M. P. and S. Kirpatrick "Global Wiring by Simulated Annealing" IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. CAD-2, (1982), 215-222. [YK82] Yoshimura, T. and E. S. Kuh "Efficient Algorithms for Channel Routing" IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol CAD-1 (1982), 25-35.

ICCAD85 – 8A.4, Pages 229-231

A Strategy for Introducing CAD into Microcomputer Design Atsushi Kurosawa, Aritoyo Kishimoto, Kazutaka Yamada, Kunio Mori, Nobuyuki Nishiguchi NEC Corporation, 1753 Shimonumabe, Nakahara-ku Kawasaki, 211 Japan

ABSTRACT This paper describes a CAD system for microcomputer chip layouts. The approach is not full automation, but selective introduction of CAD subsystems for efficient manual tailored layouts. The system is featured by the following three subsystems: (1) Contact-hole generating, [1] which allows a designer to make simple layout descriptions. (2) Technology independent design supported by automatic compaction [2] according to design rules. (3) Automatic layout verification [3] [4] concerning with electrical rules and its logic. The total effect of the system, in contrast to the traditional handcraft method, has been found to be approximately 2 times increase in design efficiency. REFERENCES [1] T. Fujioka, et al. "ADULTS-C: An Automatic Contact-hole Generating System for VLSI symbolic Layout" Proc. 1983 IE [sup.3] ICCD, PP.544-547, 1983 [2] N. Nishiguchi, et al. "VLSI Design Support System-Layout compacter (ADULTS-L)" Circuit and System, Rept. CAS83-210 (in Japanese), 1984 [3] A. Kishimoto, et al. "A Logic Function Extraction Algorithm for MOS VLSI" Proc ICCAD 1983, PP.143-144, 1983 [4] T. Fujioka, et al "An Electrical Rule Check System of LSI Artwork Data: SIMPLE PALMS" Monograph of Technical Group on Design Technology of Electronics Equipment of Inform. Process. Soc. Japan 10-2 (1981) (in Japanese)

ICCAD85 – 8B.1, Pages 234-236

A MOS Transistor Model-Evaluation Attached Processor for Circuit Simulation Ronald S. Gyurcsik, D. O. Pederson Department of Electrical Engineering and Computer Sciences Electronics Research Laboratory, University of California, Berkeley, California 94720

ABSTRACT The time required to solve the MOS transistor model equations comprises a large portion of the total circuit simulation time of MOS-dominated circuits. A reduction in total simulation time can be obtained with a special-purpose attached processor for the MOS transistor model evaluation. The MOS transistor model implemented by the attached processor is empirical, represented by piecewise cubic polynomials. The architecture of the attached processor supports the pipelined evaluation of multiple MOS transistors. A prototype has been built for the IBM Personal Computer which evaluates four transistors concurrently at approximately 100 µ−seconds per transistor evaluation. The prototype attached processor's transistor model evaluation time is two orders of magnitude faster than the time needed to evaluate the SPICE Level II MOS transistor model equations on the IBM PC-XT with a mathematics coprocessor. References [Coh81] E. Cohen. Performance Limits of Integrated Circuit Simulation on a Dedicated Minicomputer System. Memo No. UCB/Electronics Research Lab. M81/29, Electronics Research Laboratory, University of California, Berkeley, May 1981. [Deu85] J. T. Deutsch. Algorithms and Architecture for Multiprocessor-Based Circuit Simulation. Memo No. UCB/Electronics Research Lab. M85/39, Electronics Research Laboratory, University of California, Berkeley, May 1985. [FrC80] F. N. Fritsch and R. E. Carlson. Monotone Piecewise Cubic Interpolation. SIAM Journal of Numerical Analysis 17, 2 (April 1980), 238-246. [Gyu85] R. S. Gyurcsik. BIASC: A Circuit Simulation Program for use on the IBM Personal Computer. Proceedings of the WESCON/85 Convention, November 1985. [Nag75] L. W. Nagel. SPICE2 - A Computer Program to Simulate Semiconductor Circuits. Memo No. Electronics Research Lab.-M520, Electronics Research Laboratory, University of California, Berkeley, May 1975. [Sal84] R. A. Saleh. Iterated Timing Analysis and SPLICE1. Memo No. UCB/Electronics Research Lab. M84/2, Electronics Research Laboratory, University of California, Berkeley, January 1984. [SYD83] T. Shima, H. Yamada and R. L. M. Dang. Table Look-Up MOSFET Modeling System Using a 2D Device Simulator and Monotonic Piecewise Cubic Interpolation. IEEE Transactions On ComputerAided Design Of Integrated Circuits CAD-2, 2 (April 1983), 121-125. [TsM84] Y. P. Tsividis and G. Masetti. Problems With Precision Modeling of the MOS Transistor for Analog Applications. IEEE Transactions On Computer-Aided Design Of Integrated Circuits CAD-3, 1 (January 1984), 72-79.

[VIL80] A. Vladimirescu and S. Liu The Simulation of MOS Integrated Circuits Using SPICE2. Memo No. UCB/Electronics Research Lab. M80/7, Electronics Research Laboratory, University of California, Berkeley, October 1980. [Wei84] WTL 1032/1033 High-Speed Floating-Point Multiplier/ALU Data Sheet. Weitek Corporation, 1984. [Whi85] J. White. Private communications, 1985.

ICCAD85 – 8B.2, Pages 237-239

An Efficient Ordering Algorithm in the Modified Nodal Approach for VLSI Circuit Simulations Ping Yang VLSI Design Laboratory Texas Instruments Inc., MS 369, P. O. Box 225621 Dallas, Texas

Abstract A simple partitioning and ordering algorithm has been presented previously which guarantees that no zero-value pivots will be generated for the matrix formulated by the modified nodal approach. However, the resulting matrix is not structurally symmetric and the reordering of matrix equations is not completely flexible. The issue of reordering of equations for an asymmetrical matrix to minimize the number of fills has not been addressed. This presents a serious problem for VLSI circuit simulations, especially when large number of inductors need to be included to describe the circuit behavior accurately. The resulting large number of fills by a non-optimum reordering can easily increase the number of operations by an order of magnitude, which may explain why the matrix solution dominates the circuit simulation runtime for very large circuits in SPICE. In this paper, a revised partition scheme is presented which allows complete flexibility in the reordering of the matrix equations and at the same time guarantees that no zero-value pivots will be generated. A near-optimum reordering scheme has been constructed based on experimental results. The matrix operations for large circuits has been shown to be reduced by a factor of 3 to 400. References [1] P. Yang, I. N. Hajj and T. N. Trick "On Equation Ordering in the Modified Nodal Approach" Thirteenth Annual Asilomar Conference on Circuits, Systems and Computers, Pacific Grove, CA, Nov. 1979. [2] I. N. Hajj, P. Yang and T. N. Trick "Avoiding Zero Pivots in the Modified Nodal Approach" IEEE Trans. on Circuits and Systems, Vol. CAS-28, April 1981, pp. 271-279. [3] R. D. Berry "An Optimum Ordering of Electronic Circuit Equations for a Sparse Matrix Solution" IEEE Trans. Circuit Theory, Vol. CT-18, pp. 40-50, Jan. 1971. [4] L. N. Nagel "SPICE2: A Computer Program to Simulate Semiconductor Circuits" ERL Memo. ERLM520, Univ. of California, Berkeley, May 1975.

ICCAD85 – 8B.3, Pages 240-242

Nonlinear Circuit Simulation in the Frequency-Domain Kenneth S. Kundert, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA. 94720

Abstract Simulation in the frequency-domain avoids many of the severe problems experienced when trying to use traditional time-domain simulators such as SPICE [1] to find the steady-state behavior of analog, RF, and microwave circuits. In particular, frequencydomain simulation eliminates problems from distributed components and high-Q circuits by forgoing a nonlinear differential equation representation of the circuit in favor of a complex algebraic representation. This paper describes the spectral Newton technique for performing simulation of nonlinear circuits in the frequency-domain, and its implementation in Harmonica. Also described are the techniques used by Harmonica to exploit both the structure of the spectral Newton formulation and the characteristics of the circuits that would be typically seen by this type of simulator. These techniques allow Harmonica to be used on much larger circuits than were normally attempted by previous nonlinear frequency-domain simulators, making it suitable for use on Monolithic Microwave Integrated Circuits (MMICs). References [1] Laurence W. Nagel SPICE2: A Computer Program to Simulate Semiconductor Circuits, Electronics Research Laboratory Publications, U.C.B., 94720, Memorandum No. UCB/ERL M520, May 1975. [2] T.J. Aprille, T.N. Trick "Steady-state analysis of nonlinear circuits with periodic inputs." Proceedings of the IEEE, Vol. 60, pp. 108-114, January 1972. [3] Stig Skelboe "Computation of the periodic steady-state response of nonlinear networks by extrapolation methods" IEEE Transactions on Circuits and Systems, Vol. CAS-27, No. 3, pp. 161-175, March 1980. [4] M. Nakhla, J. Vlach "A piecewise harmonic balance technique for determination of the periodic response of nonlinear systems" IEEE Transactions on Circuits and Systems, Vol. CAS-23, No. 2, pp. 8591, February 1976. [5] K. Gopal, M.S. Nakhla, K. Singhal, J. Vlach "Distortion analysis of transistor networks" IEEE Transactions on Circuits and Systems, Vol. CAS-25, No. 2, pp. 99-106, February 1978. [6] F. Filicori, o. Monaco, C. Naldi "Simulation and design of microwave class-C amplifiers through harmonic analysis" IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-27, No. 12, pp. 1042-1051, December 1979. [7] A. Ushida, L.O. Chua "Frequency-domain analysis of nonlinear circuits driven by multi-tone signals" IEEE Transactions on Circuits and Systems, Vol. CAS-31, No. 9, pp. 766-778, September 1984.

[8] Richard J. Anobile. Alien, Avon, 1979. This modification of the Alien's teaser was found on a men's bathroom wall in Cory Hall; U.C. Berkeley. [9] J.M. Ortega, W.C. Rheinboldt. Iterative Solution of Nonlinear Equations in Several Variables, R Academic Press, 1970. [10] J.B. Beyer, S.N. Prasad, R.C. Becker, J.E. Nordman, G.K. Hohenwarter "MESFET distributed amplifier design guidelines" IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-32, No. 3, pp. 268-275, March 1984.

ICCAD85 – 8C.1, Pages 244-246

Exclusion Constraints for Digital MOS Circuits: A New Set of Electrical Design Rules Kevin Karplus Cornell University, School of Electrical Engineering (also in Computer Science Department)

Abstract Exclusion constraints are boolean equations that must always be satisfied for an MOS circuit to be adequately modeled by simple switch models. The constraints are generated by a new set of electrical design rules, which are simple enough to be checked automatically. Violating an exclusion constraint does not necessarily mean a circuit is unusable, but careful analysis or analog simulation is needed to ensure digital operation. The rules attempt to formalize common rule-of-thumb design practices, summarized as follows: Rule 1: Avoid shorting power. Rule 2: Avoid changing the inputs. Rule 3: Avoid parallel pullups. Rule 4: Avoid gates in the middle of pulldown chains. Rule 5: Avoid charge-sharing. Rule 6: Avoid odd inverter cycles. Rule 1 is the primary well-formedness criterion for static CMOS and pre-charged circuits. Rule 2 prevents sneak paths that can cause modules to behave incorrectly when connected. Rule 3 makes inverter ratio checking more accurate, and points out where special ratio computations are needed. Rule 4 detects un-intentional bi-directional pass transistors. Rule 5 detects some situations in which circuit behavior is not digital. Rule 6 detects oscillation and some non-digital circuit behavior. References [1] Robert Tarjan. "Fast algorithms for solving path problems" Journal of the Association for Computing Machinery 28(3), 1981, 594-614. [2] Alan George and Joseph Liu. Computer Solution of Large Sparse Positive Definite Systems. Prentice Hall, Englewood Cliffs NJ, 1981. [3] Kevin Karplus. A Formal Model for MOS Clocking Disciplines. Cornell Computer Science Technical Report 84-632, August 1984. [4] David Cooke Noice. A Clocking Discipline for Two-phase Digital Integrated Circuits. Stanford PhD Thesis, January 1983. University Microfilms 8314482. [5] Randal E. Bryant. Graph-based Algorithms for Boolean Function Manipulation. Carnegie Mellon Computer Science Technical Report CMU-CS-85-135. [6] E. M. Reingold, J. Nievergelt, and N. Deo. Combinatorial Algorithms, Theory and Practice. Prentice Hall, Englewood Cliffs NJ, 1977.

ICCAD85 – 8C.2, Pages 247-249

Using a Relational Database for Spice Results Analysis Mark G. Faust Electrical Engineering Department, University of Portland, Portland, OR 97203

Abstract Spice is widely used for circuit simulation despite the difficulty in analyzing the results it produces. This paper describes Sugar, a flexible system using a relational database and query language for the analysis and perusal of Spice output results. Sugar allows the IC designer to present even complex queries in a simple relational query language, print summaries, and to graph output data from Spice results files. References [1] L.W. Nagel "SPICE2: A Computer program to simulate semiconductor circuits" Memo No. ERLM520, University of California, Berkeley, 1975. [2] C.J. Date. An Introduction to Database Systems. 3rd edition, Addison-Wesley, 1983. [3] T.W. Sidle "Weaknesses of commercial data base management systems in engineering applications" Proceedings of the 17th Design Automation Conference, 1980. [4] W. Kent "A simple guide to five normal forms in relational database theory" Communications of the ACM, 26(2), February, 1983. [5] "Ingres Reference Manual." Relational Technology Incorporated, Berkeley, CA. 1985. [6] R.H. Katz "A Database approach for managing VLSI design data." Proceedings of the 19th Design Automation Conference, 1982. [7] R.H. Katz "Computer-aided design databases" IEEE Design and Test, 2(1), February, 1985.

ICCAD85 – 8C.3, Pages 250-252

In Retrospect: Setup of a Semicustom Library Development Group Tina Nerat Applied Micro Circuits Corporation, San Diego, CA.

INTRODUCTION This paper represents a view in retrospect AMCC's efforts to establish a library development group to support on-site design. On-site design is the capability of customers to design on their own Engineering Workstation (EWS) utilizing AMCC component libraries and support software. This recounts the learning curve, the pitfalls, the original approaches, and the changes instituted during the evolution of a semi custom library development group. REFERENCES [1] Earl Ravid and Tina Nerat "Problems in Logic-Array Design on Engineering Workstations" VLSI DESIGN September, 1984.

ICCAD85 – 8C.4, Pages 253-255

Computer-Aided Heat Sink Design for Printed Wiring Boards Michael Pecht, Milton Palmer, John Horan Mechanical Engineering Department, University of Maryland, College Park, MD 20742

ABSTRACT A computer-aided design (CAD) program has been developed which generates a graphical layout of a printed wiring board (PWB) showing its fundamental characteristics, automatically performs a heat sink design for conductively cooled in-line PWBs, and sets up a working data base containing generated thermal characteristics for subsequent thermal and reliability analysis. The program was designed to interface with an existing computer-aided component layout and routing routine and to be user interactive. REFERENCES [1] "Integrated Thermal Avionics Design (ITAD)" AFFDL-TR-78-76, Westinghouse Defense and Electronic Systems Center, June (1978). [2] The Redac Mini/Maxi PCB Designer Data Preparation, Issue 2, Feb. (1982). [3] Pound, R. "Thermal CAD Brings Hot Spots Under Control" Electronic Packaging and Production, p. 56, April (1983). [4] Hillier, W. and W. Meadows "A Decade of PCB Design Experience" Electronics and Power, p. 10, June (1981). [5] Dixon, J. and M. Simmons "Computers That Design: Expert Systems for Mechanical Engineers" CIME, p. 10, November (1983). [6] Hamilton, C. A Guide to Circuit Board Design. Butterworth London, (1984). [7] Horan, John "Graphical Integration of Thermal Analysis with Computer-Aided PCB Design" Masters Thesis, Mechanical Engineering Department University of Maryland, College Park, MD, January (1985). [8] Pecht, M., Palmer, M. and J. Horan "Expert System Integration in the Design of PWBs" Westinghouse Report, IAG-WR/DEC 1, Jan. 1985. [9] Horan, J., Palmer, M., Pecht M. and Y. Wong "Intelligent Design of Printed Wiring Boards" Proceeding: Association for Computing Machinery, Vol. 1, p. 123, (1985). [10] Mitchell, C., et al. "Thermal Studies of a Plastic Dual-in-Line Package" IEE Transactions on Components, Hybrids, and Manufacturing Technology, Chmt-2, No. 4, (1979). [11] Bar-Cohen, A. et. al. "Thermal Frontiers in the Design and Packaging of Microelectronic Equipment" Mechanical Engineering, pp 53-59, June (1983). [12] "Reliability Prediction of Electronic Equipment" Military Handbook, January (1982).

ICCAD85 – 9A.1, Pages 260-262

SPARTA: A Partitioning Spreadsheet Martin L. Resnick GTE Laboratories, Waltham, Massachusetts 02254

ABSTRACT Partitioning is the design phase in which a system's functionality is divided into smaller parts that fit onto physical units. SPARTA is a partitioning spreadsheet program for evaluating trial partitions against an objective and reporting any violations of limits. To use SPARTA a designer specifies property values for elements of a design, imposes limits on those values for physical units, and states the objective of the partitioning. REFERENCES [1] D. Hill and W.vanCleemput "SABLE, A Tool for Generating Structured Multi-Level Simulation" 16th Design Automation Conference, June 1979. [2] G. Estrin "A Methodology for the Design of Digital Systems, Supported by SARA at the Age of One" Proceedings National Computer Conference, June 1978. [3] T.S. Payne and W.M. vanCleemput "Automated Partitioning of Hierarchically Specified Digital Systems" 19th Design Automation Conference, June 1982. [4] R.L. Russo, P.H. Oden, P.K. Wolf "ALMS: Automated Logic Mapping System" Proceedings of the SHARE-ACM-IEEE Design Automation Workshop, 1971. [5] S. German and K. Lieberherr "Zeus: A Language for Expressing Algorithms in Hardware" IEEE Computer, February 1985. [6] B.W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" The Bell System Technical Journal, February 1970.

ICCAD85 – 9A.2, Pages 263-265

Data Path Synthesis with/without Constraints Gee-Gwo Mei, Wentai Liu Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 276957911

ABSTRACT In this paper, we present a method to synthesize the data path directly from the behavior language with/without the constraints on the number of operators. The method consists of operator, bus, and storage element allocators. Hu's, A*, and cliques partitioning algorithms are adopted to implement those three allocators respectively. By using allocation sequences and algorithms different from Tseng and Siewiorek's, in which only the case without constraints being considered, our method produces better result. Moreover, ours can be applied to the case with constraints which is not formally studied before. REFERENCES [1] G. Zimmerman "MDS - The Mimola Design System" Journal of Digital Systems 4(3) pp. 337-369 (1980). [2] D. E. Thomas, C. Y. Hitchcock III, T. J. Kowalski, J. V. Rojan, and R. J. Walker "Methods of Automatic Data Path Synthesis" IEEE Computer 16(12) pp. 59-70 (December 1983). [3] L. J. Hafer and A. C. Parker "Automated Synthesis of Digital Hardware" IEEE Trans. Comput. C31(2)(February 1982). [4] C. J. Tseng and D. P. Siewiorek "Facet: A Procedure for the Automated Synthesis of Digital, Twentieth Design Automation Conference', pp. 490-496 (1983). [5] C. J. Tseng and D. P. Siewiorek "Emerald: A Bus Style Designer" Twenty First Desing Automation Conference, pp. 315-321 (1984). [6] C. L. Seitz "Concurrent VLSI Architecture" IEEE Trans. Comput. C-33(12)pp. 1247-1265 (December 1984). [7] R. Sethi "Algorithms for Minimal-Length Scheduling" in Computer and Job-Shop Scheduling Theory, ed. Coffman, John Wiley and Son (1976). [8] N. J. Nilsson "Search Strategies for Al Production Systems" pp. 74-84 in Principle of Artificial Intelligence, Tioga (1980). [9] J. D. Ullman "Complexity of Sequencing Problems" in Computer and Job-Shop Scheduling Theory, ed. Coffman, John Wiley and Son (1976). [10] T. C. Hu "Parallel Sequencing and Assembly Line Problems" Operations Research 9(1961). [11] E. Rich "Advanced Problem-Solving Systems" pp. 201-277 in Artificial Intelligence, McGraw-Hill (1983).

[12] G. Mei and W. Liu "On Applying the Planning Method to VLSI Data Path Synthesis" In Preparation, (1985).

ICCAD85 – 9A.3, Pages 266-268

Processor Control Part Synthesis Tool Yields Short Turnaround Times by High Level Description Lukas Loeffler, Roland Schmid, Utz G. Baitinger Institute for Information Processing, University of Karlsruhe (TH), Kaiserstr. 12, D-7500 Karlsruhe 1, West Germany

Abstract This paper describes a computer based design system for the automatic design of the control logic of digital processors. The system uses a functional and a structural description as its input and generates various control flow implementations as specified by the user. Covering the whole range from the machine level of a processor down to the complete hardware of firmware solution, the use of our design system will greatly reduce the time required for the logic design of a digital processor"s control part. The designer will be able to investigate a variety of control flow implementations using one high level input only. References [1] W. Grass, H.M. Lipp "LOGE - A Highly Effective System for Logic Design Automation" ACM SIGDA Newsletter, Vol. 9, June 1979, pp 6-13 [2] W. Grass, G. Biehl, S. Hall "LOGE-MAT: A Program for the Synthesis of Microprogrammed Controllers" Proc. 4th International Conference on Computers in Design Engineering, Brighton, March 1980, pp 543-558 [3] G. Biehl, W. Grass, S. Hall "Optimization of the Influence of Problem Modifications on Given Microprogrammed Controllers" Proc. 17th Design Automation Conference, Minneapolis, June 1980, pp 309-317 [4] S. Dasgupta, J. Tartar "The Identification of Maximal Parallelism in Straight-Line Microprograms" IEEE Trans. on Computers, Vol. C-25, No. 10, Oct. 1976, pp 986-992 [5] J.A. Fisher "Trace Scheduling: A Technique for Global Microcode Compaction" IEEE Trans. on Computers, Vol. C-30, No. 7, July 1981, pp 478-490 [6] G. Biehl "Erhohung der Arbeitsgeschwindigkeit digitaler Steuerungen durch Maximierung des Parallelitatsgrades" Ph.D. thesis, Universitat Karlsruhe, 1981 [7] S.W. Director et al. "A Design Methodology and Computer Aids for Digital VLSI Systems" IEEE Trans. on Circuits and Systems, Vol. CAS-28, No. 7, July 1981 [8] A.W. Nagle, A.C. Parker "Algorithms for Multiple-Criterion Design of Microprogrammed Control Hardware" Proc. 18th Design Automation Conference, 1981, pp 486-493 [9] G. Zimmermann "The MIMOLA Design System: A Computer Aided Digital Processor Design Method" Proc. 16th Design Automation Conference, 1979, pp 53-58

[10] P. Marwedel "The MIMOLA Design System: Detailed Description of the Software System" Proc. 16th Design Automation Conference, 1979, pp 59-63

ICCAD85 – 9B.1, Pages 270-272

Hierarchical Routing of Single Layer Metal Trees in Compiled VLSI David W. Russell Seattle Silicon Technology, 12356 Northup Way Bellevue, WA

In hierarchical VLSI systems, modules must be independently routed for power and ground, as well as possibly for any number of other metal-only clock and voltage reference lines. User definition of module interfaces precludes making any useful assumptions of module port placement. This paper presents a technique for growing multiple trees of metal-only nets by routing each tree under a selective avoidance cost function and then resolving conflicts after each node addition. Trees are constrained to lie only on the boundaries of local routing regions. REFERENCES [1] Lie, Margaret, and Chi-Song Horng. "A Bus Router for IC Layout" ACM IEEE Nineteenth Design Automation Conference Proceedings, July, 1982 pages 129-132. [2] Rothermel, H-J., and D. A. Mlynski. "Computation of Power Supply Nets in VLSI Layout" ACM IEEE Eighteenth Design Automation Conference Proceedings, 1981, pages 37-42. [3] Hassett, James E. "Automatic Layout in ASHLAR: An Approach to the Problems of 'General Cell' Layout for VLSI" ACM IEEE Nineteenth Design Automation Conference Proceedings, July, 1982, pages 777-784. [4] Rivest, Ronald L. "The 'PI' (Placement and Interconnect) System" ACM IEEE Nineteenth Design Automation Conference Proceedings, July, 1982, pages 475-481. [5] Moulton, Andrew. "Laying the Power and Ground Wires on a VLSI Chip" ACM IEEE 20th Design Automation Conference, 1983, pages 754-755. [6] Chen, Nang-Ping. University of California, Berkeley Doctoral Thesis, 1983. [7] Moulton, Andrew. "private communication" MIT paper 1984. [8] Syed, Azhir A.;, Abbas El Gamal, and M. A. Breuer. "On Routing for Custom Integrated Circuits" ACM IEEE Nineteenth Design Automation Conference Proceedings, July, 1982, pages 887-893. [9] Syed, Zahir A., and Abbas El Gamal. "Single Layer Routing of Power and Ground Networks in Integrated Circuits" Journal of Digital Systems, Volume VI, Number 1, Spring, 1982, pages 53-63. [10] Aho, Hopcraft, Ullman "The Design and Analysis of Computer Algorithms" Addison Wesley Publishing Company, Reading, MA 1974.

ICCAD85 – 9B.2, Pages 273-275

New Algorithms for Hierarchical Place and Route of Custom VLSI C. Fowler, G.D. Hachtel, L. Roybal University of Colorado Department of Electrical and Computer Engineering, Campus Box 425 Boulder, CO 80309

Abstract We describe in this paper a system for hierarchical place and route of sets of custom or standard cell modules specified in a high level language. We perform MIN-CUT placement, which automatically creates a slicing structure. Placement is hierarchical, and can handle floorplanning of rectangular custom blocks or of conventional standard cell row blocks. In our system, placement is automatically adjusted to permit 100% routing completion. The channel routing algorithm derive from the "Greedy" router, but with the following novel features: a) it is gridless; b) it efficiently exploits wiring space in the variable width channels which arise in custom place and route; and c) it handles 3rd-layer net pinouts inside the channel. Our system also features a novel, linear complexity, bottleneck shortest path algorithm for the global routing phase. Other global routers require O(nlog n) or, more typically, O(n[sup.2]) operations for the global routing of each net, where n is the number of channels in the channel graph. The complexity of our global router is O(n) operations (per net) for edge sparse channel graphs. References [CCH85] N.P. Chen, C.C. Chen, C.P. Hsu, H.H. Chen, E.S. Kuh and M. Marek-Sadowska. BBL-2 User's Manual Electronics Research Laboratory, college of Engineering, University of California, Berkeley, CA 94720, January 24, 1985. [COK81] T. Chiba, N. Okuda, T. Kambe, I. Nishioka and S. Kiura. SHARPS: A Hierarchical Layout System for VLSI, Proc. 18th Design Automation Conference, June 1981, 293-300. [Han65] M. Hanan. No Wiring for Large Scale Integrated Circuits, IBM Research Rep. RC-1375, February 1965. [Kim83] S. Kimura. An Automatic Routing Scheme for General Cell LSI, IEEE Trans. Computer Aided Design CAD-2, 2 (October 1983), 285-292. [Lau79] U. Lauther. A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation, Proceedings of the 16th Design Automation Conference, 1979, 1-10. [OHM85] J. Ousterhout, G. Hamachi, R. Mayo, W. Scott and G. Taylor. The Magic VLSI Layout System, IEEE Design and Test, , February 1985. [RiF82] R. L. Rivest and C. M. Fiduccia. A 'Greedy' Channel Router, Proc. 19th Design Automation Conference,, 1982, 418-424. [Tar83] R. E. Tarjan. Data Structures and Network Algorithms, SIAM Monograph 44, Philadelphia, 1983.

[Wag76] R. A. Wagner. A Shortest Path Algorithm for Edge-sparse Graphs, J. Assoc. Comput. Mach. 23, (1976), 50-57. [Wis] J. Wisniewski. Private Communication, SANDIA Laboratories.

ICCAD85 – 9B.3, Pages 276-278

A Manually Driven Line Search Router in a Line Editor David W. Hightower GE Semiconductor Microelectronics Center, PO Box 13049 Research Triangle Park, NC 27709

ABSTRACT MODWIRE TM (Modification of Designs With an Intelligent Routing Editor) is an interactive gate array routing editor system which uses a manually controlled line search router to help the user quickly find routing paths. This feature, called Explore, has been used to complete routing failures on very large gate arrays (up to 13,500 2-input logic gates). This paper describes MODWIRE and Explore (including an improvement to the trace-back phase of the line search algorithm), and describes some of the data structures that permit virtually immediate response on all editing, routing, and informative commands. REFERENCES [1] Hightower, D. "A solution to Line Routing Problems on the Continuous Plane." Proceedings 6th Design Automation Workshop, June, 1969. [2] Moore, E. "Shortest Path Through a Maze." Annals of the Harvard Computation Harvard University Press, Cambridge, Mass., Vol. 30, 1959. [3] Hoel, J. "Some Variations of Lee's Algorithm." IEEE Transactions on Computers, vol C-25, January, 1976. [4] Hightower, D. "An Automatic Router for Single-level CMOS Gate Arrays." International Symposium on Circuits and Systems Proceedings (IEEE 82CH1681-6), May, 1982. [5] Hightower, D. "The Lee Router Revisited." Proceedings International Conference on Computer Design (IEEE 83CH1935-6), November, 1983. [6] Cohoon, J. "A Line Intersection Algorithm for the Routing Problem." University of Virginia, School of Engineering and Applied Science Report DAMACS 1984-02.

ICCAD85 – 9C.1, Pages 280-282

MASTIF - A Workstation Approach to Fabrication Process Design Duane S. Boning, Dimitri A. Antoniadis Massachusetts Institute of Technology, Cambridge, MA 02139

ABSTRACT The design of a fabrication process increasingly necessitates the availability and use of a variety of tools, including process and device simulation, analysis, and synthesis aids. The MASTIF workstation (MIT Analysis and Simulation Tools for IC Fabrication) is a menu and window oriented program written in C and Fortran which provides a methodology and uniform software structure for the connection of process and device design tools. MASTIF currently includes a facility for incremental development and version management of a process description, management mechanisms for definition of physical cross sections deriving from the overall process description, and an interactive graphics interface and data interchange for process and device simulators (SUPREM III and MINIMOS). With MASTIF, the user can effectively develop and evaluate a fabrication process via a single integrated workstation. REFERENCES [1] C.P. Ho, J.D. Plummer, S.E. Hansen, and R.W. Dutton. VLSI Process Modeling SUPREM III, IEEE Trans. Electron Devices, Vol. ED-30, No. 11, pp. 1438-1452, Nov. 1983. [2] D. Chin, M. Kump, R.W. Dutton. SUPRA - Stanford University PRocess Analysis program, Reference Manual, July 1981. [3] S. Selberherr, A. Schutz, H. W. Potzl. MINIMOS - A Two-Dimensional MOS Transistor Analyzer, IEEE Trans. on Electron Devices, Vol. ED-27, No. 8, p. 1540, August 1980. [4] K.M. Cham, S.-Y. Oh, and J.L. Moll. Computer Aided Design in VLSI Device Development, IEEE J. Solid State Circuits, Vol. SC-20, No. 2, pp. 495-500, April 1985. [5] A.R. Neureuther, C.H. Ting, and C.Y. Liu. Application of Line-Edge Profile Simulation to Thin-Film Deposition Processes, IEEE Trans. Electron Devices, Vol. ED-27, No. 8, pp. 1449-1459, August 1980. [6] G. L. Billingsley. Program Reference for KIC, Electronics Research Laboratory, U.C. Berkeley Memorandum No. UCB/ERL M83/62, October 1983.

ICCAD85 – 9C.2, Pages 283-285

Three-Dimensional Threshold Voltage Expressions for Both the LOCOS and Deep Trench Isolated MOSFET's Cheng T. Wang Department of Electrical Engineering, California State University, Long Beach, CA 90840

ABSTRACT Simple threshold voltage expressions based on an approximate three-dimensional analysis have been obtained for MOSFET's with different isolation techniques. It predicts both the short-channel and the narrow-width effects for MOSFET's with the LOCOS isolation and the results match the experimental data. In addition, the threshold expression is more general than any other existing models. An inverse narrow-width effect is predicted for MOSFET's with the deep-trench isolation and the threshold voltage drop as the width decreases is found to be milder if the lateral gate voltage (VDD) is reduced. REFERENCES [1] L.D. Yau "A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's" Solid-State Electron., Vol.17, pp.1059-1063, 1974. [2] L.A. Akers and C.S. Chao "A Closed-Form Threshold Voltage Expression for a Small-Geometry MOSFET"IEEE Trans. Electron Devices, vol.ED-29, pp.776-778, 1982. [3] G.W. Taylor "Subthreshold Conduction in MOSFET's" IEEE Trans. Electron Devices, vol.ED-25, pp.337-349, 1978. [4] C.S. Chao, L.A. Akers, and D.N. Pattanayak "Drain-Voltage Effects on the Threshold Voltage of a Small-Geometry MOSFET" Solid-State Electron., vol.26, pp.851-860, 1983. [5] K.N. Ratnakumar and J.D. Meindl "Short-Channel MOST Threshold Voltage Model" IEEE J. SolidState Circuits, vol.SC-17, pp.937-947, 1982. [6] R.D. Rung, H. Momose, and Y. Nagakubo "Deep Trench Isolated CMOS Devices" in IEDM Tech. Dig., pp.237-240, 1982. [7] C.T. Wang "The Charge-Burden Effect on the Threshold Voltage of Long-Channel VDMOSFET's" Tech. Dig. of International Conference on Computer-Aided-Design, pp.176-178, 1984. [8] C.T. Wang and D.H. Navon "Threshold and Punch-through Behavior of Laterally Nonuniformly Doped Short-Channel MOSFET's" IEEE Trans. Electron Devices, vol. ED-30, pp.776-782, 1983. [9] C.T. Wang "A Threshold Voltage Expression for Small-Size MOSFET's Based on An Approximate Three Dimensional Analysis" accepted for publication, IEEE Trans. on Electron Devices, Jan. 1986. [10] K.M. Cham and S.Y. Chiang "A Study of the Trench Surface Inversion Problem in the Trench CMOS Structure" IEEE Electron Device Letter, EDL-4, pp.303-305, 1983.

ICCAD85 – 9C.3, Pages 286-288

Statistical Characterization, Optimization and Design of Semiconductor Processes Using Computer Generated Data-Base Created by Mathematical Process and Device Simulators Osman Ersed Akcasu, Kyle Sadao Yakabu, James Lyle Bouknight Fairchild Camera and Instrument Corporation Memory and High Speed Logic Division, 1111 39th Avenue S.E., P.O. Box 5000, Puyallup, Washington 98373

ABSTRACT In this paper we present an accurate and efficient theoretical method of predicting statistical distributions of device modeling parameters from given statistical distributions which are related to process parameters. The analysis is based on a discrete multi-variate statistical approach under the assumption that each device parameter can be a function of up to three, but generally two independent process variables. The relationship between process and device parameters are evaluated by data-bases created by process and device simulations. The second objective is to use the same methodology to predict and optimize the parametric yield of the process, and tailor it to the imposed process or device requirements. REFERENCES [1] D. A. Antoniadis and R. W. Dutton "Models for Computer Simulation of Complete IC Fabrication Process" IEEE Journal of Solid State Circ., Vol. SC-14, No 2, April 1979, pp.412-422. [2] O. E. Akcasu "Convergence Properties of Newton's Method for the Solution of Semiconductor Transport Equations and Hybrid Solution Techniques for Multi-Dimensional Simulation of VLSI Devices" Solid-State Elec. Vol. 27, No 4, April 1984, pp.319-328. [3] A. Ito, L. K. Gast, W. T. Coston, R. E. Lowter, R. W. Webb, E. W. George "A Statistical Process and Device Simulator (SPADS)" ICCAD 1983 Technical Digest, pp.209-210.

ICCAD85 – 10A.1, Pages 290-292

Synthesis and Optimization of Multi-level Logic Under Timing Constraints K. Bartlett, W. Cohen Department of Electrical Engineering, University of Colorado at Boulder

A. De Geus General Electric Microelectronics Center

G. Hachtel Department of Electrical Engineering University of Colorado at Boulder

Abstract Automating the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry and guarantees functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes a synthesis system capable of generating combinational logic in a given technology under user defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. The presentation is necessarily brief. A full length paper is under preparation. References [1] Brayton, R.K., G.D. Hachtel, C.T. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Syntehsis. Kluwer Academic Publishers (1984). [2] Hachtel, G. D., A. R. Newton, and A. L. Sangiovanni-Vincentelli "An Algorithm for Optimal PLA Folding" IEEE Trans. on CAD of Int. Circ. and Syst. 1(2) pp. 63-77 (April 1982). [3] DeMicheli, G., M. Hoffman, A. R. Newton, and A. Sangiovanni-Vincentelli "A Design System for PLA-based Digital Circuits" in Advances in Computer Engineering Design, ed{ A. SangiovanniVincentelli, Jai Press (1985). [4] DeMicheli, G. and A. Sangiovanni-Vincentelli "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications" IEEE Trans. on CAD of IC and Systems CAD-2(3) pp. 151-167 (July 1983). [5] Brayton, R. K., C. L. Chen, C. T. McMullen, R.H.J.M. Otten, and J. Y. Yamour "Automated Implementation of Switching Functions as Dynamic CMOS Circuits" Custom Integrated Circuits Conference Proceedings, (May 21-23, 1984). [6] Hoffman, M. and R. Newton "Automatic Generation of CMOS DOMINO Logic" IEEE/ACM Design Automation Workshop (no proceedings), (April 1985). [7] Sasao, T. "An Application of Multiple-Valued Logic to a Design of Masterslice Gate Arrays" Proceedings ISMVL-82, (May 1982). [8] Darringer, J., D. Brand, J. Gerbi, W. Joyner, Jr., and L. Trevillyan "LSS: A System for Production Logic Synthesis" IBM Journal of Research and Development, (September 1984).

[9] Brayton, R.K. and C.T. McMullen "Synthesis and Optimization of Multistage Logic" Proceedings of the IEEE International Conference on Computer Design. (October 1984). [10] Cohen, W.W., K.A. Bartlett, and A.J. DeGeus "Impact of Meta-Rules in a Rule Based Expert System for Gate Level Optimization" Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 873-876 (June 1985). [11] DeGeus, A.J. and W. Cohen "A Rule Based System for Optimizing Combinational Logic" IEEE Design and Test of Computers, pp. 22-32 (August 1985). [12] Brayton, R.K. and C.T. McMullen "The Decomposition and Factorization of Boolean Expressions" Proceedings of the International Symposium on Circuits and Systems, pp. 49-54 (1982).

ICCAD85 – 10A.2, Pages 293-295

Symbolic Minimization of Logic Functions Giovanni De Micheli IBM - T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598

ABSTRACT Symbolic minimization consists of determining a two-level sum-of-products representation of a switching function in a minimal number of product-terms, independently of the Boolean encoding of all (or part of) the inputs and outputs. When the objective is to determine a binary-valued description, the minimal symbolic representation determines a set of constraints for the encoding of the input and outputs into Boolean variables. Symbolic minimization is related, but not equivalent, to multiplevalued logic minimization. It represents a new concept in switching theory. Formal definitions and properties of a symbolic representation of a switching function are presented for the first time. An algorithm for symbolic minimization is described. The algorithm is implemented in a computer program called CAPPUCCINO, which is built on top of a modified version of the heuristic logic minimizer ESPRESSO-II. REFERENCES [BRAY84b] R.Brayton, G.D.Hachtel, C.McMullen and A.L.Sangiovanni- Vincentelli "Logic Minimization Algorithms for VLSI Synthesis" Kluwer Academic Publishers, 1984. [DEMI84c] G.De Micheli, R.Brayton and A.L. Sangiovanni Vincentelli "KISS: a Program for Optimal State Assignment of Finite State Machines" Proc. ICCAD Santa Clara, nov 1984. [DEMI85a] G.De Micheli, R.Brayton and A.L.Sangiovanni Vincentelli "Optimal State Assignment for Finite State Machines" IEEE Transactions on CAD/ICAS, Vol. CAD-4, No. 3, pp.269-284, July 1985. [DEMI85b] G.De Micheli "Optimal Synthesis of Combinational and Sequential Circuits using Two-level Logic" (in preparation) [HONG74] S.J.Hong,R.G.Cain and D.L.Ostapko "MINI: a Heuristic Approach for Logic Minimization" IBM Jour. of Res. and Dev., vol. 18, pp. 443-458, sep. 1974. [NICH65] A.Nichols and A.Bernstein "State Assignment in Combinational Networks" IEEE Trans on Elect. Comp., vol. EC-14, pp. 343-349, Jun. 1965. [POST21] E.L.Post "Introduction to a General Theory of Elementary Propositions" Amer. J. Math., vol. 43, pp. 163-185, 1921. [RINE77] D.Rine "Computer Science and Multiple-Valued Logic" North Holland, 1977. [RUDE85a] R. Rudell and A. Sangiovanni-Vincentelli "ESPRESSO-MV: Algorithms for Multivlued Logic Minimization" Proc. Custom Int. Circ. Conf., Portland, Oregon, May 85. [SASA83] T.Sasao "Input Variable Assignment and Output Phase Assignment of PLAs" IBM Research Report, No. 1003, June 1983.

ICCAD85 – 10B.1, Pages 298-300

A "Greedy" Three Layer Channel Router Peter Bruell, Paul Sun Microelectronics and Computer Technology Corporation, Austin, Texas 78759

ABSTRACT We present a three layer "greedy" channel router based upon Rivest and Fiduccia's channel router. The channel router uses two wiring layers for horizontal routing, and one wiring layer for vertical routing. The computational complexity of the "greedy" algorithm is linearly proportional to the number of columns in a channel for the average case. Results from several "benchmark" examples are evaluated. The three layer "greedy" router found an 11 track solution for Deutsch's difficult example. Our solution is three track less than the reported result of 14 tracks by Chen and Liu. References [BP83] Burstein, M. and R. Pelavin "A Hierarchical Channel Router" Proc. 20th Design Automation Conference, 1983, 591-597. [CL84] Chen, Y.K. and M.L. Liu "Three Layer Channel Routing" IEEE Transactions on CAD, Vol. 3, No. 2, April 1984, 156-163. [De76] Deutsch, D.N. "A 'Dogleg' Channel Router" Proc. 13th Design Automation Conference, 1976, 425433. [HO84] Hamachi G. T. and Ousterhout J. K. "A switchbox router with obstacle avoidance" Proc. 21st Design Automation Conference, 1984, 173-179. [HS71] Hashimoto, A. and J. Stevens "Wire Routing by Optimizing Channel Assignment" Proc. 8th Design Automation Conference, 1971, 214-224. [King84] Kingsley, C. "A Hierarchical Error-Tolerant compactor" Proc. 21st Design Automation Conference, 1984, 126-132. [Klei82] Klein, K., E. Miersch, R. Remshardt, H. Schettler, U. Schultz, and R. Zuehlke "A Study on Bipolar VLSI Gate-Arrays Assuming Four Layers of Metal" IEEE Journal of Solid-State Circuits, Vol. SC17, No.3, June 1982, 472-480. [KSP73] Kernighan, B.W., D.G. Schweikert and G. Persky "An Optimum Channel-Routing Algorithm for Polycell Layouts of Integrated Circuits" Proc. 10th Design Automation Workship, 1973, 50-59. [MOTO] 2900ETL macrocell array user's manual. Motorola semiconductor products Inc. 1984. [MH84] Mori, H. "Interactive compaction router for VLSI layout" Proc. 21st Design Automation Conference, 1984, 137-143. [RF82] Rivest, R.I., and C.M. Fiduccia "A 'Greedy' Channel Router" Proc. 19th Design Automation Conference, 1982, 418-424.

[SS83] Sangiovanni-Vincentelli, A. and M. Santomauro "YACR: Yet Another Channel Router" Proc. Custom Int. Circ. Conf., 1983, 327-331. [SSR84] Sangiovanni-Vincentelli, A., M. Santomauro, and J. Reed "A New GridlessChannel Router the Second (YACR-II)" Proc. ICCAD, 1984. [Tagu84] Taguchi M., S. Audo, S. Hijiya, T. Nakamura, S. Economo, and T. Yabu "A CapacitanceCoupled Bit-Line Cell for Mb Level DRAMs" ISSCC Digest of Technical Papers, Feb. 1984, 100-101. [WL84] W. K. Luk "A greedy switch-box router" Research Report V158, Computer Science Dept., Carnegie-Mellon University, May, 1984. [YK82] Yoshimura, T. and E.S. Kuh "Efficient Algorithms for Channel Routing" IEEE Trans. CAD of ICs and Systems, Vol. CAD-1, n.1, 1982, 25-35.

ICCAD85 – 10B.2, Pages 301-303

A Modified Detour Router Yu-I Hsieh, C. C. Chang GE/CRD, P.O. BOX 8, Schenectady, NY 12301

ABSTRACT Detour [1] is a router that is capable of routing both switchboxes and channels. It gave the IC designers the option of prewiring special nets by hand or by other routers. We can use gridless channel router to route the gate array, standard cell and PCB systems if the modules are well placed. Some chips can be routed by using channel and switchbox routers, if those modules inside the chips are well placed. This class of module placement is called the Routable Net (R-Net) chips. Detour is one such example with some allignment problems to complete the routing patterns for the R-Nets. In this paper we show how to improve the Detour router to route the Burstein's difficult example. All chips that do not belong to the class of R-Net may need a global router to complete the routing patterns. REFERENCES [1] G. T. Hamachi and J. K. Ousterhout. A Switchbox Router with Obstacle Avoidance. Elect. Engr. and Compt. Sciences, UCB, SRC RP\#-841074. [2] Y. T. Lai. Algorithms for Floor Plan Design. Ph. D. Research Proposal, private communication. [3] R. L. Rivest and C. M. Fiduccia. A Greedy Channel Router. GE/CRD, Schenectady, NY 12301, March 1981. [4] M. Burstein and R. Pelavin. Hierarchical Channel Router. 20th DA Conference, 1983.

ICCAD85 – 10B.3, Pages 304-306

A Variable-Width Gridless Channel Router Howard H. Chen, Ernest S. Kuh Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA 94720

ABSTRACT In the traditional channel routing, terminals must be located on grid points and wire segments must be placed on grid lines. Without using the grids, we can take advantage of the two interconnection layers with different pitches. Terminals are no longer required to be on grids, and signals may even have different wire widths. The new gridless approach we propose is based on the design rules. The objective is to minimize the routing area, while keeping the constraints of wire widths and spacing satisfied. This router is also capable of handling channels with irregular boundaries, cyclic constraints, and prewirings. The algorithm has been implemented in C language, and will be integrated into our BBL (Berkeley Building-Block Layout) system. References [1] A. Hashimoto and J. Stevens "Wire routing by optimizing channel assignment within large apertures" in Proc. 8th Design Automation Workshop, pp. 155-169, 1971. [2] D. Deutsch "A dogleg channel router" in Proc. 13th Design Automation Conf., pp. 425-433, 1976. [3] D. Hightower "A generalized channel router" in Proc. 17th Design Automation Conf., pp. 12-21, 1980. [4] K. Sato et al. "A 'grid-free' channel router" in Proc. 17th Design Automation Conf., pp. 22-31, 1980. [5] T. Yoshimura, and E. S. Kuh "Efficient Algorithms for channel routing" IEEE Trans. on CAD of ICs and Systems, vol. CAD-1, no. 1, pp. 25-35, January 1982. [6] R. Rivest, and C. Fiduccia "A 'greedy' channel router" in Proc. 19th Design Automation Conf., pp. 418424, 1982. [7] M. Burstein, and R. Pelavin "Hierarchical channel router" in Proc. 20th Design Automation Conf., pp. 591-597, 1983. [8] A. Sangiovanni-Vincentelli, and M. Santomauro "YACR: Yet another channel router" in Proc. Cust. Int. Circ. Conf., pp. 327-331, 1983. [9] H. Rothermel, and D. Mlynski "Automatic variable-width routing for VLSI" IEEE Trans. on CAD, vol. CAD-2, no. 4, pp. 271-284, October 1983. [10] S. Kimura et al. "An automatic routing scheme for general cell LSI" IEEE Trans. on CAD, vol. CAD2, no. 4, pp. 285-292, October 1983. [11] T. Yoshimura "An efficient channel router" in Proc. 21st Design Automation Conf., pp. 38-44, 1984. [12] G. Hamachi and J. Ousterhout "A switch box router with obstacle avoidance" in Proc. 21st Design Automation Conf., pp. 173-179, 1984.

[13] A. Sangiovanni-Vincentelli et al. "A new gridless channel router : yet another channel router the second (YACR-II)" IEEE International Conference on Computer-Aided Design, pp. 72-75, 1984. [14] C. P. Hsu et al. "ALPS2 : A standard cell layout system for double-layer metal technology" in Proc. 22nd Design Automation Conf., pp. 443-448, 1985.

ICCAD85 – 10B.4, Pages 307-309

Switch-Box Routing the Greedy Way J.R. Stenstrom, R.M. Mattheyses General Electric Company Corporate Research and Development, Schenectady, NY 12345

ABSTRACT We present a switch-box routing algorithm based on the Rivest-Fiduccia Greedy Channel Router modified to accommodate specific target tracks for nets. To route a switch-box region, the modified greedy router is applied in two phases, the first running from left to right in the region and the second running from right to left. This router serves as the main router for the GE Two-Pi system, a descendant of the MIT PI project. REFERENCES [1] Deutsch, D.N. "A 'Dogleg' Channel Router" Proc. 13th Design Automation Conf. (1976), pp. 425-433. [2] Luk, W.K. "A Greedy Switch-box Router" Tech Rept, Computer Science Dept., Carnegie-Mellon University, VLSI-Doc. 158, April, 1984. [3] Pinter, R.Y. "On Routing Two-Point Nets Across a Channel" Proc. 19th Design Automation Conf. (1982), pp 894-902. [4] Rivest, R.L. "The 'PI' (Placement and Interconnect) System" Proc. 19th Design Automation Conf. (1982), pp 475-481. [5] Rivest, R. L. and Fiduccia, C.M. "A 'Greedy' Channel Router" Computer Aided Design Vol 15, No 3 (1983), pp 135-140. [6] Smith, L.R., Saxe, T., Newkirk, J., and Mathews, R. "A New Area Router, The LRS Algorithm" Proc. IEEE International Conf. on Circuits and Computers (1982), pp 256-259.

ICCAD85 – 10C.1, Pages 312-314

Parametric Yield Optimization for VLSI Dale E. Hocevar, Paul F. Cox, Ping Yang VLSI Design Laboratory Texas Instruments Inc., P.O. Box 225621, MS 369 Dallas, Texas 75265

Abstract In this modern age of VLSI circuits, the geometries continue to be scaled down; however, the underlying statistical process variations, do not necessarily scale down as fast. These variations are thus becoming more significant, in relation to the circuit performance. Statistical design tools are required to cope with these design problems. This paper is concerned with the statistical optimization problem, specifically yield maximization. Realistic techniques for accomplishing this are presented, with the major contribution being the technique for computing the yield gradient. This work is based upon the statistical modeling and analysis techniques that we have already developed for this problem [1] [2] [3] [4] [5]. The yield gradient is computed by differentiating the yield integral, and numerically performing the resulting integration, over the faces of the yield polytope. This gradient is then used in the maximization algorithm. References [1] P. Yang and P. K. Chatterjee "Statistical modelling of small geometry MOSFETS" IEEE Int. Elec. Dev. Meeting, pp. 286-289, Dec. 1982. [2] P. F. Cox, P. Yang, S. S. Mahant-Shetti, and P. K. Chatterjee "Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits" IEEE Trans. Elec. Dev., vol. ED-32, pp. 471-478, Feb. 1985. [3] Ping Yang and P. K. Chatterjee "SPICE modeling for small geometry MOSFET Circuits" IEEE Trans. Computer Aided Design of ICAS, vol. CAD-1, no. 4, pp. 169-182, October 1982. [4] Ping Yang and P. K. Chatterjee "An optimal parameter extraction program for MOSFET models" IEEE Trans. Elec. Dev., vol. ED-30, no. 9, pp. 1214-1219, Sept. 1983. [5] D. E. Hocevar, Ping Yang, T. N. Trick, and B. D. Epler "Transient sensitivity computation for MOSFET circuits" IEEE Trans. Computer Aided Design of ICAS, vol. CAD-4, no. 4; also in, IEEE Trans. Elec. Dev., vol. ED-32, no. 10, October 1985.

ICCAD85 – 10C.2, Pages 315-317

Statistical Design Rule Developer Rahul Razdan, Andrzej Strojwas Electrical and Computer Engineering Department, Carnegie-Mellon University, Pittsburgh, Pennsylvania 15213

Abstract In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. At the center of the approach is the concept of a statistical design rule which is defined as a geometric design rule with an associated probability of failure. Global lateral variations generated by FABRICS, and local spot defects are taken into account when calculating the probability of failure. An enhanced failure model is used to include both catastrophic and parametric faults. The model for failure also includes electrical effects, such as "punch-through" caused by expansion of the depletion layer in a short channel. STRUDEL can be used to optimize chip area for the actual distributions of the process disturbances and defects, and the tool can be used for coarse yield estimation during the design rules check. References [1] Robert D. Rung "Determining IC Layout Rules for Cost Minimization" IEEE Journal of Solid-State Circuits, February 1981, pp. 35-43. [2] Clark Beck "Computer Evaluated Layout Design Rules For Integrated Circuits" Proc. of the 1984 Custom Integrated Circuits Conference, IEEE, 1984, pp. 420-424. [3] Nassif, S.R., Strojwas, A.J., and Director, S.W. "FABRICS II: A Statistical Simulator of the IC Fabrication Process" IEEE Transactions on CAD of ICAS, Special Issue on Custom IC's, January 1984. [4] Wojciech Maly "Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits" IEEE Transactions on CAD of Integrated Circuits and Systems, IEEE, 1985, pp. 166-177. [5] Spanos, C. "PROMETHEUS" PhD Thesis, Carnegie-Mellon University, 1985.

ICCAD85 – 10C.3, Pages 318-320

VLASIC: A Yield Simulator for Integrated Circuits H. Walker, S. W. Director Computer Science Department and SRC-CMU Research Center for CAD, Carnegie-Mellon University, Pittsburgh, PA 15213

Abstract This paper describes the yield simulator VLASIC (VLSI LAyout Simulation for Integrated Circuits). VLASIC is a Monte Carlo simulator that uses a process model and defect statistics to place random catastrophic point defects on a chip layout and determine what circuit faults, if any, have occurred. This information can be used to predict yield, optimize design rules, generate test vectors, evaluate redundancy, etc. A redundancy analysis system which uses this data is described and an example of its use given. References [1] Anoop Gupta "ACE: A Circuit Extractor" Proceedings of the ACM IEEE 20th Design Automation Conference, June 1983. [2] C. Stapper, F. Armstrong, and K. Saji "Integrated Circuit Yield Statistics" Proceedings of the IEEE, Vol. 71, No. 4, April 1983, pp. 453-470. [3] C. H. Stapper "Modeling of Defects in Integrated Circuit Photolithographic Patterns" IBM Journal of Research and Development, Vol. 28, No. 4, July 1984, pp. 461-475. [4] O. Paz, and T. Lawson "Modification of Poisson Statistics: Modeling Defects Induced by Diffusion" IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 5, October 1977, pp. 540-546. [5] C.H. Stapper "LSI Yield Modeling and Process Monitoring" IBM Journal of Research and Development, Vol. 20, No. 3, May 1976, pp. 228-234. [6] R.M. Warner Jr. "Applying a Composite Model to the IC Yield Program" IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 3, June 1974, pp. 86-95. [7] Charles H. Stapper "Defect Density Distribution for LSI yield Calculations" IEEE Transactions on Electron Devices, Vol. ED-20, No. 7, July 1973, pp. 655-657. [8] W. Maly, F. Ferguson, and J. Shen "Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells" International Test Conference, IEEE, 1984.

ICCAD85 – 10C.4, Pages 321-323

PI/C: Process Interpreter/Compiler Patrick Kager, Andrzej Strojwas Electrical and Computer Engineering Department, Carnegie-Mellon University, Pittsburgh, Pennsylvania 15213

Abstract This paper presents a process interpreter/compiler (PI/C) which can be used for the synthesis of VLSI fabrication processes. PI/C, with the use of a graphical process editor (PED), and a statistical process/device simulator (FABRICS-II), allows the process designer to enter a graphical process description and receive instant feedback concerning process performance. PI/C automatically generates the process description needed by process and device simulators, after error checking has been performed to assure that the process entered will produce valid devices. References [1] Nassif, S.R., Strojwas, A.J., and Director, S.W. "Fabrics II: A Statistical Simulator of IC Fabrication Process" IEEE Transaction on CAD of ICAS, January 1984, Special Issue on Custom IC's [2] Kager, P.W. "PI/C: Process Interpreter/Compiler" Master's thesis, Carnegie-Mellon University, August 1985. [3] Low, K.K. "PED: A Graphical Process Editor for FABRICS-II" Master's thesis, Carnegie-Mellon University, May 1985. [4] Mead, C and Conway, L. Introduction of VLSI Systems. Addison-Wesley Publishing Company, 1980. [5] Ho, C.P., and Hansen, S.E. "SUPREM III - A Program for Integrated Circuit Process Modeling and Simulation" Tech. report SEL 83-001, Stanford Electronics Laboratories, Stanford University, July 1983. [6] Pinto, M.R., Rafferty, C.S., Dutton, R.N. "PISCES-II - User's Manual" Tech. report, Stanford University, August 1984.

ICCAD85 – 11A.1, Pages 326-328

TILOS: A Posynomial Programming Approach to Transistor Sizing J. P. Fishburn A. E. Dunlop AT&T Bell Laboratories, Murray Hill, New Jersey 07974

ABSTRACT A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) minimize A subject to T