1986 Abstracts - CiteSeerX

1986 ICCAD, Pages 2-5

Mighty: A 'Rip-Up and Reroute' Detailed Router Hyunchul Shin, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720

ABSTRACT For the macro-cell design style and for routing problems where the routing regions are irregular, two dimensional routers are often necessary. In this paper a new routing technique that can be applied for general two-layer detailed routing problems including switch boxes, channels and partially routed areas, is presented. The routing regions that can be handled are very general: the boundaries can be described by any rectilinear chains and the pins can be on the boundaries of the region or inside it, the obstructions can be of any shape and size. The technique is based on an algorithm that routes incrementally and intelligently the nets in the routing region and allows modifications and rip-up of nets that may impede the complete routing of other nets. The modification steps (also called weak modification) push some segments of nets already routed to make room for a blocked net. The rip-up and re-route steps (called strong modification), remove segments of nets already routed to make room for a blocked connection and is invoked only if weak modification fails. The algorithm is rigorously proven to complete in finite time and its complexity is analyzed. Many test cases have been run and on all the examples known in the literature the router has performed as well or better than existing algorithms. In particular, the Burstein's difficult switch box example has been routed using one less column than the original data. In addition, the router has routed difficult channels such as Deutsch's in density and has performed better than or as well as YACR-II in all the channels available to us. REFERENCES [Shir83] Shirakawa, I. and Futagami, S. "A Re-routing Scheme for Single-Layer Printed Wiring Boards" IEEE Trans. on CAD Vol. CAD-2, No. 4, pp 267 - 271, Oct 1983. [Lee61] Lee, C. Y. "An Algorithm for Path Connections and its Applications" IRE Trans. on Electronic Computers vol EC-10, pp 346 - 365, Sep. 1961. [Deut76] Deutsch, D. "A Dogleg Channel Router" Proc. 13th Design Automation Conf. pp 425 - 433, Jun 1976. [Yosh82] Yoshimura, T. and Kuh, E. "Efficient Algorithms for Channel Routing" IEEE Trans. on CAD, Vol. CAD-1, No. 1, pp 25 - 35, 1982. [Hsu82] Hsu, C. "A New Two-Dimensional Routing Algorithms" Proc. 19th Design Automation Conf. pp 46 - 50, Jun 1982. [Burs83] Burstein, M. and Pelavin, R. "Hierarchical Channel Router" Proc. 20th Design Automation Conf. pp 591 - 597, Jun 1983.

[Hama84] Hamachi, G. T. and Ousterhout, J. K. "A Switch-box Router with Obstacle Avoidance" Proc. 21nd Design Automation Conf. Jun 1984, pp 173 - 179. [Luk85] Luk, W. K. "A Greedy Switch-box Router" INTEGRATION, the VLSI journal 3, 1985, pp 129 149. [Joob85] Joobbani, R WEAVER: A Knowledge- Based Routing Expert" Research Report CMUCAD-8556, Carnegie-Mellon Univ. Jun 1985. [Mare 85] Marek-Sadowska, M. "Two-dimensional Router for Double Layer Layout" Proc. 22nd Design Automation Conf. Jun 1985, pp 117 - 123. [Hsie85] Hsieh, Y. and Chang, C. "A modified detour router" Proc. Int. Conf. on CAD, Nov 1985, pp 301 303. [Reed85] Reed, J., Sangiovanni-Vincentelli, A. and Santomauro, M. "A New Symbolic Channel Router: YACR2" IEEE Trans. on Computer-Aided Design, Vol. CAD-4, No, 3, Jul 1985, pp 208 - 219. [Brau86] Braun, D., Burns, J., Devadas, S., Ma, H., Mayaram, K., Romeo, F., and Sangiovanni-Vincentelli, A. "Chameleon: A New Multi-Layer Channel Router" Proc. 23rd Design Automation Conf. Jun 1986. [Ohts85] Ohtsuki, T., Tachibana, M. and Suzuki, K. "A Hardware Router with Rip-up and Re-route Support" Proc. Int. Conf. on CAD, pp 220 - 222, Nov 1985. [Laut 85] Lauther, U. "Channel Routing in A General Cell Environment" Proc. VLSI Conf., pp 389 - 399, 1985 [Sequ86] Sequin, C. "Design and Layout Generation at the Symbolic Level" In preparation, 1986.


The Scan Line Approach to Power and Ground Routing Xiao-Ming Xiong, Ernest S. Kuh Electronics Research Laboratory Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720

ABSTRACT We present a new approach to routing power and ground nets simultaneously by applying the scan line method. In contrast to other algorithms which maintain and process the information on the whole chip at all time, our algorithm only looks at the data on the scan-line for pursuing routing at each step. Thus our algorithm is very efficient in the aspect of complexity. As long as the power net and the ground net can be routed topologically on one layer, we will find a solution with time complexity O(nlogn) and space complexity O(n), where n is the number of blocks in the chip. References [1] Zahir A. Syed and Abbas El Gamal "Single Layer Routing of Power and Ground Networks in Integrated Circuits" Journal of Digital Systems, Volume VI, Number 1, Spring 1982, pp. 53-63. [2] Margeret Lie and Chi-Song Horng "A Bus Router For IC Layout" Proc. 19th Design Automation Conference, 1982, pp. 129-132. [3] H-J. Rothermel and D. A. Mlynski "Computation of Power Supply Nets in VLSI Layout" Proc. 18th Design Automation Conference, 1981, pp. 53-63. [4] Andrew S. Moulton "Laying The Power And Ground Wires On A VLSI Chip" Proc. 20th Design Automation Conference, 1983, pp. 754-755. [5] J. Nievergelt and F. P. Preparata "Plane-Sweep Algorithms for Intersecting Geometric Figures" Communications of the ACM, Volume 25, Number 10, October 1982, pp. 739-747. [6] X. M. Xiong "Nutcracker: An Intelligent Channel Spacer" University of California, Berkeley Technical Report, Electronics Research Laboratory memo \#M86/55, May 1986.


Test Methodology for a 32-Bit Processor Chip Patrick Bosshart, Thirumalai Sridhar Texas Instruments Incorporated, Dallas, Texas 75265

Abstract In this paper the overall test methodology for a 32-bit processor chip will be presented. Several novel design-for-test ideas have been implemented which address various phases of the product cycle such as engineering debug, manufacturing test, microcode development, system test, and system maintenance. The processor uses scan design, allowing automatic test pattern generation for detection of stuck faults. A special twopattern test mode allows detection of more difficult faults. A bond pad scan ring has been provided which can drive most input pins in order to allow low pin-count wafer probing. An on-chip ROM is provided to perform a self-test of the datapath and on-chip memories. During the self-test, test responses are compressed by two on-chip parallel signature analyzers. Extra capabilities have been added to the microinstructions to allow testing of the on-chip memories at full speed. The ROM self-test and the scan paths are used to test the processor embedded in a system, as well as to debug the system and the microcode. Finally, a powerful user interface for microcode development and chip debugging is presented, which allows direct inter-active control of a processor board or a chip at wafer-probe from the same interface used for simulation during chip design. References [1] J. Kuban and J. Salik "Testability features of the MC68020" Proc. 1984 Int'l Test Conf., pp. 821-826. [2] "Testing the Intel 80386" Private Communication. [3] S. M. Reddy et al. "On testable design for CMOS logic circuits" Proc. 1983 Int'l Test Conf., pp. 435445. [4] T. Sridhar, et al. "Analysis and simulation of parallel signature analyzers" Proc. 1982 Int'l Test Conf., pp. 656-661.


Efficient Testing of RISC Microprocessors Jim Tsen-Gong Hsu, Ruby Bei-Loh Lee, Gregory D. Burroughs Hewlett-Packard Laboratories, Palo Alto, California 94304

Abstract The complexity of a microprocessor, with its large number of embedded structures, presents a particular challenge to any single chip testing methodology. This paper compares test generation and test application methodologies in an effort to identify the more efficient methodologies for microprocessor structural testing. It is demonstrated that RISC architectures facilitate structural testing via the normal program execution. Experimental results on logic circuits and memory units illustrate the efficiency of the proposed methodology for both test vector generation and test application for a industrial RISC microprocessor. REFERENCES [1] J. RothM W. Bouricius and P. Schneider. Programmed Algorithms to compute tests to detect and distinguish between failures in logic circuits, IEEE Trans. on Elec. Comp., Oct. 1967. [2] H. Fujiwara and T. Shimono. On the acceleration of test generation algorithms, IEEE Trans. Comput., Dec. 1983. [3] J. Losq. Efficiency of random compact testing, IEEE Trans. Compu., June 1978. [4] E. McCluskey. Built-in Test Structures, Built-in Test - Theory and Implementations, 1984. [5] J. Kuban and J. Salick. Testing Approaches In the MC68020, VLSI DESIGN, Sept. 1984. [6] J. Healy. Automatic testing and evaluation of digital integrated circuits, Reston, Virginia: Prentice-Hall, 1981. [7] R. Lee, R. Wu and K.C. Chen. Testability design for the single-chip CMOS Spectrum, Proc. of 1986 VLSI Design Technology Conf., Hewlett-Packard Co., May 1986. [8] M. Williams and J. Angel. Enhancing testability of large scale integrated circuits via test points and additional logic, IEEE Trans. Comput., Jan. 1973.


Chipbuster VLSI Design System Bill McCalla, Beatriz Infante, Dennis Brzezinski, Joe Beyers Hewlett-Packard Company, Circuit Technology Group

1. A SYSTEM FOR VLSI DESIGN ChipBuster is an integrated, UNIX workstation-based IC design system. It provides a high degree of configurability which allows it to be customized to support a spectrum of integrated circuit design and process technologies. Currently, it is configured to support the design of CMOS VLSI full custom IC's as depicted by the following representative floorplan: ChipBuster was conceived and designed by tool developers and IC designers working together. This cooperative effort has resulted in an integrated circuit design system that recognizes the following: * Chips must be designed and represented hierarchically - there is simply too much data associated with a chip having over 500,000 transistors to be understood or designed "flat." * Design complexity management is best handled by a top-down definition, bottom-up implementation approach. * The design tools should complement and support the design methodologies - if cells are assembled hierarchically, they should be verified hierarchically. * Individual tools, no matter how powerful, are rarely useful unless well integrated into a system. The sheer complexity of VLSI problems makes moving from tool to tool more complicated and time-consuming than actually using the tool. * Integrated circuit design has evolved from a sequential to a parallel process. Multiple designers working simultaneously on a single chip necessitates proper management of shared libraries and concurrent access to designs.


Data Management and Graphics Editing in the Berkeley Design Environment David S. Harrison, Peter Moore, Rick L. Spickelmier, A. Richard Newton Electronics Research Laboratory, University of California, Berkeley, California 94720

Abstract The Oct data manager and the VEM graphics editor form the foundation for the integration of many the CAD tools being developed at Berkeley. Oct provides the means for building, modifying and searching circuit designs, and a uniform means of storage and retrieval of these designs. VEM acts as a graphics shell for viewing and editing Oct designs and invoking other CAD tools that manipulate, analyze, or optimize these designs. The current set of tools using Oct include compactors, module and array generators, logic synthesis tools, circuit simulators, a circuit critic, and placement and routing tools. VEM is designed to interface to all these tools, using the Oct data manager and using remote procedure calls. References [Apple85] Inside Macintosh, Apple Computer, Inc., Cupertino, Cal., 1985. [Bru86] T. Brunhoff "Design Considerations for Remote File Systems" Masters Report, Univ. of Denver, 1986. [Del86] T. Della Fera "XMenu - X Deck of Cards Meny System" Unix Manual Page, 1986. [DEC85] "DECnet-ULTRIX User's and Programmer's Guide" AA-EA88A-TE, Digital Equipment Corp., July 1985. [Edif85] EDIF - Electronic Design Interchange Format Version 1.0.0, EDIF Steering Committee, 1985. [GND86] J. Gettys, R. Newman and T. Della Fera. Xlib - C Language X Interface, Protocol Version 10, MIT, Cambridge, Mass., 1986. [Har86] D. S. Harrison "Masters Report" In preparation, Univ. of Cal., 1986. [Hil85] M. D. Hill "SPUR: A VLSI Multiprocessor Workstation" UCB/Computer Science Dpt. 86/273, Computer Science Div., Univ. of Cal., Dec 1985. [KAC86] R. H. Katz, M. Anwarrudin and E. Chang "A Version Server For Computer-Aided Design Data" Proceedings of the 23rd Design Automation Conf., Las Vegas, Nevada, June 1986, 27-33. [Kel84] K. H. Keller "An Electronic Circuit CAD Framework" M84/54, Electronics Research Lab., Univ. of Cal., July 1984. [Les84] M. E. Lesk "Tbl - A Program to Format Tables" UNIX User's Manual - Supplementary Documents, Bell Labs, 1984. [Tes81] L. Tesler "The SMALLTALK Environment" Byte, August 1981, 90-147. [Xerox82] Courier: The Remote Procedure Call Protocol, Xerox Corp., Stamford, Conn., February 1982.


A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells Andrea Casotto, Fabio Romeo, Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Science, University of California, Berkeley

ABSTRACT A modification of the classical Simulated Annealing algorithm for the Macro-Cell placement problem is proposed for implementation on multiprocessor systems. The algorithm has been implemented on the Sequent Balance 8000, a multiprocessor system with shared-memory architecture. Experimental results show that the new algorithm obtains results comparable to those of the single processor version; processor utilization is greater than 80% using up to 8 processors. REFERENCES [AAR85] E.H.L. Aarts, F.M.J. de Bont, J.H.A. Habers and P.J.M. van Laarhoven "A parallel statistical cooling algorithm" "Symposium on the Theoretical Aspects of Computer Science" (STACS 86), Paris, (Jan. 86). [KIR83] S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi. Optimization by Simulated Annealing, Science, Vol. 220, N. 4598, pp. 671-680, 13 May 1983. [KRA86] S.A. Kravitz "Multiprocessor-based placement by simulated annealing" Master's thesis, CMUCAD-86-6, Carnegie-Mellon University (Feb. 86). [SEC84] C. Sechen, A. Sangiovanni Vincentelli "The TimberWolf Placement and Routing Package" Proc. 1984 Custom Integrated Circuit Conference, Rochester, May 1984.


A Parallel Simulated Annealing Algorithm for Standard Cell Placement on a Hypercube Computer Prithviraj Banerjee, Mark Jones Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

ABSTRACT A parallel processing algorithm for standard cell placement suitable for execution on a Hypercube computer is presented. In the past, several parallel algorithms for performing module placement have been proposed that are suitable for execution on a twodimensional array of processors. Those algorithms had several limitations, namely, they got stuck at local minima, were susceptible to oscillations, could not handle variable sized modules (standard cells), and allowed only nearest neighbor exchanges. Recently, the simulated annealing technique has been applied to solve the standard cell placement problem on conventional uniprocessor computers. These algorithms do not get stuck at local minima and can handle modules of variable sizes, but take an extremely long time to be executed. In this paper, a parallel version of the simulated annealing technique is presented which is targeted to run on a Hypercube computer. We discuss how the cells in a two-dimensional area of a chip are mapped onto processors in an n-dimensional hypercube such that both small and large moves can be applied. Two types of moves are allowed: cell exchanges and cell displacements. The computation of the cost function in parallel among all the processors in the hypercube is described along with a distributed data structure that needs to be stored in the hypercube to support such a parallel cost evaluation. Initial estimates show that the algorithm is several orders of magnitude faster than existing simulated annealing-based algorithms running on conventional uniprocessors. REFERENCES [1] M. Hanan and J. M. Kurtzberg "Placement Techniques" in Design Automation of Digital Systems: Theory and Techniques, ed., M. A. Breuer. Prentice-Hall, pp. 213-282, 1972. [2] M. A. Breuer "Min-cut Placement" Jour. Design Automation and Fault Tolerant Computing, vol. 1, pp. 343-382, Oct. 1977. [3] D. J. Chyan and M. A. Breuer "A Placement Algorithm for Array Processors" Proc. 20th Design Automation Conf., pp. 182-188, Jun. 1983. [4] K. Ueda, T. Komatsubara, and T. Hosaka "A Parallel Module Placement Approach for Logic Module Placement" in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems. pp. 39-47, Jan. 1983. [5] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi "Optimization by Simulated Annealing" Science, vol. 220, pp. 671-680, May 1983. [6] C. Sechen and A. S. Vincentelli "The TimberWolf Placement and Routing Package" Proc. Custom Integrated Circuits Conf., pp. 522-527, May 1984.

[7] S. A. Kravitz and R. A. Rutenbar "Multiprocessor-Based Placement by Simulated Annealing" Proc. 23rd Design Automation Conf., pp. 567-573, Jun. 1986. [8] J. Tuazon, J. Peterson, M. Pniel, and D. Leberman, "Caltech/JPL Mark II Hybercube Concurrent Processor" Proc. 1985 Parallel Processing Conference, pp. 666-673, Aug. 1985. [9] J. C. Peterson, J. Tuazon, D. Lieberman, and M. Pniel "The Mark III Hypercube-Ensemble Concurrent Computer" Proc. 1985 Parallel Processing Conference, pp. 71-73, Aug. 1985. [10] Intel Scientific Computers "iPSC: The First Family of Concurrent Supercomputers" 1985, product announcement. [11] Ametek System 14 User's Guide C Edition Version 2.0. Ametek Computer Research Div., May 1986. [12] N. Deo in Graph Theory with Applications to Engineering and Computer Science, Englewoods Cliffs, N.J.: Prentice-Hall, Inc., 1974. [13] R. M. Fujimoto. Simon: A Simulator of Multicomputer Networks, Univ. of California, Berkeley, Sep. 1983. [14] J. S. Emer and D. W. Clark "A Characterization of Processor Performance in the VAX-11/780" Proc. 11th Int. Symp. on Computer Architecture, pp. 301-310, Jun. 1984.


Topological Optimization of Multiple Level Array Logic: On Uni and Multiprocessors Srinivas Devadas and A. Richard Newton Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720

Abstract: Algorithms for topological compaction are introduced which solve the problem of efficient automatic layout of multi-level CMOS and NMOS logic circuits. These technology independent algorithms operate on symbolic layouts in the form of Weinberger Arrays or Gate Matrices and minimize area by multiply folding the rows of the array/matrix using a simulated-annealing-based approach. Unlike previous techniques our approach provides for widely differing transistor sizes in the array/matrix. Constrained optimization problems are defined and solved both for the gate matrix and the Weinberger array cases. The simulated annealing based algorithms have been implemented on a Balance 8000 Sequent multiprocessor with modifications to fully exploit parallelism. Dynamic windowing and dynamic partitioning techniques have been used resulting in efficiences of upto 75% on eight processors. REFERENCES [asan82] T. Asano "An optimum gate placement algorithm for MOS one-dimensional arrays" Journal of Digital Systems, vol VI, no 1, 1982, pp 1-28. [cass86] A. Casotto, F. Romeo and A. Sangiovanni-Vincentelli "A multi-processor implementation of simulated annealing" ICCAD86 Digest. [deva86] S. Devadas and A.R. Newton "Genie: A Generalized Array Optimizer for VLSI Synthesis" 1986 Design Automation Conference, Las Vegas. [krav86] S. Kravitz and R. Rutenbar "Multi-processor based placement" 1986 Design Automation Conference, Las Vegas. [kirk83] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi "Optimization by Simulated Annealing" Science, Vol.220,N. 4598, pp 671-680, 13 May 1983 [lope81] A. D. Lopez and H-F S. Law "A dense gate matrix layout style for MOS VLSI" IEEE Trans. Electron Devices, pp 1671-1675 Aug. 1981 [mlyu85] M. L. Yu and W. J. Kubitz "A VLSI Cell Synthesiser with structural constraint considerations" ICCAD Digest 1985, pp 58-61. [ohts79] T. Ohtsuki, H. Mori, E. S. Kuh, T. Kashiwabara, and T. Fujisawa "One dimensional logic gate assignment and interval graphs" IEEE Trans. Circuits Syst, pp 675-684, Sept 1979. [rome85] F. Romeo, and A. Sangiovanni-Vincentelli "Probabilistic Hill Climbing Algorithms: Properties and Applications” 1985 Chapel Hill Conference on VLSI.

[sech85] C. Sechen and A. Sangiovanni-Vincentelli "The TimberWolf Placement and Routing Package" IEEE Journal of Circuits and Systems, April 1985. [wein67] A. Weinberger "Large Scale Integration of MOS Complex Logic: A Layout Method" IEEE Journal of Solid-State Circuits, vol SC-2, no 4, Dec 1967, pp 182-190. [wing82] O. Wing "Automated Gate Matrix Layout" Proc '82 IEEE Int. Symp. On Circ. and Sys. Rome, Italy, pp 681-685, 1982. [wing85] O. Wing, S. Huang, and R. Wang "Gate Matrix Layout" IEEE Transactions on Computer-Aided Design,Vol.CAD-4, No. 3, July 1985 [yosh75] H. Yoshizawa, H. Kawanishi, and K. Kani "A Heuristic procedure for ordering MOS arrays" Proc. 12th Design Automation Conference, 1975, pp 384-89


Fast, High Quality VLSI Placement on an MIMD Multiprocessor J.S. Rose, D.R. Blythe, W.M. Snelgrove, Z.G. Vranesic Departments of Electrical Engineering and Computer Science, University of Toronto, Toronto, Ontario, Canada

ABSTRACT We present two parallel algorithms that produce quality equivalent to the Simulated Annealing placement algorithm for Standard Cells [11]. The first creates parallelism by simulataneously investigating different areas of the combinatorial search space. The second technique replaces the low temperature phase of Simulated Annealing, in which the placement is divided geographically and different areas are assigned to separate processors. Each processor then generates Simulated Annealing-style moves for the cells in its area. References [1] D.R. Blythe "Master/Slave TUNIS: A Multiprocessor Operating System" M.Sc. Thesis, Department of Computer Science, University of Toronto, 1986. [2] M.A. Breuer "Min-Cut Placement" Journal of Design Automation and Fault-tolerant Computing, Oct 1977, pp. 343-362. [3] A.E. Dunlop, B.W. Kernighan "A Procedure for Placement of Standard-Cell VLSI Circuits" IEEE Transactions on CAD, Vol. CAD-4, No. 1, January 1985, pp. 92-98. [4] C.M. fiduccia, R.M. Matheyses "A Linear Time Heuristic for Improving Network Partitions" Proc. 19th Design Automation Conference, June 1982, pp. 175-181. [5] S. Goto "An Efficient Algorithm for the Two-Dimensional Placement Problem in Electrical Circuit Layout" IEEE Transactions on Circuits and Systems, Vol. CAS-28, No. 1, January 1981, pp. 12-18. [6] S. Kirkpatrick, C.D. Gelatt, Jr., M.P. Vecchi "Optimization by Simulated Annealing" Science, Vol. 220, No. 4598, May 13, 1983, pp. 671-680. [7] S.A. Kravitz "Multiprocessor-Based Placement by Simulated Annealing" SRC-CMU Centre for Computer Computer-Aided Design, Research Report No. CMUCAD-86-6. [8] S.A. Kravitz, R.A. Rutenbar "Multiprocessor-Based Placement by Simulated Annealing" Proc. 23rd Design Automation Conference, June 1986, pp. 567-573. [9] J.S. Rose, W.M. Snelgrove, Z.G. Vranesic "ALTOR: An Automatic Standard Cell Layout Program" Proc. Canadian Conference on VLSI, November 1985, pp. 168-173. [10] J.A. Rose "Fast, High Quality VLSI Placement on an MIMD Multiprocessor" Ph.D. Thesis, University of Toronto, in progress. [11] C. Sechen, A. Sangiovanni-Vincentelli "The Timberwolf Placement and Routing Package" IEEE JSSC, Vol. SC-20, No. 2, April 1985, pp. 510-522. [12] TIL Systems Limited, Toronto Ontario, ZP 1632 Processor Boards.


Fault Coverage of Pseudorandom Testing Kenneth Wagner, Cary Chin, Edward McCluskey CENTER FOR RELIABLE COMPUTING, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305

ABSTRACT Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a Linear Feedback Shift Register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile. We develop an exact expression and an approximation for the expected fault coverage of pseudorandom testing, a measure of test quality. The influence of each fault on the expected fault coverage can be evaluated. Relationships between fault coverage, fault detectability, and test length are examined. REFERENCES [1] Golomb, S. Shift Register Sequences, Revised Edition, Aegean Park Press, Laguna Hills, California, 1982. [2] Trivedi, K. Prob. & Stats. with Reliab., Queuing, & Comp. Sci. Appls., Prentice-Hall, New Jersey, 1982. [3] Shedletsky, J. "Random Testing: Practicality vs. Verified Effectiveness" Proc. 7th Int'l Conf. on F-T Computing, pp. 175-179, June 1977. [4] Chin, C. and E. McCluskey "Test Length for Pseudo Random Testing" Proc. Int'l Test Conf., pp. 94-99, Nov. 1985. [5] Malaiya, Y.K. and S. Yang "The Coverage Problem for Random Testing" Proc. Int'l Test Conf., pp. 237-245, Nov. 1984. [6] Savir, J., G. Ditlow and P. Bardell "Random Pattern Testability" Dig. of Papers, IEEE 13th Annual Int'l Symp. on F-T Computing, pp. 80-89, June 1983. [7] Brglez, F., P. Pownall and R. Hum "Accelerated ATPG and Fault Grading via Testability Analysis" Proc. Int'l Symp. on Ckts. and Sys., pp. 695-698, Japan, 1985. [8] McCluskey, E.J. Logic Design Principles, Prentice-Hall, New Jersey, 1986. [9] Wagner, K., C. Chin, and E. McCluskey "Pseudorandom Testing" Stanford University, Center for Reliable Computing, TR No. 86-6, June 1986. [10] Hughes, J. and E. McCluskey "Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets" Proc. Int'l Test Conf., Nov. 1986. [11] Savir, J. and P. Bardell "On Random Pattern Test Length" Proc. Int'l Test Conference, pp. 95-106, 1983.

[12] Chin, C. and E. McCluskey "Weighted Pattern Generation for Built-In Self Test" Stanford University, Center for Reliable Computing, TR No. 84-7, Aug. 1984. [13] Eichelberger, E. and E. Lindbloom "Random Pattern Coverage Enhancement for LSSD Logic SelfTest" IBM Jour. of R. and D., Vol. 27, pp. 265-272, May 1983.


Test Set Generation for Pseudo-Exhaustive BIST Jon G. Udell Jr. Center for Reliable Computing, Stanford University, Stanford, CA

ABSTRACT The problem of determining test sets for pseudo-exhaustive testing of combinational circuits is discussed. A method, based upon the subscripted D-algorithm (AALG), is presented that yields an exhaustive test set for a given segment of a circuit. This test set is simple enough that it can be easily generated in hardware, facilitating Built-In Self-Test (BIST). REFERENCES [1] Archambeau, E. C. "Fault Coverage of Pseudo-Exhaustive Testing" IEEE International Conference on Fault-Tolerant Computing, Orlando, FL, June 20-22, 1984. [2] Archambeau, E. C. "Network Segmentation for Pseudo-Exhaustive Testing" CRC Technical Report, No. 85-10, Stanford, CA, July 1985. [3] Benmehrez, C., and J. F. McDonald "The Subscripted D-Algorithm ATPG with Multiple Independent Control Paths" IEEE Automatic Test Program Generation Workshop, San Francisco, CA, March 15-16, 1983. [4] Benmehrez, C., and J. F. McDonald "Measured Performance of a Programmed Implementation of the Subscripted D-Algorithm" Proceedings of the 20th Design Automation Conference, pp. 308-315, 1983. [5] Goel, P. "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits" IEEE Transactions on Computers, vol C-30, pp. 215-222, March 1981. [6] McCluskey, E. J., and S. Bozorgui-Nesbat "Design for Autonomous Test" IEEE Transactions on Computers, vol C-30, pp. 866-875, November 1981. [7] McCluskey, E. J. "Verification Testing - A Pseudo-exhaustive Test Technique" Correspondence - IEEE Transactions on Computers, vol C-33, pp. 541-546, June 1984. [8] McCluskey, E. J. Logic Design Principles: With Emphasis on Testable Semi-Custom Circuits, PrenticeHall, Englewood Cliffs, NJ, 1986. [9] McDonald, J. F., and C. Benmehrez "Test Set Reduction using the Subscripted D-Algorithm" Proceedings of the 1983 International Test Conference, pp. 115-121, 1983. [10] Patashnik, O. "Circuit Segmentation for Pseudo-Exhaustive Testing" CRC Technical Report, No. 8314, Stanford, CA, October 1983. [11] Roberts, M. W., and P. K. Lala "An algorithm for the partitioning of logic circuits" IEE Proceedings, Vol. 131, Pt. E, No. 4, July 1984. [12] Roth, J. P. "Diagnosis of automata failures: A calculus & a method" IBM Journal of Research and Development, vol. 10, pp. 278-291, July 1966.


Complete Feedback Shift Register Design for Built-In Self-Test Laung-Terng Wang, Edward J. McCluskey CENTER FOR RELIABLE COMPUTING, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305 USA

ABSTRACT Linear feedback shift registers (LFSRs) are commonly used for built-in self-test. It is often necessary for the LFSR to cycle through the all-zero state. This paper presents a new, systematic design approach by which the all-zero state can be easily implemented in an LFSR. LFSRs configured for zero-state insertion, called complete feedback shift registers, can be used in a number of existing on-chip or on-board test pattern generators, such as maximum-length LFSRs, store address generators, LFSRs/shift registers, and LFSRs using linear codes and cyclic codes. REFERENCES [Akers85] Akers, S.B. 5th Int'l Symposium of Fault-Tolerant Computing (FTCS-15), pp. 148-153, June 1985. [Barzilai81] Barzilai, Z., J. Savir, G. Markowsky, and M.G. Smith IEEE Trans. on Computers (IEEETC), pp. 996-1000, Dec. 1981. [Barzilai83] Barzilai, Z., D. Coppersmith, and A. Rosenberg IEEETC, pp. 190-194, Feb. 1983. [Craig85] Craig, G.L., and C.R. Kime Proc. of IEEE 1985 Int'l Test Conference (ITC), pp. 126-137, Nov. 1985. [Golomb 82] Golomb, S.W. Shift Register Sequences, Revised Edition, Aegean Park Press, Laguna Hills, CA, 1982. [Hsiao77] Hsiao, M.Y., A.M. Patel, and D.K. Pradhan IEEE Trans. on Computers, Vol. c-26, No. 11, pp. 1144-1147, November 1977. [Konemann79] Konemann, B., J. Mucha, and G. Zwiehoff "Built-In Logic Block Observation Techniques" ITC, pp. 37-41, Oct. 1979. [McCluskey81] McCluskey, E.J., and S. Bozorgui-Nesbat IEEE Trans. on Circuits and Systems, pp. 10701079, Nov. 1981. [McCluskey84] McCluskey, E.J. "A Survey of Design For Testability Scan Techniques" VLSI Design, pp. 38-61, Dec. 1984. [McCluskey85a] McCluskey, E.J. "Built-In Self-Test Techniques" IEEE Design & Test of Computers, pp. 21-28, April 1985. [McCluskey85b] McCluskey, E.J. "Built-In Self-Test Structures" IEEE Design & Test of Computers, pp. 29-36, April 1985. [McCluskey86] McCluskey, E.J. Logic Design Principles, Prentice-Hall, Englewood Cliffs, NJ, 1986.

[Peterson72] Peterson, W.W., and E.J. Weldon, Jr. Error Correcting Codes, 2nd edition, M.I.T. Press, Massachusetts, 1972. [Scholefield60] Scholefield, P. "Shift Registers Generating Maximum-Length Sequences" Electronic Tech., pp. 389-394, Oct. 1960. [Tang84] Tang, D.T., and C.L. Chen "Logic Test Pattern Generation Using Linear Codes" IEEETC, pp. 845-850, June 1984. [Vasanthavada85] Vasanthavada, N., and P.N. Marinos ITC, pp. 476-482, Nov. 1985. [Wagner86] Wagner, K., C. Chin, and E.J. McCluskey IEEE 4th Int'l Conf. on Computer-Aided Design. Nov. 1986, see this issue. [Wang 85] Wang, L.-T., and E.J. McCluskey Proc. of IEEE 1985 Int'l Symp. on Circuits and Systems (ISCAS-85), pp. 1305-1308, 1985. [Wang86a] Wang, L.-T., and E.J. McCluskey "Concurrent Built-In Logic Block Observer (CBILBO)" SCAS-86, pp. 1054-1057, May 1986. [Wang86b] Wang, L.-T., and E.J. McCluskey "A Hybrid Design of Maximum-Length Sequence Generators" ITC, Sept. 1986. [Wang86c] Wang, L.-T., and E.J. McCluskey IEEETC, pp. 367-370, April 1986. [Wang86d] Wang, L.-T., and E.J. McCluskey "Circuits for Pseudo-Exhaustive Test Pattern Generation" ITC, Sept. 1986. [Wang86e] Wang, L.-T., and E.J. McCluskey "Complete Feedback Shift Register Design For Built-In SelfTest" CRC Technical Report, Stanford Univ., 1986, to be published.


Test Control Signal Distribution in Self-Testing VLSI Circuits Jerzy Kalinowki, Alexander Albicki, James Beausang The University of Rochester, Department of Electrical Engineering, Rochester, N.Y. 14627

Abstract In this paper techniques which reduce the area overhead associated with test control line distribution in self-testing VLSI circuits are proposed. Two schemes for distributing test control signals from the test controller to the BIST (Built-In Self-Test) modules are investigated: parallel distribution and serial distribution. There is a trade-off between the area required for test control line distribution and that consumed by local controllers which can be incorporated into the BIST modules. This trade-off is discussed and enumerated based upon implemented circuits and heuristics. References [1] B. Konemann, J. Mucha and G. Zwiehoff "Built-In Logic Block Observation Technique" Proc. IEEE International Test Conference, pp. 34-41, October 1979. [2] J. Beausang and A. Albicki "Toward Determining an Optimal Test Control Line Distribution Scheme for a Self-Testable Chip" Technical Report EL-86-02, The University of Rochester, Dept. of Electrical Engineering, February 1986. [3] A. Albicki and J. Kalinowski "Distribution of Control Signals in Self-Testing Designs" Technical Report EL-86-02, The University of Rochester, Dept. of Electrical Engineering, February 1986.1. V.D. Agraval, S.K. Jain and D.M. Singer, “A CAD System for Design for Testability”, VLSI Design, pp.46-54, October 1984. [4] C.R. Kime and K.K. Saluja "Test Scheduling in Testable VLSI Circuits" Proc. 12-th International Symposium on Fault-Tolerant Computing, pp. 406-412, 1982. [5] M.S. Abadir and M.A. Breuer "Test Schedules for VLSI Circuits Having Built-In Test Hardware" IEEE Transactions on Computers, Vol C-35, No. 4, pp. 361-367, April 1986.


Optimal Chaining of CMOS Transistors in a Functional Cell Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman IBM Israel Scientific Center, Technion City Haifa 32 000 ISRAEL

Abstract We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, highperformance layout in the style of a transistor chain. This algorithm is intended for the generation of basic cells in a custom or semi-custom design environment. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. Such an algorithm can serve as the basis for a powerful cell generation tool that will take the burden of arduous mask definition off the designer's back. REFERENCES [1] Uehara T., and W. M. vanCleemput. Optimal Layout of CMOS Functional Arrays, IEEE Transactions on Computers C-30, 5 (May 1981), 305-312. [2] Nair, R., A. Bruss, and J. Reif. Linear Time Algorithms for Optimal CMOS Layout, VLSI: Algorithms and Architectures, P. Bertolazzi and F. Luccio (Eds), Elsevier (North-Holland), 1985, 327-338. [3] Hill D. Sc2 - a Hybrid Automatic Layout System, Proceedings of the ICCAD, 1985, 172-174. [4] Mavor J., M. A. Jack, and P.B. Denyer. Introduction to MOS LSI Design, Addison-Wesley, 1983. [5] Fiebrich R.-D., Y.-Z. Liao, G. Koppelman, and E. N. Adams. PSI - a Symbolic Layout System, IBM Journal of Research and Development 28, 5 (September 1984), 572-580. [6] Liao, Y. Z., and C. K. Wong. An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints, Proceedings of the Twentieth Design Automation Conference, June 1983, 107-112. [7] Bron C., and J. Kerbosch. Algorithm 457 - Finding all Cliques of an Undirected Graph, Communications of the ACM 16 (1973). [8] Rivest, R. L., and C. M. Fiduccia, A "Greedy" Channel Router, Proceedings of the Nineteeth Design Automation Conference, June 1982, 418-424.


Characterization of an Automatic Random Logic Layout Synthesizer Meng-Lin Yu AT&T Bell Laboratories, Crawfords Corner Road Holmdel, NJ 07733

William J. Kubitz Department of Computer Science, University of Illinois at Urbana-Champaign

Abstract In this paper, a sequence of experiments with an automatic random logic layout synthesizer, designed for a silicon compilation environment, using a one-dimensional synthesis approach with structural constraints [YuKu85a] [YuKu85b] and their results are described. Data about deformability, aspect ratio, and their relationship with partitioning, data about effects of imposing I/O constraints to cells on cell area and routing area, and device density data with respect to different input sizes are shown and discussed. The experiments are not exhaustive but are designed to illustrate the key behavior of the synthesizer and the nature of random logic layout. The effectiveness of imposing relative I/O ordering constraints is supported by the experimental data. Routing area reduction usually more than compensates for the cell area penalty. Smaller than quadratic area growth rate for cell synthesis has been observed. Experience suggests that this approach is a viable and promising one for VLSI layout synthesis. Our experiments also suggest that there are hyperbola-like deformability curves, which exist for manual cell designs [Ance83], existing for an automatic random logic layout synthesizer and that a wide range of aspect ratios can be expected and utilized by the floor-planner. References [Ance83] F. Anceau. Layout Strategies for NMOS-CMOS VLSI, Proceedings of International Conference on Computer Design, October 1983, pp. 705-708. [Breu79] M.A. Breuer. Min-Cut Placement, Design Automation & Fault-Tolerant Computing, pp. 343-362. [BrFu85] F. Brglez, H. Fujiwara. A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran, Proceedings of 1985 IEEE International Symposium on Circuits and Systems, June 1985. [DuKe85] A.E. Dunlop, and B.W. Kernighan. A Procedure for Placement of Standard-Cell VLSI Circuits, IEEE Transactions on CAD, Vol. CAD-4, No. 1, January 1985, pp. 92-98. [Feue82] M. Feuer. Connectivity of Random Logic, IEEE Transactions on Computers, Vol. C-31, No. 1, January 1982, pp. 29-33. [Law83] H.F. Law. Gate Matrix: A Practical, Stylized Approach to Symbolic Layout, VLSI Design, September 1983, pp. 49-59. [Wein67] A. Weinberger. Large Scale Integration of MOS Complex Logic: A Layout Method, IEEE JSSC, Vol. SC-2, No.4, April 1967, pp.182-190.

[YuKu85a] M-L. Yu, W.J. Kubitz. A VLSI Cell Synthesizer with Structural Constraint Considerations, Digest of IEEE ICCAD, 1985, pp.58-60. [YuKu85b] M-L. Yu, W.J. Kubitz. Linear-Time Heuristics for Cell Layout Synthesis Under Constraints, Digest of IEEE ICCAD, 1985, pp.64-66. [Yu86] M-L. Yu. Automatic Random Logic Layout Synthesis - A Module Generator Approach, University of Illinois at Urbana-Champaign, Department of Computer Science, Report UIUCDCS-R-86-1244, Ph.D Thesis, 1986.


Mocha Chip: A System for the Graphical Design of VLSI Module Generators Robert N. Mayo Computer Science Division of EECS, University of California, Berkeley, CA 94720

ABSTRACT Mocha Chip is a tool for designing module generators. Unlike most such tools, Mocha Chip allows module generators to be designed by drawing a diagram of the structure of the module, rather than by writing code. Because of this, Mocha Chip is easy to learn, and generators designed with Mocha Chip are easy to understand and modify. References [1] R. Mayo and J. Ousterhout. Pictures with Parentheses: Combining Graphics and Procedures in a VLSI Layout Tool, Proc. 20th Design Automation Conference, 1983, pp. 270-276. [2] C. Bamji, C. Hauck and J. Allen. A Design by Example Regular Structure Generator, Proc. 22nd Design Automation Conference, 1985, pp. 16-22. [3] H. Law and J. Mosby. An Intelligent Composition Tool for Regular and Semi-Regular VLSI Structures, IEEE International Conference on Computer Aided Design, 1985, pp. 169-171.

1986 ICCAD, Pages 78-81 3

C : A System and Methodology for the Development of Module Generators William Kao, David Tsou, Daniel Chi, Mohammad Movahed-Ezazi Xerox Corporation, El Segundo, CA 90245

Abstract This paper describes the C3 (Compiler-Compiler in C) system and methodology that enables the development of module generators and silicon compilers. The procedural layout language XL2 (Xerox Layout Language) is used to describe VLSI circuits. The C3 system is composed of two compilers. The XL2 compiler that translates an XL2 source file containing cell constructs into intermediate C source code, and a C compiler that compiles the intermediate C source code to generate an object file. Technology data containing layout design rules and other processing information are given in a separate file making the generators technology independent. Outputs of the module generators will be layouts in either GDSII or CIF formats. A couple of application examples are included. References [1] S. Law and J. Mosby "An Intelligent Composition Tool for Regular and Semi-regular VLSI Structures" ICCAD, San Jose, 1985, pp. 169-171. [2] K. Chu and R. Sharma "A Technology Independent MOS Multiplier Generator" Proceedings of the 21st Design Automation, Albuquerque, NM, 1984, pp. 90-97. [3] M. W. Stebnisky, M.J. McGinnis, J. C. Werbickas, R. N. Putatunda, and A. Feller "A Fully Automatic, Technology Independent PLA Macrocell Generator" Proceedings of International Conference on Circuits and Computers, Sept. 1982, pp. 156-161. [4] P. Powell and M. Elmasry "The ICEWATER Language and Interpreter" Proceedings of the 21st Design Automation Conference, Albuquerque, NM, 1984, pp. 98-102. [5] C. Yeung and F. Mavaddat "Procedural Cell Design, Placement, and Routing for VLSI Design Automation" VLSI SYSTEM DESIGN, Sept. 1985, pp. 122-125. [6] R. Lipton, S. C. North, R. Sedgewick, J. Valdes, G. Vijayan "ALI: a Procedural language to describe VLSI Layouts" Proceedings of the 19th Design Automation Conference, Las Vegas, 1982, pp. 467-474. [7] W. Cory "Layla: A VLSI Layout Language" Proceedings of the 22nd Design Automation Conference, Las Vegas, 1985, pp. 245-251. [8] N. H. E. Weste and K. Eshraghian. Principles of CMOS VLSI Design, Addison-Wesley, Reading, MA.


The Segmented Waveform Relaxation Method for Mixed-Mode Switch Electrical Simulation of Digital MOS VLSI Circuits and its Hardware Acceleration on Parallel Computers D. Dumlugol, P. Odent, J. Cockx, H. De Man. IMEC, Kapeldreef 75, B-3030 Heverlee, Belgium

Abstract In this paper first an overview is given of the Segmented Waveform Relaxation Method (SWRM) for electrical simulation of digital MOS VLSI circuits. SWRM is a new waveform relaxation (WR) method which provides a rigorous solution to the problem of feedback loops in digital MOS networks leading to logically correct and accurate startwaveforms after the first WR iteration. Tests on large circuits (up to 4k transistors) with SWRM implemented in the program SWAN reveal speedup of 20..50 for startwaveforms and 10..20 for relaxed waveforms over the direct method in SWAN. Mixed-mode switch-electrical simulation in SWAN and new algorithms to increase parallelism for hardware acceleration on parallel computers are described together with test results. References [1] E. Lelarasmee et al. "The waveform relaxation method for time domain analysis of large scale integrated circuits" IEEE Trans. on CAD of IC and Syst., Vol. 1, n.3, pp.131-145, July 1982. [2] D. Dumlugol et al. "Segmented Waveform Relaxation algorithms for large scale circuit simulation" Proceedings of ISCAS 85, pp.1069-1072, Japan, 1985. [3] J. White et al. "Accelerating relaxation algorithms for circuit simulation using waveform newton, iterative step size refinement and parallel techniques" [4] R. Tarjan "Depth-first search and linear graph algorithms" SIAMJ. Comput. Vol. 1, N.2, June 1972. [5] D. Dumlugol et al. "Local relaxation algorithms for event driven simulation of MOS networks including assignable delay modeling" IEEE Trans. on CAD of IC and Syst., Vol. 2, n. 3, pp.193-202, July 1983.


Block Time-Point Relaxation Algorithms for Circuit Simulation M.P. Desai, I.N. Hajj Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign

ABSTRACT In this paper we study the convergence properties of block time-point relaxation methods when applied to the simulation of VLSI circuits. Two relaxation methods are considered: SOR-Newton and Newton-SOR. It is shown that, under certain assumptions, a sufficient condition for convergence is the existence of capacitors to ground at the external nodes of each subcircuit, provided the time-step is sufficiently small. We then compare the application of these methods to two partitioning strategies: the bordered-block-diagonal form (BBDF) and the nearly-lower-block-triangular form (NLBT). Our computational results show that these partitioning strategies offer similar speeds of convergence. REFERENCES [1] A.R. Newton and A.L. Sangovianni-Vincentelli " Relaxation-based electrical simulation" IEEE Trans. on El. Dev., no. 9, pp.1186-1207, September 1983. [2] E. Lelarasmee, A. E. Ruehli, and A. L. Sangovianni-Vincentelli "The waveform relaxation method for time-domain analysis of large scale integrated circuits" IEEE Trans. on computer-Aided Design of Integrated Circuits and Systems vol. CAD-1, no.3, pp. 131-144, July 1982. [3] J.M. Ortega and W.C. Rheinboldt "Iterative solution of nonlinear equations in several variables" Academic Press 1970. [4] I.N. Hajj "Sparsity considerations in network solution by tearing" IEEE Trans. on Circuits and Systems, vol. CAS-27, no. 5, pp.357-366, May 1980. [5] G. De Micheli, H. Y. Hsieh, and I.N. Hajj "Decomposition techniques for large scale circuit simulation" in Circuit Analysis, Design and Simulation, A. Ruehli. Ed., North-Holland Pub. Co., New York, 1986. [6] R. Saleh, J. E. Kleckner, A. R. Newton "Iterated timing analysis in SPLICE1" Proceedings, ICCAD, pp. 139-140, 1983. [7] M.P. Desai "Parallel algorithms for circuit simulation" M.S. Thesis, Univ. of Illinois at UrbanaChampaign, August 1986.


Techniques for Using SPICE Sensitivity Computations in DELIGHT.SPICE Optimization Bill Nye Epsilon Active Inc. and Department of EECS, University of California, Berkeley.

Abstract We discuss the mechanics of how circuit sensitivities are used in a circuit optimization program that handles complex performance specifications. In particular, the use of computed SPICE voltage sensitivities … to obtain the (simplified) gradient … necessary for optimization is discussed. A typical operational amplifier problem description is used to illustrate the key difficulties. These include the treatment of track (matched) parameters, and of the particularly nasty phase margin and offset voltage specifications. We illustrate how the computation of phase margin can be generalized to include many commonly occurring switching time, as well as other specifications. The paper closes with a few suggestions for gaining additional efficiency. REFERENCES [1] S. W. Director and R. A. Rohrer "The Generalized Adjoint Network and Network Sensitivities" IEEE Transactions Circuit Theory vol. CT-16, pp. 318-323 (1969). [2] G. D. Hachtel and R. A. Rohrer "Techniques for the Optimal Design and Synthesis of Switching Circuits" Proc. IEEE, no. 55, pp. 1864-1877 (1967). [3] D. E. Hocevar, P. Yang, T. N. Trick, and B. D. Epler "Transient Sensitivity Computation for MOSFET Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems vol. CAD-4, no.4, pp. 609-620 (October 1985). [4] E. Lelarasmee and A. L. Sangiovanni-Vincentelli "Time Domain Sensitivity Computation by the Perturbation Method" University of California, Berkeley (1981). [5] W. T. Nye and D. C. Riley "Transient Sensitivity in SPICE" EECS 290H course project report, Department of Electrical Engineering and Computer Science, University of California, Berkeley, California (June 1982). [6] W. T. Nye DELIGHT: An Interactive System for Optimization-Based Engineering Design, Ph.D. Thesis, Department of EECS, University of California, Berkeley, California (1983). [7] W. T. Nye, A. Sangiovanni-Vincentelli, J. P. Spoto, and A. L. Tits "DELIGHT.SPICE: An Optimization-Based System for the Design of Integrated Circuits" Proceedings of the 1983 Custom Integrated Circuits Conference, pp. 233-238 (May 1983). [8] W. T. Nye, D. C. Riley, and A. Sangiovanni-Vincentelli "DELIGHT.SPICE User's Guide" Department of Electrical Engineering and Computer Science, University of California, Berkeley, California (February 1983). [9] W. T. Nye and Engineering Computations Group "DELIGHT.SLICE User's Guide" Harris Semiconductor, Melbourne, Florida (1986).

[10] W. T. Nye, D. Riley, A. Sangiovanni-Vincentelli, and A. L. Tits "DELIGHT.SPICE: An OptimizationBased System for the Design of Integrated Circuits" submitted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1986). [11] W. T. Nye and A. L. Tits "An Application-Oriented, Optimization-Based Methodology for Interactive Design of Engineering Systems" International Journal of Control vol. 43, no. 6, pp. 1693-1721 (1986).


An Approach to Design Automation for Highly Testable Logic Circuits Terumine Hayashi, Kazumi Hatayama, Yoshio Kunitomo, Shigeo Kuboki Hitachi Research Laboratory, Hitachi, Ltd., 4026 Kujicho, Hitachi, Ibaraki 319-12, JAPAN

ABSTRACT Scan structures are effective for improving the testability of sequential circuits and simplifying test data generation. However, most logic designers who are not expertized, could not utilize such approaches because of complicated logic design rules for scanning. This paper presents a design automation ( DA ) technique by which logic designers can design highly testable logic circuits with no difficulty by utilizing a scan structure. The technique converts a sequential circuit which is designed without any testability consideration to a circuit with the Scan Bus structure. The technique can be applied for both clocked sequential circuits and asynchronous circuits. Moreover, most logic design rules for scaning are satisfied in the converted circuit, even though they are not satisfied in the original circuit. The design automation system using the above technique can generate both highly testable logic circuits and test data with high fault coverage. REFERENCES [1] E. B. Eichelberger and T. W. Williams "A Logic Design Structure for LSI Testability" Proc. 14th DA Conf., 462-468, 1977. [2] S. Funatsu, N. Wakatsuki and T. Arima "Test Generation Systems in Japan" Proc. 12th DA Conf., 114122, 1974. [3] H. Ando "Testing VLSI with Random Access Scan" Digest COMPCON 1980, 50-52, 1980. [4] M. R. Mercer, V. D. Agrawal and C. M. Roman "Test Generation for Highly Sequential Scan-Testable Circuits through Logic Transformation" Proc. 1981 Test Conf., 561-565, 1981. [5] V. D. Agrawal, S. K. Jain and D. M. Singer "A CAD System for Design for Testability" VLSI Design, Vol. 5, No. 10, 46-54, 1984. [6] T. Masui, F. Niimi and M. Iwase "A New Approach to Design for Testability in an LSI Logic Synthsis System" ICCAD-85, 105-107, 1985. [7] K. Chen "On-Chip Testability Circuit for CMOS Gate Arrays" VLSI Design, Vol. 7, No. 1, 48-50, 1986. [8] P. P. Fasang, J. P. Shen, M. A. Schuette and W. A. Gwaltney "Automated Design for Testability of Semicustom Integrated Circuits" Proc 1985 Test Conf., 558-564, 1985. [9] S. Kuboki, I. Masuda, T. Hayashi and S. Torii "A 4K CMOS Gate Array with Automatically-Generated Test Circuits" Proc. 1985 ISSCC, 128-129, 1985. [10] J. P. Roth "Diagnosis of Automata Failures : A Calculus and a Method" IBM J. of Res. and Dev., Vol. 10, 278-291, 1966.

[11] H. Fujiwara and T. Shimono "On the Acceleration of Test Generation Algorithms" IEEE Trans. on Comput., Vol. C-32, 1137-1144, 1983.


Automatic Test Generation for Sequential Circuits with Irregular Scan Structure Kazumi Hatayama, Terumine Hayashi Hitachi Research Laboratory, Hitachi, Ltd., 4026 Kujicho, Hitachi, Ibaraki 319-12, JAPAN

Kaoru Moriwaki Kanagawa Works, Hitachi, Ltd., 1 Horiyamashita, Hatano, Kanagawa 259-13, JAPAN

Shigeru Suzuki Odawara Works, Hitachi, Ltd. 2880 Kouzu, Odawara, Kanagawa 256, JAPAN

Masahiro Takakura Hitachi Engineering Co., Ltd. 3-2-1 Saiwaicho, Hitachi, Ibaraki 317, JAPAN

ABSTRACT The concept of design for testability (DFT) is necessary for the design of large-scale logic circuits. This paper presents an efficient test generation procedure for sequential circuits with an irreguler scan structure. For such circuits, the scan-in and scan-out patterns cannot be derived from the scan structure of the circuit automatically, due to the irregularity of the scan structure. Therefore, it is necessary to generate not only test patterns for combinational circuit part but also scan patterns for these circuits. However conventional test generation algorithms for sequential circuits do not always assure high fault coverage because they cannot distinguish scan circuit parts from functional circuit parts. On the contrary, the procedure manages well the above two circuit parts by dividing the process into four stages and generates test data with high fault coverage. Experimental results show the effectiveness of the test generation procedure. REFERENCES [1] E. B. Eichelberger and T. W. Williams "A Logic Design Structure for LSI Testability" Proc. 14th DA Conf., 462-468, 1977. [2] S. Funatsu, N. Wakatsuki and T. Arima "Test Generation Systems in Japan" Proc. 12th DA Conf., 114122, 1974. [3] H. Ando "Testing VLSI with Random Access Scan" Digest COMPCON 1980, 50-52, 1980. [4] S. Goshima, T. Kozawa, Y. Oka, T. Mori, Y. Takeguchi and Y. Ohno "Diagnostic System for Large Scale Logic Cards and LSI's" Proc. 18th DA Conf., 256-259, 1981. [5] J. P. Roth "Diagnosis of Automata Failures : A Calculus and a Method" IBM J. of Res. and Dev., Vol. 10, 278-291, 1966. [6] P. Goel "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits" IEEE Trans. on Comput., Vol. C-30, 215-222, 1981. [7] H. Fujiwara and T. Shimono "On the Acceleration of Test Generation Algorithms" IEEE Trans. on Comput., Vol. C-32, 1137-1144, 1983.


A Hierarchical Logical Design Rule Check Program for Scan Design Circuit K. Muroi, M. Kitta T. Ogihara, S. Murai Mitsubishi Electric Corporation, 5-1-1 Ofuna Kamakura Kanagawa , JAPAN

ABSTRACT This paper describes a design rule check program for large scale scan design circuits which adopts new symbolic simulation technique. The program has several features as follows. First it can check a very large scale circuit such as a CPU of a computer. Second if a circuit is designed hierarchically, the program checks the circuit both in the top down and the bottom up manners. Sub-modules mounted on the circuit under test, say LSI's on a PCA, can be treated as black boxes. Third the logical design rules consist of the rules for testability and for the normal operation. The program checks the both rules. Fourth it can check topological violations that could hardly be detected by logic simulation method. Fifth it has a good user interface. For instance, we devised interface signal names so that they express the information for checking as well as identifications. REFERENCES [1] Godoy, H.C., G.B. Franklin and P.S. Bottorff "Automated Checking of Logic Design Structure for Compliance with Testability Ground Rules" proc. 14th DA Conference, pp 469-478 [2] Bhavsar, D.K. "DESIGN FOR TEST CALCULUS: AN ALGORITHM FORDFT RULES CHECKING" proc. 20th DA Conference, pp 300-307 [3] Eichelberger, E.B. and T.W. Williams "A Logic Design Structure for LSI Testing" proc. 14th DA Conference, pp 462-468 [4] Funatsu, S., et al. "Design Digital Circuits with Easily Testable Considerations" 1978 Test Conference [5] Ogihara, T., et al. "TEST GENERATION FOR SCAN DESIGN CIRCUITS WITH TRI-STATE MODULES AND BIDIRECTIONAL TERMINALS" proc. 20th DA Conference, pp 71-78 [6] Horstmann, P.W. and E.P. Stabler "Computer Aided Design Using Logic Programming" 1984 DA Conference, pp 144-151 [7] Kyushik Son "RULE BASED TESTABILITY CHECKED AND TEST GENERATION" 1985 Test Conference, pp 884-88


Behavioral Synthesis with Interfaces J. A. Nestor, D. E. Thomas Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, Pennsylvania 15213

Abstract This paper describes new techniques for the specification and synthesis of synchronous digital systems with interfaces. A method of describing behavior with interfaces has been developed that ties structure, behavior, and timing specifications together. Now tools have been added to an existing synthesis system to generate designs which meet the extended specifications. These tools include a scheduler that determines the sequence of operations in the implementation while taking timing constraints into account, and an interface binder that creates the hardware necessary for the interface. An example specification is presented along with the design that results from applying the new tools to the example. References [1] D. E. Thomas, C. Y. Hitchcock, T. J. Kowalski, J. V. Rajan and R. Walker. "Automatic Data Path Synthesis". In IEEE Computer, Dec. 1983. [2] E. F. Girczyc and J. P. Knight. "An ADA to Standard Cell Hardware Compiler Based on Graph Grammars and Scheduling". In Proc. ICCD. 1984. [3] R. Camposano. "Synthesis Techniques for Digital Systems Design". In Proc. ICCD. 1984. [4] A. C. Parker, J. Pizarro, and M. Milnar. "MAHA : A Program for Data Path Synthesis". In Proc. DAC. 1986. [5] P. G. Paulin, J. P. Knight, and E. F. Girczyc. "HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis". In Proc. DAC. 1986. [6] M. R. Barbacci. "Instruction Set Processor Specification (ISPS): The Notation and its Applications". In IEEE Trans. Computers. Jan., 1981. [7] Intel Corporation "Intel Multibus Specification". 1981. [8] J. Vasantharajan. Design and Implementation of a VT-Based Multi-Level Representation. MS Thesis, Carnegie-Mellon Univ. 1982. [9] E. F. Girczyc, R. J. Buhr, and J. P. Knight. "Applicability of a Subset of ADA for Graph-Based Hardware Compilation. In IEEE Trans. CAD. April 1985. [10] S. Davidson, D. Landskov, B. D. Shriver and P. W. Mallett. "Some Experiments in Local Microcode Compaction for Horizontal Machines". In IEEE Trans. Computers. July 1981. [11] C. J. Tseng. Automated Synthesis of Data Paths in Digital Systems. PhD. Thesis, Carnegie-Mellon Univ. 1984.

[12] J. A. Fisher. "Trace Scheduling: A Technique for Global Microcode Compaction". In IEEE Trans. Computers. July 1981.


Evaluation of Behavior Description Based CAD System Used in Prolog Machine Design Kiyoshi Oguri, Yukihiro Nakamura, Ryo Nomura Electrical Communication Laboratories, NTT, 1-2356 Take Yokosuka Kanagawa JAPAN

Abstract This paper describes how a Register Transfer Level (RTL) CAD system was used for the logic design of a PROLOG machine (Advanced Inference Machine (AIM)). The CAD system consisting of a behavioral structured function description language (SFL), behavior simulator (SFLSIM), and hardware expander (SFLEXP) is evaluated based on the design results. AIM is a dedicated one-chip PROLOG interpreter provided with several mainframe acceleration mechanisms, including advance control, automatically progressing control, pipeline control, and interleaved multi-bank storages control. AIM operates at 130KLIPS, which is the highest level of processing power yet achieved, and is 18,213 gates in size. Work involved in its design took only 7.8 man-months using the CAD system. References [1] Y. Nakamura, K. Oguri, H. Nakanishi, and R. Nomura, "An RTL Behavioral Description based Logic Design CAD System with Synthesis Capability" Proc. of the 7th International Conference on Comprter Hardware Description Languages and their Applications, 1985, pp. 64-78. [2] Y. Nakamura, Y. Sakata, K. Oguri, H. Nakanishi, and R. Nomura "A Behavioral Description Based Logic Design System with Synthesis Capability" Monograph of Technical Group on Systems and Circuit of Inst. Electron. Commun, Eng. Japan, CAS 84-136, 1984. [3] S. Takagi "Design Method based Logic Synthesis" Proc. of the 7th International Conference on Comprter Hardware Description Languages and their Applications, 1985, pp. 49-63. [4] T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama, K. Ishihara "POLARIS: Polarity propagation Algorithm for Combination Logic Synthesis" Proc. of 21th DAC, 1984, pp. 322-328.


Functional Language Extractor and Boolean Cover Generator D.L. Ravenscroft, M.R. Lightner Department of Electrical and Computer Engineering, University of Colorado, Boulder, CO 80309

Abstract Initial results in developing a functional language extractor used as the front end of the VLSI design synthesis system being developed at the University of Colorado are presented in this paper. Functional models are described using an embedded hardware description language based on the C programming language. From this description, the extractor produces a complete multi-level boolean cover with all output ON and don't care conditions defined. Flow graph techniques are used during the syntactic and semantic parsing of the functional description of a model to detect and partition sequential logic and to produce the multi-level boolean cover of the model. As a result the extractor acts as a key element of our silicon compiler by bridging the synthesis gap between functional specification and testing of a system and the logic level synthesis, optimization, and physical configuration of the system. References [AH74] Aho, Alfred V., John E. Hopcroft, and Jeffrey D. Ullman. The Design and Analysis of Computer Algorithms, Addison-Wesley Publishing Company, Reading, MA (1974). [AM85] Amsbury, Wayne. Data Structures From Arrays to Priority Queues, Wadsworth Publishing Company, Belmont, CA (1985). [BA85] Bartlett, K., W. Cohen, A. J. de Geus, and G. D. Hachtel "Synthesis and Optimization of Multilevel Logic under Timing Constraints" IEEE International Conference on Computer-Aided Design, pp. 290-292 (Nov 1985). [BR84] Brayton, Robert K., Gary D. Hachtel, Curtis T. McMullen, and Alberto L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, boston (1984). [BY84] Bye, C. T., M. R. Lightner, and D. L. Ravenscroft, "A Functional Modeling and Simulation Environment based on ESIM and C" IEEE International Conference on Computer-Aided Design, pp. 51-53 (Nov 1984). [CA85] Camposano, Raul "Synthesis Techniques for Digital Systems Design" 22nd Design Automation Conference, pp. 475-481 (1985). [FO85] Fowler, C., G. Hachtel, and L. Roybal "New Algorithms for Hierarchical Place and Route of Custom VLSI" IEEE International Conference on Computer-Aided Design, pp. 273-275 (Nov 1985). [FR84] Frey, Ernest J. "ESIM: A Functional Level Simulation Tool" IEEE International Conference on Computer-Aided Design, pp. 48-50 (Nov 1984). [LI85] Lightner, M. R., P. H. Moceyunas, B. L. Vellandi, and H. P. Vellandi "CSIM: The Evolution of a Behavioral Level Simulator from a Functional Simulator: Implementation Issues and Performance Measurements" IEEE International Conference on Computer-Aided Design, pp. 350-351 (Nov. 1985).

[TA83] Tarjan, Robert Endre. Data Structures and Network Algorithms, Society for Industrial Applied Mathematics, Philiadelphia (1983).


Timing Analysis Using Functional Relationships Daniel Brand, Vijay S. Iyengar IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598, USA

Abstract The usual block oriented timing analysis for logic circuits does not take into account functional relations between signals. If we take functional relations into consideration we may find that a long path is never activated. This observation can be used to calculate improved and more accurate delays. It is not practical to consider the complete truth table with all the relationships between signals. We use a procedure that considers only a subset of the relationships between signals and checks for non-functional paths. The delay calculation then takes into account the discovered non-functional paths to determine less pessimistic delays through the logic. References [1] R.B. Hitchcock, Sr., G.L. Smith, D.D. Cheng "Timing Analysis of Computer Hardware" IBM Journal of Research and Development January 1982, 100-105. [2] M.A. Breuer and A.D. Friedman. Diagnosis and Reliable Design of Digital Systems, Computer Science Press, Inc., 1976. [3] D. Brand, V.S. Iyengar "Timing Analysis Using Functional Analysis" IBM Research Report, No. RC 11768, March 1986. [4] D. Brand "Redundancy and Don't cares in Logic Synthesis" IEEE Transactions on Computers, Vol. C32, No. 10, October 1983. [5] J.A. Darringer, D. Brand, J.V. Gerbi, W.H. Joyner, Jr., L. Trevillyan "LSS: A system for Production Logic Synthesis" IBM Journal of research and Development, Vol. 28, No. 5, September 1984. [6] CMOS Macrocell Manual AR50-000001-20 B, LSI Inc. [7] Special session on "Recent Algorithms for Gate-level ATPG with Fault Simulation and Their Performance Assessment" at International Symposium on Circuits and Systems, June 1985.


LEADOUT: A Static Timing Analyzer for MOS Circuits Thomas G. Szymanski AT&T Bell Laboratories, Murray Hill, New Jersey 07974

Abstract. LEADOUT is a prototype system for static timing analysis of synchronous MOS circuits. It has two novel features. One is that it correctly handles multi-phase clocking disciplines with a minimum of user intervention. In particular, circuits with levelsensitive latches are treated accurately even when signals stream through the latches in mid-phase. The second novelty is that LEADOUT compiles the essential timing properties of a circuit into a system of equations that can be solved rapidly and repeatedly with different values for such independent variables as the clock period, phase durations, transistor sizes, parasitics, and process parameters. Each solution yields such information as the identity of critical paths and late outputs. Evaluation times for a typical 75,000 transistor circuit with a four phase clock are under a minute on a VAX 780 and only a few seconds on a Cray XMP. LEADOUT thus provides a means for interactively optimizing circuit performance. References. [1] V. D. Agrawal "Synchronous Path Analysis in MOS Circuit Simulator" Proc. of the 19th Design Automation Conference, pp.629-635 (1982). [2] H. K. Al-Hussein "Path-Delay Computation Algorithms for VLSI Systems" VLSI Design, pp. 86-91 (February 1985). [3] L. C. Bening, T. A. Lane, and J. E. Smith "Developments in logic Network Path Delay Analysis" Proc. of the 19th Design Automation Conference, pp. 605-615 (1982). [4] E. Chan "Development of a Timing Analysis Program for Multiple Clocked Network" Proc. of the 22th Design Automation Conference, pp. 816-819 (1985). [5] J. P. Fishburn and A. E. Dunlop "TILOS: A Posynomial Programming Approach to Transistor Sizing" IEEE Inter. Conf. on Computer-Aided Design, pp. 326-328 (November, 1985). [6] R. B. Hitchcock "Timing Verification and the Timing Analysis Program" Proc. of the 19th Design Automation Conference, pp. 594-604 (1982). [7] N. P. Jouppi "TV: An NMOS Timing Analyzer" Proc. of 3rd Caltech Conf. on VLSI, pp. 72-85 (1983). [8] A. Kolodny, R. Friedman, and T. Ben-Tzur "Rule-Based Static Debugger and Simulation Compiler for VLSI Schematics" IEEE Inter. Conf. on Computer-Aided Design, pp. 150-152 (November, 1985). [9] T. M. McWilliams "Verification of Timing Constraints on Large Digital Systems" Journal of Digital Systems V(4), pp. 401-427 (1981).

[10] J. K. Ousterhout "A Switch-level Timing Verifier for Digital MOS VLSI" IEEE Trans. on ComputerAided Design CAD-4(3), pp. 336-349 (July, 1985). [11] T. Sasaki, A. Yamada, T. Aoyama, K. Hasegawa, and S. Kato "Hierarchical Design Verification for Large Digital Systems" Proc. of the 18th Design Automation Conference, pp. 105-112 (1981). [12] R. E. Tarjan "Depth First Search and Linear Graph Algorithms" SIAM J. Computing 1(2), pp. 146-160 (1975). [13] D. E. Wallace and C. H. Sequein "Plug-in Timing Models For an Abstract Timing Verifier" Proc. of the 23rd Design Automation Conference, pp. 683-689 (1986).


New Techniques for Statistical Timing Simulation Jacques Benkoski, Andrzej J. Strojwas Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

Abstract This paper describes a new approach to true statistical timing simulation. A methodology based on circuit partitioning and characterization of the resulting blocks as a function of the input slope, output capacitance, and the process parameters which influence performance has been developed. Using a nominal event-driven timing simulation as a front-end, we have successfully obtained meaningful statistical timing results. A software tool has been implemented, and both nominal and statistical simulation results are presented. References [1] James H. Shelly and David R. Tryon. Statistical Techniques of Timing Verification. In 20th Design Automation Conference. 1983. [2] S. R. Nassif, A. J. Strojwas and S. Director. FABRICS-II: A statistically based IC fabrication process simulator. IEEE Transactions on Computer-Aided Design CAD-3, 1984. [3] Young Hwan Kim. ELOGIC: A Relaxation-Based Switch-Level Simulation Technique. Master's thesis, U.C. Berkeley, 1985. ERL Memorandum No. M86/2. [4] L. M. Vidigal, S. R. Nassif and S. W. Director. CINNAMON: Coupled Integration and Nodal Analysis of MOs Networks. In 23rd Design Automation Conference. 1986.


Performance-Oriented Synthesis in the Yorktown Silicon Compiler Giovanni De Micheli IBM - T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract We present some algorithms for the optimization of the switching-time performances of synchronous systems designed by the Yorktown Silicon Compiler. Circuit performance is related to the worst-case propagation delay of signals between two register boundaries and the optimization of circuit performance is equivalent to the minimization of the critical path delay through combinational circuits. We consider here a global approach to timing performance optimization which involves operations at the logic, topological and physical level of description of the circuit. We assume that the combinational portion of the circuit being designed is described at the logic level as an interconnection of gates implementing single-output logic functions. This description may be transformed, by a procedure called logic re-synthesis, by modifying the internal structure of the logic gates and their interconnection to minimize the propagation delay of those signals limiting the performance of the circuit. At the topological level, we perform a timing-oriented re-positioning of groups of logic gates to reduce the delay on the wires along the critical paths. At the physical design level, we perform re-sizing of the driver gate sizes to improve the switching speed. These operations are interlaced with the synthesis steps of the Yorktown Silicon Compiler and can be seen as the "code optimizer" part of the compiler that may be invoked when compiling circuits with critical timing performances. The algorithms are described as well as their implementation and the interface to the Yorktown Silicon Compiler. The results of applying timing-performance optimization to a 32-bit microprocessor design are reported. REFERENCES [BRAY84b] R.Brayton, G.D.Hachtel, C.McMullen and A.L.Sangiovanni- Vincentelli "Logic Minimization Algorithms for VLSI Synthesis" Kluwer Academic Publishers, 1984. [BRAY84c] R.Brayton and C.McMullen "Synthesis and Optimization of Logic Circuits" Int. Conf. on Circ. and Comp. Des., Rye, NY, pp. 23-28, Sep 1984. [BRAY85a] R.Brayton, N.Brenner, C.Chen, G.De Micheli, C.McMullen and R. Otten "The Yorktown Silicon Compiler" Proc. Int. Symp. on Circuit and Systems, Kioto, Japan, pp. 391-394, Jun 1985. [BRAY85c] R.Brayton, C.Chen, G.De Micheli, J.Katzenelson C.McMullen R. Otten and R.Rudell "A Microprocessor Design Using the Yorktown Silicon Compiler" Proc. Int. Conf. on Circuit and Comput. Des., Rye, N.Y., pp. 225-230, Oct 1985. [BURS85] M.Burstein and M.Youssef "Timing Influenced Layout Design" Proc. 22th Des. Autom Conf. pp. 124-130, Las Vegas, Jun 85.

[CHEN84a] C.L.Chen and R.Otten "Considerations for Implementing CMOS Processors" Int. Conf. on Circ. and Comp. Des., Rye, NY, pp. 48-53, Sep 1984. [CHEN85] C.L.Chen Private Communication. [FISH85] J.Fishburn and A.Dunlop "TILOS: A Posynomial Programming Approach to Transistor Sizing" Int. Conf. on Comp. Aid. Des., Santa Clara, pp. 326-328, Nov. 1985. [HITC82] R.Hitchcock, G.Smith and D.Cheng "Timing Analysis of Computer Hardware" IBM Journal of Research and Development, Vol. 26, No.1 pp. 100-105, Jan. 1982. [HONG74] S.J.Hong,R.G.Cain and D.L.Ostapko "MINI: a Heuristic Approach for Logic Minimization" IBM Jour. of Res. and Dev., vol. 18, pp. 443-458, Sep. 1974. [KIRK83] S.Kirkpatric, D.Gelatt and M. Vecchi "Optimization by Simulated Annealing" Science, May 1983. [JOUP83] N.Jouppi "TV: an nMOS Timing Analyzer" in R.Bryant, Editor Third Caltech Conference on VLSI, Computer Science Press, 1983. [LEIS83] C.Leiserson, F.Rose and J.Saxe "Optimizing Synchronous Circuitry by Retiming" in R.Bryant, Editor Third Caltech Conference on VLSI, Computer Science Press, 1983. [LUIS76] J.Luisi "High-speed low-cost clock-controlled CMOS logic implementation" U.S. Patent 3982138, Sept 21, 1976. [OTTE84] R.Otten and L. Van Ginneken "Stepwise Layout Refinement" Int. Conf. on Circ. and Comp. Des., Rye, NY, pp. 30-36, Sep 1984. [OUST85] J.Ousterhout "A Switch-Level Timing Verifier for Digital MOS VLSI" IEEE Trans. on CAD/ICAS, Vol. CAD-4, No 3, pp. 336-348, July 1985. [RUEH77a] A.E. Ruehli P.K. Wolff Sr. and G.Goertzel "Analytical power/timing optimization technique for digital systems" Proc. 14th Des. Autom Conf. [TRIM85] S.Trimberger "Automated Performance Optimization of Custom Integrated Circuits" in A.Sangiovanni, Editor Advances in Computer-Aided Engineering Design, Jai Press, 1985.


Testability-Driven Random Pattern Generation Robert Lisanke, Aart de Geus, David Gregory GE - Calma Company, One Micron Drive Research Triangle Park, NC 27709

Franc Brglez BNR, P. O. Box 13478 Research Triangle Park, NC 27709

Abstract This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from non-uniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage. References [1] ISCAS-85 Benchmarks "Special Session: Recent algorithms for gate-level ATPG with fault simulation and their performance assessment" Proc. 1985 IEEE Int. Symp. Circuits and Systems, June 1985. [2] J. L. Carter, S. F. Dennis, V. S. Iyengar, B. K. Rosen "ATPG via random pattern simulation" Proc. 1985 IEEE Int. Symp. Circuits and Systems, June 1985, pp. 683-686. [3] H. D. Schnurmann, E. Lindbloom, R. G. Carpenter "The weighted random test-pattern generator" Trans. Comp., Vol. C-24 July 1975, pp. 695-700. [4] K. P. Parker "Adaptive Random Test Generation" Journal of Design Automation and Fault-Tolerant Computing, Oct. 1976, pp. 62 - 83. [5] P. Agrawal, V. D. Agrawal "On Monte Carlo testing of logic tree networks" IEEE Transactions on Computers, Vol. C-25 June 1976, pp. 664-667. [6] H. Wunderlich "PROTEST: A Tool For Probabilistic Testability Analysis" ACM IEEE 22nd Design Automation Conference Proceedings, 1985, pp. 204 - 211. [7] K. P. Parker and E. J. McCluskey "Probabilistic Treatment of General Combinational Networks" IEEE Trans. on Computing, June 1975, pp. 668-670. [8] F. Brglez "On testability analysis of combinational networks" Proc. 1984 IEEE Int. Symp. Circuits and Systems, May 1984, pp. 221-225. [9] V. Agrawal, S. Seth "Probabilistic Testability" Proceedings of the International Converence on Computer Design, October 1985. [10] J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, T. McCarthy "Fault Simulation for Structured VLSI" VLSI System Design, Vol. VI December 1985, pp. 20-32. [11] V. D. Agrawal "When to use random testing" IEEE Transactions on Computers, Vol. C-27 November 1978, pp. 1054-1055.

[12] G. R. Walsh. Methods of Optimization, John Wiley & Sons, 1975.


On Delay Fault Testing in Logic Circuits C.J. Lin, S.M. Reddy Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa 52242

ABSTRACT Correct operation of a logic circuit requires propagation delays of all paths in the circuit be smaller than the intended "clock interval". Random or deterministic tests, conducted at the normal clocking rate, can be used to insure that path delays in manufactured circuits meet the specifications. Algorithms, based on a four valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect path delay faults are proposed. The results can be used to determine the test length for a desired confidence level in testing a path fault, and to evaluate the testability of a given network when random tests are used. REFERENCES [1] E.P. Hseih et al. "Delay Test Generation" Proc. 14th Design Automation Conf., June 1977, pp. 486-491. [2] J.P. Lesser and J.J. Shedletsky "An Experimental Delay Test Generator for LSI Logic" IEEE TC, March 1980, pp. 235-248. [3] R.B. Hitchcock, G.L. Smith and D.D. Cheng "Timing Analysis of Computer Hardware" IBM J. Research and Development, Vol. 26, No. 1, Jan. 1982, pp. 100-105. [4] Z. Brazilai and B.K. Rosen "Comparison of AC Self-Testing Procedures" Proc. 1983 Int'l. Test Conf., Oct. 1983, pp. 89-94. [5] Y.K. Malaiya and R. Narayanaswamy "Testing for Timing Faults in Synchronous Sequential Integrated Circuits" Proc. 1983 Int'l. Test Conf., Oct. 1983, pp. 560-571. [6] T. Hayashi et al. "A Delay Test Generator for Logic LSI" Proc. 14th Int'l. Fault-Tolerant Computing, June 1984, pp. 146-149. [7] K.D. Wagner "The Error Latency of Delay Faults in Combinational and Sequential Circuits" Proc. 1985 Int'l. Conf., Nov. 1985, pp. 334-341. [8] G.L. Smith "Model for Delay Faults Based Upon Paths" Proc. 1985 Int'l. Sonf., Nov. 1985, pp. 342349. [9] J. Savir and W.H. McAnney "Random Pattern Testability of Delay Faults" ITC 1986. [10] K.D. Wagner "Delay Testing of Digital Circuits Using Pseudorandom Input Sequences" Center for Reliable Computing Report 85-12, revised March 1986, Stanford University. [11] E.J. McCluskey "Logic Design Principles" Prentice Hall, 1986. [12] S.C. Seth, B.B. Bhattacharya and V.D. Agrawal "An Exact Analysis for Efficient Computation of Random-pattern Testability in Combinational Circuits" Proc. 16th Int'l. Fault Tolerant Computing, July 1986, pp. 318-323.

[13] J.P. Roth "Diagnosis of Automata Failures - A Calculus and a Method," IBM J. Research and Development, Vol. 10, No. 4, July 1966, pp. 278-291. [14] P. Goel "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits" IEEE TC, Vol. C-30, No. 3, March 1981, pp. 215-222.


An Automatic Test Pattern Generation Algorithm for PLAs John Salick, Bill Underwood, John Kuban Motorola, Inc.

M. Ray Mercer U. of Texas

This paper describes a new algorithm implemented to automatically generate tests for PLAs. The currently assumed fault model is the standard set of all single stuck-atzero/one faults. The algorithm generates tests with reasonable run times—even for large PLAs. Test pattern compaction is done during test generation so that the total number of test patterns is relatively small, and as many inputs as possible are left unspecified. REFERENCES [BA82] P. Bose and J. A., Abraham "Test Generation for Programmable Logic Arrays" Proceedings of the 19th Design Automation Conference, Las Vegas, NV, 1982, pp. 574-580. [C78] C. W. Cha "A Testing Strategy For PLAs" Proceedings of the 15th Design Automation Conference, Las Vegas, NV, June, 1978, pp. 83-89. [EL80] E. B. Eichelberger and E. Lindbloom "A Heuristic Test-Pattern Generator for Programmable Logic Arrays" IBM Journal of Research and Development, Vol. 24, January, 1980, pp. 15-22. [G81] P. Goel "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits" IEEE Transactions on Computers, Vol. C-30, March, 1981, pp. 215-222. [HO79] S. J. Hong and D. L. Ostapko "Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)" IEEE Transactions on Computers, vol. C-28, Sept., 1979, pp. 617-626. [S79] J. E. Smith "Detection Of Faults in Programmable Logic Arrays" IEEE Transactions on Computers, vol. C-28, Nov., 1979, pp. 845-853. [SGMP84] F. Somenzi, S. Gai, M. Mezzalama, and P. Prinetto "PART: Programmable Array Testing Based On A Partitioning Algorithm" IEEE Transactions on CAD, vol. CAD-3, April, 1984, pp. 142-149. [SMU85] J. Salick, M. R. Mercer, and B. Underwood "Built-In Self Test Input Generator for Programmable Logic Arrays" Proceedings of IEEE International Test Conference, Philadelphia, PA, 1985, pp. 115-125. [WS85] R.-S. Wei and A. Sangiovanni-Vincentelli "PLATYPUS: A PLA Test Pattern Generation Tool" Proceedings of the 22nd Design Automation Conference, Las Vegas, NV, 1985, pp. 197-203.


A Parallel Scheme for Test-Pattern Generation Akira Motohara, Kenji Nishimura Matsushita Electric Industrial Co., Ltd., Osaka 570 Japan

Hideo Fujiwara Meiji University, Kawasaki 214 Japan

Isao Shirakawa Osaka University, Osaka 545 Japan

ABSTRACT An approach to the parallel processing for generating test-patterns for combinational circuits is described. In general, difficulty in the test-pattern generation lies in the two points; how to deal with a large number of faults, and what to do with the fault that is hard to generate test-pattern and that leads to cause a great number of backtracks. Our new test-pattern generation system, consisting of a test-pattern generation algorithm and a fault simulation, is capable of parallel processing and has resulted in the improvement of those difficulties. In order to confirm its performance, we implemented the proposed method on a multimicrocomputer system and applied it to the combinational circuits with 1,000 gates or less. It is our conclusion that the proposed approach to the parallel processing is effective to obtain a good fault coverage within a short period of time as compared with the conventional method run on the general purpose von-Neumann computers. REFERENCES [1] H. Fujiwara and S. Toida "The complexity of fault detection problems for combinational logic circuits" IEEE Trans. on Comp., Vol. C-31, No. 6, pp.555-560, June 1982. [2] G. A. Kramer "Employing massive parallelism in digital ATPG algorithm" Proc. Int. Test Conf., pp. 108-114, Oct. 1983. [3] H. Nishimura, H. Ohno, T. Kawata, I. Shirakawa and K. Ohmura "LINKS-1: A parallel pipelined multimicrocomputer system for image creation" 10th Int. Symp. on Computer Architecture, pp. 387-394, June 1983. [4] P. Goel "An implicit enumeration algorithm to generate tests for combinational logic circuits" IEEE Trans. on Comp., Vol. C-30, No. 3, pp. 215-222, March 1981. [5] H. Fujiwara and T. Shimono "On the acceleration for test generation algorithms" IEEE Trans. on Comp., Vol. C-32, No. 12, pp. 1137-1144, Dec. 1983. [6] E. G. Ulrich and T. Backer "The concurrent simulation of nearly identical digital networks" Proc. 10th Design Automation Workshop, pp. 25-27, June 1973.


A Rule-Base and Algorithmic Approach for Logic Synthesis Takeshi Yoshimura, Satoshi Goto C & C Systems Research Laboratories, NEC Corporation, 4-1-1 Miyazaki, Miyamae-ku Kawasaki 213, JAPAN

Abstract This paper presents a logic synthesis system based on a combined approach of rule-base and algorithm, where not only tables for transformation are described as rules, but also a logic minimization is registered as one of the rules. These rules are applied by a rule interpreter. Physical constraints such as longest path lengths between registers, fan-in/out and polarity are checked whenever each rule is applied. Experimental results show that the system generates solutions very close to the manual implementation, and a logic minimization algorithm reduces the circuit size by 20%. Reference [1] T. J. Kowalski and D. E. Thomas "The VLSI Design Automation Assistant: Prototype System" Proc. of the 20th Design Automation Conference, 1983, pp 479-483. [2] J. A. Darringer, W. H. Joyner, C. L. Berman and L. Trevillyan "Logic Synthesis Through Local Transformations" IBM J. Res. Develop., Vol. 25, No. 4, 1981, pp 272-280. [3] J. Dussault, C. C. Liaw and M. M. Tong "A High Level Synthesis Tool for MOS Chip Design" Proc. of the 21st Design Automation Conference, 1984, pp 308-314. [4] T. Shinsha, T. Kubo, M. Hikosaka, K. Akiyama and K. Ishihara "POLARIS: Polarity Propagation Algorithm for Combinational Logic Synthesis" Proc. of the 21st Design Automation Conference, 1984, pp 322-329. [5] T. Sasaki, A. Yamada, S. Kato, T. Nakajima, K. Tomita and N. Nomizu ""MIXS": A Mixed Level Simulator for Large Digital System Logic Verification" Proc. of 17th Design Automation Conference, 1980, pp 626-633 [6] J. R. Duley and D. L. Dietmeyer "Translation of a DDL Digital System Specification to Boolean Equations" IEEE TC Vol. C-18, April 1969. [7] Y. Chu "An ALGOL-like Computer Design Language” Communications ACM, Act, 1965. [8] D. W. Brown "A State Machine Synthesizer - SMS" Proc. of the 18th Design Automation Conference, 1981, pp 301-305.


Rule Based Logical Synthesis for Silicon Compilers G. Saucier, S. Hanriat Laboratoire "Circuits et Systemes" – IMAG, 46, Avenue F. Viallet - 38031 Grenoble cedex France

ABSTRACT A rule based system allowing flexible synthesis of boolean functions for different implementations and efficient controller design is presented.


Matching a Parts Library in a Silicon Compiler Mark Kahrs AT&T Bell Laboratories, 600 Mountain Avenue Murray Hill, NJ 07974 U.S.A.

Abstract This paper reports on a graph matching algorithm used in a silicon compiler for Very High Level Languages. The matching algorithm is used to find library modules to implement the functions of the data flow graph. Bibliography [1] L. Monier and J. Vuillemin. Using Silicon Assemblers, VLSI-85, Tokyo, Japan, Aug. 1985, 309-318. [2] D. Persky, D. N. Deutsch and D. G. Schweikert, LTX -- A Minicomputer-Based System For Automated LSI Layout, Journal of Design Automation and Fault-Tolerant Computing 1, 3 (May 1977), 217-255. [3] R. Rivest, The PI (Placement and Interconnect) System, DA19, Mar. 1982. (Also MIT memo 82-74). [4] M. W. Kahrs. Silicon Compilation of Very High Level Languages, PhD thesis, University of Rochester, October 1983. [5] R. E. Tarjan. Depth first searching of graphs, SIAM Journal of Computing 1, 2 (1972). [6] R. G. G. Cattell. Formalization and Automatic Derivation of Code Generators, Tech. Rep. 78-115, PhD thesis, CMU, Apr. 1978 (Also published by UMI Press). [7] M. Ganapathi, C. N. Fischer and J. L. Hennessey. Table-driven Code Generation, Computing Surveys 14, 4 (Dec. 1982), 573-592.


Analogical Reasoning for Digital System Synthesis Ramon D. Acosta, Michael N. Huhns, Shiuh-li Liuh Microelectronics and Computer Technology Corporation, 9430 Research Blvd. Austin, Texas 78759

Abstract Knowledge-based expert systems are being integrated into a variety of VLSI computeraided design tools. Unfortunately, the static and predetermined capabilities of most of these systems do not allow them to acquire design experience for future use. To overcome this limitation, a digital synthesis system based on analogical reasoning principles has been developed. It is capable of remembering past design experience and employing this accumulated experience in solving new problems. This approach results in a system that acts as an intelligent design assistant because of its ability to improve in both design capabilities and performance through its use. The system refines VHDL behavioral specifications into structural modules by building hierarchical design trees. This refinement is accomplished by executing plans composed of partially ordered rule sets. The current system has rules for designing circuits comprised of elementary digital components including transistors, logic gates, and inverter loop memory cells. Some of the reasoning and learning techniques being employed include formulation of design plans and their preconditions, abstraction of plans, and transformation of plans to analogous design problems. References [1] H. Brown, C. Tong, and G. Foyster "Palladio: An Exploratory Environment for Circuit Design" Computer, Vol. 16, No. 12, December 1983, pp. 41-56. [2] J.G. Carbonell "Derivational Analogy: A Theory of Reconstructive Problem Solving and Expertise Acquisition" in Machine Learning: An Artificial Intelligence Approach, Vol. II, R.S. Michalski, J.G. Carbonell, and T.M. Mitchell, Eds., Morgan Kaufmann, Los Altos, CA, 1986, pp. 371-392. [3] R.E. Fikes, P. Hart, and N.J. Nilsson "Learning and Executing Generalized Robot Plans" Artificial Intelligence, Vol. 3, 1972, pp. 251-288. [4] R.E. Fikes and N.J. Nilsson "STRIPS: A New Approach to the Application of Theorem Proving to Problem Solving" Artificial Intelligence, Vol. 2, 1971, pp. 189-208. [5] P.E. Friedland and Y. Iwasaki "The Concept and Implementation of Skeletal Plans" Journal of Automated Reasoning, Vol. 1, 1985, pp. 161-208. [6] IEEE Design & Test of Computers, Special Issue on VHDL: The VHSIC Hardware Description Language Vol. 3, No. 2, April 1986. [7] V.E. Kelly "The CRITTER System - Automated Critiquing of Digital Circuit Designs" Proceedings of the 21st Design Automation Conference, June 1984, pp. 419-425. [8] J. Kim and J. McDermott "Computer Aids for IC Design" IEEE Software, Vol. 3, No. 2, March 1986, pp. 38-47.

[9] A. Kolodny, R. Friedman, and T. Ben-Tzur "Rule-Based Static Debugger and Simulation Compiler for VLSI Schematics" Proceedings of the IEEE International Conference on Computer-Aided Design, 1985, pp. 150-152. [10] T.J. Kowalski. An Artificial Intelligence Approach to VLSI Design, Kluwer Academic Publishers, Boston, Massachusetts, 1985. [11] R.S. Michalski, J.G. Carbonell, and T.M. Mitchell, Eds. Machine Learning: An Artificial Intelligence Approach, Vol. I, Tioga, Palo Alto, California, 1983. [12] R.S. Michalski, J.G. Carbonell, and T.M. Mitchell, Eds. Machine Learning: An Artificial Intelligence Approach, Vol. II, Morgan Kaufmann, Los Altos, California, 1986. [13] T.M. Mitchell, R.M. Keller, and S.T. Kedar-Cabelli "Explanation-Based Generalization - A Unifying View" Technical Report ML-TR-2, Laboratory for Computer Science Research, Rutgers University, August 1985. [14] T.M. Mitchell, S. Mahadevan, and L.I. Steinberg "LEAP: A Learning Apprentice for VLSI Design" Proceedings of the 9th International Joint Conference on Artificial Intelligence, August 1985, pp. 573-580. [15] T.M. Mitchell, L.I. Steinberg, and J.S. Shulman "A Knowledge-Based Approach to Design" IEEE Transaction on Pattern Analysis and Machine Intelligence, Vol. PAMI-7, No. 5, September 1985, pp. 502510. [16] P.S. Rosenbloom, J.E. Laird, J. McDermott, A. Newell, and E. Orciuch "R1-Soar: An Experiment in Knowledge-Intensive Programming in a Problem-Solving Architecture" IEEE Transactions on Pattern Analysis and Machine Intelligence, Vol. PAMI-7, No. 5, September 1985, pp. 561-569. [17] E.D. Sacerdoti "Planning in an Hierarchy of Abstraction Spaces" Artificial Intelligence, Vol. 5, No. 2, 1974, pp. 115-135. [18] E. Simoudis and S. Fickas "The Application of Knowledge-Based Design Techniques to Circuit Design" Proceedings of the IEEE International Conference on Computer-Aided Design, 1985, pp. 213-215. [19] N. Singh "MARS: A Multiple Abstraction Rule-Based Simulator" Memo No. HPP-83-43, Stanford Heuristic Programming Project, December 1983. [20] "VHDL Language Reference Manual Version 7.2" Intermetrics Report IR-MD-045-2, August 1985. [21] P.H. Winston "Learning and Reasoning by Analogy" Communications of the ACM, Vol. 23, No. 12, December 1980, pp. 689-703.


A Parallel Solution Method for Large Sparse Systems of Equations Robert Lucas, Tom Blank, Jerome Tiemann Integrated Circuits Laboratory, Stanford University, Stanford, CA 94305

Abstract This paper presents a new distributed multifrontal sparse Gaussian elimination algorithm suitable for message passing parallel processors. The algorithm uses a nested dissection ordering and a multifrontal distribution of the matrix to minimize interprocessor data dependencies. It thus overcomes the communication bottleneck reported for general sparse solvers [1]. The implementation uses key routines of the Stanford PISCES program [2] so as to yield a practical engineering solution to the critical computational bottleneck now facing IC device designers. References [1] Alan George, et al. "Sparse Cholesky Factorization on a Local Memory Multiprocessor" Tech. Report ORNL-TM-6190, Mathematical Sciences Section, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (1985) [2] Mark. R. Pinto, Connor S. Rafferty, and Robert W. Dutton "PISCES-II: Poisson and Continuity Equation Solver" Stanford Electronics Laboratory, Tech. Report, Sept. 1984 [3] Connor S. Rafferty, Mark R. Pinto, and Robert W. Dutton "Iterative Methods in Semiconductor Device Analysis" IEEE Transactions on Compouter Aided Design, Vol. CAD4, No. 4, Oct. 1985, pp.462-471 [4] George Jacob, et. al. "Direct-Method Circuit Simulation Using Multiprocessors" IEEE International Symposium on Circuits and Systems, 1986, pp. 170-174 [5] Iain S. Duff and J. K. Reid "The Multifrontal Solution of Indefinite Sparse Symmetric Linear Equations" ACM Transactions on Mathematical Software, Vol. 9, No. 3, Sept. 1983, pp. 302-325 [6] George A. Giest and Michael T. Heath "Parallel Cholesky Factorization on a Hypercube Multiprocessor" Tech. Report ORNL/TM-9962, Mathematical Sciences Section, Oak Ridge National Laboratory, Oak Ridge, TN 37831 (1985) [7] Gita Alghband and Harry F. Jordan "Multiprocessor Sparse L/U Decomposition with Controlled Fill-in" Tech. Report 85-48, ICASE, NASA Langley Research Center, Hampton, VA 23665 (1985) [8] H. T. Kung and C. E. Leiserson. Algorithms for VLSI Processor Arrays, Addison-Wesley, Reading, MA, 1980, pp. 271-292 [9] Jack J. Dongarra and Iain S. Duff "Advanced Computer Architectures" Tech. Memorandum, Mathematics and Computer Science Division, Argonne National Laboratory, Argonne, IL (1985) [10] Alan George and Joseph Liu. Computer Solution of Large Sparse Positive Definite Systems, Prentice Hall, Englewood Cliffs, NJ, 1981 [11] Alan George, et. al. "Incomplete Nested Dissection for Solving n By n Grid Problems" SIAM Journal of Numerical Analysis, Vol. 15, No. 4, Aug. 1978, pp. 662-673

[12] Richard J. Lipton and Robert E. Tarjan "A Separator Theorem for Planar Graphs" SIAM Journal of Applied Mathematics, Vol. 36, No. 2, April 1979, pp. 177-189 [13] Richard J. Lipton and Robert E. Tarjan "Generalized Nested Dissection" SIAM Journal of Numerical Analysis Vol. 16, No. 2, April 1979, pp. 346-358 [14] B. M. Irons "A Frontal Solution Program for Finite Element Analysis" International Journal of Numerical Methods in Engineering, Vol. 2, 1970, pp. 5-32


CAYENNE: A Parallel Implementation of the Circuit Simulator SPICE Gabriel Bischoff, Steven Greenberg Digital Equipment Corporation, 77 Reed Road (HLO2-2/H13) Hudson, Massachusetts 01749-2895

Abstract As multiprocessor computers become commercially available, converting or creating programs to run on these machines in concurrent streams becomes more attractive. This paper presents a conversion of the well known and widely used circuit simulator SPICE into a parallel program running under the operating system VMS on a series of new VAX multiprocessor computers. The present machines are dual processors, but the converted program called CAYENNE is not limited to two processors. References [1] L.W. Nagel "SPICE2. A Computer Program to Simulate Semiconductor Circuits" University of California, Berkeley, Memo No. ERL-M520, May 1975. [2] W.T. Weeks "Algorithms for ASTAP - A Network Analysis Program" IEEE Trans. on Circuit Theory, Vol. CT-20, pp. 628-634, Nov. 1983. [3] R. Saleh, J. Kleckner and R. Newton "Iterated Timing Analysis and SPLICE1" Proc. IEEE International Conference on Computer Aided Design, Santa Clara, Ca, pp. 139-140, Sept. 1983. [4] J. White and A. Sangiovanni-Vincentelli "Relax 2.1 - A Waveform Relaxation Based Circuit Simulation Program" Proc. International Custom Integrated Circuits Conference, Rochester, N.Y., pp. 232236, June 1984. [5] K. Sakallah and S.W. Director "An Activity Directed Circuit Simulation Algorithm" Proc. IEEE Conference on Circuits and Computers, pp. 1032-1035, October 1980. [6] J.T. Deutsch "Algorithms and Architecture for Multiprocessor Based Circuit Simulation" University of California, Berkeley, Memo No. ERL M85/39, May 1985. [7] J. White and A. Sangiovanni-Vincentelli "Partitioning Algorithms and Parallel Implementation of Waveform Relaxation Algorithms for Circuit Simulation" Proc. International Symposium on Circuits and Systems, pp. 221-224, June 1985. [8] G.K. Jacob, A.R. Newton and D.O. Pederson "Direct Method Circuit Simulation Using Multiprocessors" Proc. International Symposium on Circuits and Systems, pp.170-173, May 1986. [9] A.R. Newton "The Simulation of Large Scale Integrated Circuits" IEEE Trans. on Circuits and Systems, Vol. CAS-26, pp. 741-749, Sept. 1979.

[10] R. Thomas "Using the Butterfly to Solve Simultaneous Linear Equations" BBN Labs Memorandum, March 1985. [11] Fujio Yamamoto and Sakae Takahashi "Vectorized LU Decomposition Algorithms for Large Scale Circuit Simulation" IEEE Trans. on Computer Aided Design, Vol. CAD-4, No. 3, pp. 232-239, July 1985.


Circuit Partitioning for Parallel Processing Paul Cox, Richard Burch, Berton Epler Texas Instruments Inc., Dallas, Texas

ABSTRACT Circuit simulation with SPICE on a scalar processor is too costly and time consuming to adequately support the design of VLSI circuits. The new high performance parallel processing systems offer an attractive alternative for improvement in computational throughput and satisfy circuit simulation requirements. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processors can be used efficiently. Three distinct approachs for obtaining parallel execution have been investigated in this study. These approachs differ primarily in the size of the individual tasks used to obtain parallel execution. The relative performance and advantages of each partitioning strategy have been examined. REFERENCES [1] A. Vladimirescu and D. O. Pederson Proc. ICCC '82, pp. 172-175, 1982. [2] Bruce Greer. VLSI System Design, pp 30-32, January 1986. [3] Jack Perry. Alliant Computer Systems, unpublished work. [4] Fujio Yamamoto and Sakae Takahashi. IEEE Trans. on CAD, vol. CAD-4, no. 3, July 1985. [5] B. W. Kernighan and S. Lin 'An Efficient Heuristic Procedure Partitioning Graphs' Bell System Technical Journal, vol. 49, February 1970, pp. 291-307. [6] C. M. Fiduccia and R. M. Mattheyses 'A linear-Time Heuristic for Improving Network Partitions' Proc. 19th Design Automation Conference, Las Vegas, June 1982, pp. 175-181. [7] Goldberg, M.K., and Burstein, M 'Heuristic Improvement Technique for Bisection of VLSI Networks' Proc. IEEE Int. Conf. on Computer Design: VLSI in Computers, Port Chester, NY, October 1983, pp122-5.


A Gridless Maze Router: DBM (Diffraction Boundary Method) J.G. Xiong Department of Electrical Engineering and Computer Sciences and Electronics Research Laboratory, University of California, Berkeley, CA 94720

Abstract This paper describes a gridless maze router developed from a new routing approach based on the law of propagation and diffraction of waves, and geometrical analysis of obstacles. The main advantages of this new routing approach are: (1) it has more powerful searching ability than gridded maze routers, particularly in the cases of gridless routing and multiwidth routing: if there is a Manhattan path with any required width including that one which can not be found by gridded maze routers because the path or its a part is not lying on the gridded positions, the path can always be found by this new routing approach; (2) it needs O(n) memory where 'n' is the number of line segments needed for connection of the nets; (3) it is fast, particularly when the number of nets to be routed is the same but the minimum interval between two lines is reduced, say from 5 µm to 0.5 µm, the required memory and runtime are almost unaffected (for traditional maze routers, they will increase about 100 times). (4) it can easily handle single-layer routing problems and multi-layer routing problems. So it can be used in cell design, over-the-cell routing, interactive routing, and rerouting, which occur in gate-array, standard-cell, and buildingblock layout. This gridless maze router, named DBM (Diffraction Boundary Method), was written in the C language, and runs under the 4.3 Berkeley UNIX on VAX 11/780. Although this router is still being tested, very good experimental routing results have been obtained. References [1] C.Y. Lee 'An Algorithm for Path Connections and Its Applications' TER Trans. EC-10. P.346 (Sept. 1961). [2] A. Hashimoto, J. Stevens 'Wire Routing by opimizing channel assignment within large appertures' in Proc. 8th Design Automation Workshop, PP. 159-169, 1971. [3] D. Hightower 'A solution to the line routing problem on the continuous plane' in Proc. Design Automation Workshop, pp.1-24, 1969. [4] J.G. Xiong (Xiong Ji-Guang), Tokinori Kozawa 'An algorithm for searching shortest path by propagating wave fronts in four quadrants' Proc. 18th Design Automation Conference, PP. 29-34, 1981. [5] J.G. Xiong 'Algorithms for global routing' Proc. 23rd Design Automation Conference, pp. 824-830, 1986.


TRIGGER: A Three-Layer Gridless Channel Router Howard H. Chen Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA 94720

ABSTRACT With the recent advances in VLSI technology, the multi-layer interconnection problem has become increasingly important. Given different design rules on different layers, it is impractical to use a grid-based (rows and columns) approach. A gridless approach should be used to take care of different wire widths, spacings, and contact sizes on different layers. For three-layer channel routing, we assume that horizontal wires will be routed on the first and third layer, and vertical wires will be routed on the second layer. Wires may have different width and spacing requirements on different layers. Contacts are allowed on adjacent layers only. Since the space over the cell is usually unused on layer 2 and layer 3, we can define different boundaries for different layers to utilize this space for over-the-cell routing. While the boundary for layer 3 may be larger than the boundary for layer 1, the fixed terminals can be located between the boundaries of layer 1 and layer 3. The algorithm, which is based on a weighted constraint graph, has been implemented in C on a VAX 11/785 under 4.3 Berkeley UNIX. Experimental results show that Trigger performs very well not only in the gridless cases, but also in the grid-based examples. References [1] A. Hashimoto and J. Stevens "Wire routing by optimizing channel assignment within large apertures" in Proc. 8th Design Automation Workshop, pp. 155-169, 1971. [2] D. Deutsch "A dogleg channel router" in Proc. 13th Design Automation Conf., pp. 425-433, 1976. [3] D. Hightower "A generalized channel router" in Proc. 17th Design Automation Conf., pp. 12-21, 1980. [4] K. Sato et al. "A 'grid-free' channel router" in Proc. 17th Design Automation Conf., pp. 22-31, 1980. [5] T. Yoshimura, and E. S. Kuh "Efficient Algorithms for channel routing" IEEE Trans. on CAD of ICs and Systems, vol. CAD-1, no. 1, pp. 25-35, Jan. 1982. [6] R. Rivest, and C. Fiduccia "A 'greedy' channel router" in Proc. 19th Design Automation Conf., pp. 418424, 1982. [7] M. Burstein, and R. Pelavin "Hierarchical channel router" in Proc. 20th Design Automation Conf., pp. 591-597, 1983. [8] H. Rothermel, and D. Mlynski "Automatic variable-width routing for VLSI" IEEE Trans. on CAD, vol. CAD-2, no. 4, pp. 271-284, October 1983. [9] S. Kimura et al. "An automatic routing scheme for general cell LSI" IEEE Trans. on CAD, vol. CAD-2, no. 4, pp. 285-292, October 1983. [10] T. Yoshimura "An efficient channel router" in Proc. 21st Design Automation Conf., pp. 38-44, 1984.

[11] A. Sangiovanni-Vincentelli et al. "A new gridless channel router : yet another channel router the second (YACR-II)" in Dig. Tech. Papers, IEEE Int. Conf. on Computer-Aided Design, pp. 72-75, 1984. [12] T. Krakow "Benchmark Proposal" in Int. Workshop on Symbolic Layout and Compaction, Chapel Hill, NC, 1986. [13] C. Ng "An industrial world channel router for non-rectangular channels" in Proc. 23rd Design Automation Conf., pp. 490-494, 1986. [14] H. Chen and E. Kuh "A variable-width gridless channel router," in Dig. Tech. Papers IEEE Int. Conf. on Computer-Aided Design, pp. 304-306, 1985. [15] D. Deutsch "Compacted channel routing" in Dig. Tech. Papers, IEEE Int. Conf. on Computer-Aided Design, pp. 223-225, 1985. [16] Y. Chen and M. Liu "Three-layer channel routing" IEEE Trans. on CAD, vol. CAD-3, no. 2, pp. 156163, April 1984. [17] P. Bruell and P. Sun "A 'greedy' three layer channel router" in Dig. Tech. Papers, IEEE Int. Conf. on Computer-Aided Design, pp. 298-300, 1985. [18] A. Sangiovanni-Vincentelli et al. "Chameleon: a new multi-layer channel router" in Proc. 23rd Design Automation Conf., pp. 495-502, 1986. [19] R. Enbody and H. Du "Near-optimal n-layer channel routing" in Proc. 23rd Design Automation Conf., pp. 708-714, 1986.


Variable Track Space Channel Routing Raymond Y. Tsui AT&T Bell Laboratories, 600 Mountain Avenue Murray Hill, N.J. 07974

Abstract In this paper, we propose a straight track routing compaction scheme which combines the advantages of variable track spacings and contact offsets to decrease channel routing area. A greedy algorithm for assigning offsets to contacts after channel routing is presented. This algorithm is part of the track spacer which determines the exact spacings between adjacent tracks taking contact offsets into account. Actual examples and results are given to indicate the benefits of this compaction scheme. A strategy of how to produce "more compactable" channel routing with the notion of straight tracks is also described. A precise description of how to achieve variable track space channel routing using existing standard channel routers [1] [2] [3] [4] [5] [6] [7] [8] [9] and the track spacer as a postprocessor is presented. With this proposed scheme, straight track routing compaction output can never be worse than the input. Channel area improvement of over 10% could be achieved. In addition, a discussion of the strengths and weaknesses of this compaction scheme is given. Suggestions of how to introduce "jogs" to further reduce the channel area are also included. References [1] A. Hashimoto and J. Stevens "Wire Routing by Optimizing Channel Assignment within Large Apertures" Proc. 8th Design Automation Workshop (1971). [2] B.W. Kernighan, D.G. Schweikert and G. Persky "An Optimum Channel-Routing Algorithm for Polycell Layouts of Integrated Circuits" Proc. 10th Design Automation Workshop (1973). [3] D.N. Deutsch "A 'Dogleg' Channel Router" Proc. 13th Design Automation Conference (1976). [4] K. Sato, H. Shimoyama, T. Nagai, M. Ozaki, and T. Yahara "A 'Grid-free' Channel Router" Proc. 17th Design Automation Conference (1980). [5] T. Yoshimura and E.S. Kuh "Efficient Algorithms for Channel Routing" IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. CAD-1, No. 1, (1982). [6] R.L. Rivest and C.M. Fiduccia "A 'Greedy' Channel Router" Proc. 19th Design Automation Conference (1982). [7] M. Burstein and R. Pelavin "Hierachical Channel Router" Proc. 20th Design Automation Conference (1983). [8] A. Sangiovanni-Vincentelli and M. Santomauro "YACR: Yet Another Channel Router" Proc. Custom Integrated Circuits Conference (1983). [9] A. Sangiovanni-Vincentelli, M. Santomauro and J. Reed "A New Gridless Channel Router: Yet Another Channel Router the Second (YACR-II)" Proc. of the IEEE International Conference on Computer-Aided Design (1984).

[10] D.N. Deutsch "Compacted Channel Routing" Proc. of the IEEE International Conference on Computer-Aided Design (1985). [11] B.W. Colbry and J. Soukup "Layout Aspects of the VLSI Microprocessor Design" Proc. of the IEEE International Symposium on Circuits and Systems (1982). [12] A.E. Dunlop and B. W. Kernighan "A Placement Procedure for Polycell VLSI Circuits" Proc. of the IEEE International Conference on Computer Aided Design (1983). [13] A.E. Dunlop "Automatic Layout of Gate Arrays" Proc. ICCAD (1983). [14] M. Wiesel "Loose Routing for Gate Arrays" Proc. ISCAS (1984). [15] A.E. Dunlop, V.D. Agrawal, D.N. Deutsch, M.F. Jukl, P. Kozak and M. Wiesel "Chip Layout Optimization Using Critical Path Weighting" Proc. 21st Design Automation Conference (1984).


A Versatile Finite State Machine Synthesizer Chia-Jeng Tseng, Ajit M. Prabhu, Cedric Li, Zafer Mehmood, Michael M. Tong AT&T Bell Laboratories, 600 Mountain Avenue Murray Hill, NJ 07974

Abstract This paper describes a synthesis tool, named the FSM Synthesizer, for the design of finite state machines. The input to the FSM Synthesizer can be either a textual or a graphical specification for a finite state machine; the output can be an implementation in polycells, Programmable Array Logic (PAL), or Programmable Logic Array (PLA). The FSM Synthesizer supports a menu-driven interface and has comprehensive consistencychecking capabilities. Two different types of functional simulation are available; one is state-based and the other is circuit-based. Efficient algorithms are incorporated in the synthesizer for performing automatic state-assignment. Manual state-assignment is supported; partial assignment which assigns codes to a subset of all the states is acceptable. The code assigned to a state may contain zero, one, and don't-care bits. Extensive experiments have shown that extending state-assignment to include zero, one and don't-care bits often results in more cost-effective designs than conventional approaches. References [1] D. B. Armstrong "A Programmed Algorithm for Assigning Internal Codes to Sequential Machines" IRE Transactions on Electronic Computers, Pages 466-472, August, 1972. [2] D. W. Brown "A State-Machine Synthesizer - SMS" Proceedings of the 18th Design Automation Conference, Pages 301-305, Nashville, Tennessee, 1981. [3] M. Buckley. Internal Memorandum, AT&T Bell Laboratories, May 1985. [4] H. Y. Chang, G. W. Smith, and R. B. Walford "LAMP: System Description" Bell System Technical Journal, Pages 1431-1449, Vol. 53, No. 8, October 1974. [5] G. DeMicheli and A. Sangiovanni-Vincentelli "Computer-Aided Synthesis of PLA-Based Finite State Machines" IEEE International Conference on Computer-Aided Design, Pages 154-156, Santa Clara, California, September 1983. [6] G. DeMicheli, R. Brayton, and A. Sangiovanni-Vincentelli "Kiss: A Program for Optimal State Assignment of Finite State Machines" IEEE International Conference on Computer-Aided Design, Pages 209-211, Santa Clara, California, November 1984. [7] D. L. Dietmeyer "Logic Design of Digital Systems" 2nd Edition, Allyn and Bacon, 1978. [8] J. Dussault, C. C. Liaw, and M. M. Tong "A High Level Synthesis Tool for MOS Chip Design" Proceedings of the 21st Design Automation Conference, Pages 308-314, Albuquerque, New Mexico, 1984. [9] F. Fazal, C-Y. Lu, H. N. Nham, E. Pacas-Skewes, and P. Subramaniam "The Front-End for the Second Generation MOTIS Simulation System" Proceedings of the International Conference on Computer Design: VLSI in Computers, Pages 487-491, New York, 1984.

[10] S. Kang and W. M. vanCleemput "Automatic PLA Synthesis From A DDL-P Description" Proceedings of the 18th Design Automation Conference, Pages 391-397, Nashville, Tennessee, 1981. [11] C. Mead and L. Conway "Introduction to VLSI Systems" Pages 85-88, Addison-Wesley, Massachusetts, October, 1980. [12] M. J. Meyer, P. Agrawal, and R. G. Pfister "A VLSI FSM Design System" Proceedings of the 21st Design Automation Conference, Pages 434-440, Albuquerque, New Mexico, 1984. [13] Monolithic Memories Inc. PAL Handbook" Third Edition, 1983. [14] G. Persky, D. N. Deutsch, and D. G. Schweikert "LTX - A System for the Directed Automatic Design of LSI Circuits" Proceedings of the 13th Design Automation Conference, Pages 399-407, San Francisco, California, 1976. [15] R. L. Rudell and A. Sangiovanni-Vincentelli "ESPRESSO-MV: Algorithms for Multiple-Valued Logic Minimization" Proceedings of the 1985 Custom Integrated Circuits Conference, Pages 230-233, Portland, Oregon, May 1985. [16] L. Spaanenburg, G. J. Kleissen, and H. van der Veen "Direct Implementation of State Diagram Specifications" Proceedings of the 1984 Custom Integrated Circuits Conference, Pages 361-365, Rochester, New York, May 1984. [17] J. R. Story, H. J. Harrison, and E. A. Reinhard "Optimum State Assignment for Synchronous Sequential Circuits" IEEE Transactions on Computers, Pages 1365-1373, Vol. C-21, No. 12, December, 1972. [18] R. F. Wessling, Jr. Internal Memorandum, Bell Laboratories, July 1979.


State Synthesis and Connectivity Binding for Microarchitecture Compilation Barry M. Pangrle, Daniel D. Gajski Dept. of Computer Science, University of Illinois, 1304 West Springfield Ave. Urbana, Illinois 61801

ABSTRACT Silicon Compilers are an important and necessary tool for application-specific integrated circuit (ASIC) design. State synthesis and connectivity binding play a major role in microarchitecture synthesis. In this paper we present a new strategy that uses a flexible structural model for binding variable execution time and pipelined function units. Examples for system comparisons are given. The code for this project is run under 4.2 BSD Unix on a VAX 11/780 and is written in C. REFERENCES [BrGa86] F. D. Brewer, D. D. Gajski "An Expert-System Paradigm for Design" Twenty-third Design Automation Conference, June 1986. [BuMa 85] M. R. Buric, T. G. Matheson "Silicon Compilation Environments" Custom Integrated Circuits Conf., May 1985. [DeRS86] H. DeMan, J. Rabaey, P. Six "CATHEDRAL II: A Synthesis and Module Generation System for "Multiprocessor Systems on a Chip" NATO Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L"Aquila, Italy, July 7-18, 1986. [GaDP86] D. D. Gajski, N. D. Dutt, B. M. Pangrle "Silicon Compilation (Tutorial)" Custom Integrated Circuits Conference, May 1986. [GiBK85] E. F. Girczyc, R. J. A. Buhr, J. P. Knight "Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation" IEEE Transactions on Computer-Aided Design, vol. CAD-4, no. 2, April 1985. [JVJC86] A. Jerraya, P. Varinot, R. Jamier, B. Curtois "Principles of the SYCO compiler" 23rd Design Automation Conference, June 1986. [JoMa84] S. C. Johnson, S. Mazor "Silicon Compilation lets system makers design their own VLSI chips" Electronic Design, October 1984. [Knut60] D. E. Knuth "The Art of Computer Programming: Volume 2 Seminumerical Algorithms" Addison-Wesley 1960. [KGWF85] T. J. Kowalski, D. J. Geiger, W. H. Wolf, W. Fichtner "The VLSI Design Automation Assistant: From Algorithms to Silicon" IEEE Design and Test, August 1985. [NSDK83] S. Nance, C. Starr, B. Duyn, M. Kliment "Cell-Layout Compilers Simplify Custom IC Design" EDN, September 15, 1983. [PaKG86] P. G. Paulin, J. P. Knight, E. F. Girczyc "HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis" 23rd Design Automation Conference, June 1986.

[PoRB86] S.P. Pope, J.M. Rabaey, R.W. Brodersen "Automatic Generation of Digital Signal Processing Circuits" NATO Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aquila, Italy, July 7-18, 1986. [Sout83] J. R. Southard "MacPitts: An Approach to Silicon Compilation" IEEE Computer, vol. 16, no. 12, December 1983. [TsSi86] C. J. Tseng, D. P. Siewiorek "Automated Synthesis of Data Paths in Digital Systems" IEEE Transactions on Computer-Aided Design, vol. CAD-5, no. 3, July 1986. [TsSi83] C. J. Tseng, D. P. Siewiorek "Facet: A Procedure for the Automated Synthesis of Digital Systems" Twentieth Design Automation Conference, June 1983.


Another Automated Data Path Designer Vijay K Raj Department of Electrical Engineering and Computer Science, University of Illinois at Chicago, Chicago, Illinois 60680

ABSTRACT This paper describes a methodology for translating an algorithmic description of a digital system to the register transfer structure of the system. The algorithmic description of any digital system is first translated to a data flow graph. This graph is then translated to a control sequence and a data path. This data path can have adders subtractors etc. which do their computation over multiple clock cycles. REFERENCES [GaKu83] D. D. Gajski, R. H. Kuhn "New VLSI Tools" IEEE Computer, vol. 16, no. 12, December 1983. [GaDP86] D. D. Gajski, N. Dutt, B. Pangrle "Silicon Compilation (Tutorial)" Proceedings of CICC 1986 [Hayes 78] J.P. Hayes "Computer Architecture and Organization" McGraw 1978. [Raj85] V.K. Raj "Translating Data Flow Graphs to Architectures" Ph.D. Thesis, Department of Computer Science, University of Illinois at Urbana Champaign [RaPG84] V.K. Raj, B.M. Pangrle, D.D. Gajski "Microprocessor Synthesis" Proceedings of the 21st Design Automation Conference. [SiSC 82] J. Siskind, J. Southard, Kenneth Crouch "Generating custom High Performance VLSI designs" "from succinct Algorithmic Descriptions" 1982 Conference on Advanced Research in VLSI, MIT. [Zimm80] G. Zimmerman "MDS - The Mimola Design System" Journal of Digital Systems, Vol. 4, no. 3, pp. 337-69, 1980.


Realistic Yield Simulation for IC Structural Failures Ihao Chen, Andrzej J. Strojwas SRC-CMU Center for Computer-Aided Design, Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA 15213

Abstract This paper presents an analytically-based approach for accurate and efficient IC yield simulation. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometric variations and spot defects. The probabilities of different kinds of failures for layout patterns can be calculated hierarchically. Then, yields of the cell and chip levels can be found according to these probabilities. Based upon the simulated results and the predicted faults, the design rules can be optimized to maximize the final yield. References [1] W. Maly. Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. IEEE Transactions on CAD CAD-4(3):166-177, July, 1985. [2] C. H. Stapper. Modeling of Integrated Circuit Defect Sensitivities. IBM J. Res. Develop. 27(6), November, 1983. [3] R. Razdan, and A. J. Strojwas. Statistical Design Rule Developer. IEEE International Conference on CAD Digest of Technical Papers:315-317, Nov., 1985. [4] H. Walker, and S. W. Director. VLASIC: A Yield Simulator for Integrated Circuits. IEEE International Conference on CAD Digest of Technical Papers:318-320, Nov., 1985. [5] W. Maly, A. J. Strojwas and S. W. Director. VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Transactions on CAD CAD-5, NO. 1:114-130, January, 1986. [6] R. M. Warner, Jr. Applying a Composite Model to the IC Yield Problem. IEEE J. Solid-State Circuits SC-9:86-95, June, 1974.


Statistical Modeling of VLSI Circuit Performances T.K. Yu, S.M. Kang, I.N. Hajj, T.N. Trick Coordinated Science Laboratory and Department of Electrical and Computer Engineering, University at Illinois at Urbana-Champaign, 1101 W. Springfield Avenue, Urbana, Illinois 61801

ABSTRACT A major cost in statistical analysis occurs in repeated system simulation as system parameters are varied. To reduce this cost the system performances are approximated by regression models in terms of critical system parameters. These models are then used to predict the performance variations and parametric yield. A problem then arises as to what constitute critical system parameters. This paper presents a systematic and computationally efficient method for the statistical modeling of MOS VLSI circuit performances. An average mean-squared error criterion is used to select an optimal set of points in the design space for circuit simulations, and a systematic method is introduced to check the adequacy of the fitted regression models. It will be shown through examples that accurate statistical performance models for MOS VLSI can be derived by using four or five device parameters and a small number of circuit simulations. REFERENCES [1] W. Maly, A. J. Strojwas and S. W. Director "VLSI yield prediction and estimation: a unified framework" IEEE Transactions on Computer Aided Design of ICAS, vol. CAD-5, No. 1, pp. 114-130, January 1986. [2] P. C. Cox, P. Yang, S. S. Manhant-Shetti and P. K. Chatterjee "Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits" IEEE Journal of Solid State Circuits, vol. SC-20, No. 1, pp. 391-398, February 1985. [3] P. Yang, D. E. Hocevar, P. C. Cox, C. Machala and P. K. Chatterjee "An integrated and efficient approach for MOS VLSI statistical design" IEEE Transactions on Computer Aided Design of ICAS, vol. CAD-5, No. 1, pp. 5-14, January 1986. [4] S. Liu and K. Singhal "A statistical model for MOSFET's" IEEE International Conference on Computer Aided Design, pp. 78-80, 1985. [5] G. T. Wright and H. M. A. Gaffur "Preprocessor modeling of parameter and geometry dependences of short and narrow MOSFET's for VLSI circuit simulation, optimization, and statistics with SPICE" IEEE Transactions on Electron Devices, vol. ED-32, No. 7, pp. 1240-1245, July 1985. [6] G. E. P. Box and N. R. Draper "A basis for the selection of a response surface design" American Statistical Association Journal, vol. 54, pp. 622-654, September 1959. [7] W. J. Welch "A mean squared error criterion for the design of experiments" Biometrika, vol. 70, pp. 205-213, 1983. [8] W. J. Welch "ACED: Algorithms for the construction of experiments" User's Guide, Version 1.6.1, Department of Commerce and Business Administration, University of British Columbia.

[9] R. Suich and G. C. Deringer "Is the regression model adequate?-- one criterion" Technometrics, vol. 19, no. 2, pp. 213-216, May 1977. [10] S. M. Kang "Accurate simulation of power dissipation in VLSI circuits" IEEE Journal of Solid State Circuits, to appear. [11] P. Yang "An investigation of ordering, tearing and latency algorithms for the time domain-simulation of large circuits" Ph.D. Thesis, University of Illinois at Urbana-Champaign, 1980. [12] SAS User's Guide: Basics and Statistics, SAS Institute, 1985.


Variational Analysis of Integrated Circuits V. Visvanathan AT&T Bell Laboratories, Murray Hill, New Jersey 07974

ABSTRACT Variational analysis (generalized worst-case analysis) is a technique for determining the manufacturability of a design. Given a design and information regarding manufacturing and environmental variations, the method provides a set of limits on the measures of performance and an estimate of the percentage of manufactured circuits that willsatisfy the reported limits. Further, first-order estimates of the large-change sensitivities of the design objectives to the sources of the manufacturing and environmental variations are provided. The method has been implemented in a CAD package and applied to CMOS circuits. References [1] S. R. Nassif, A. J. Strojwas and S. W. Director "A Method for Worst-Case Analysis of Integrated Circuits" IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, January 1986, pp. 104-113. [2] D. A. Divekar "DC Statistical Circuit Analysis for Bipolar IC's Using Parameter Correlations – An Experimental Example" IEEE Trans. Computer-Aided Design, vol. CAD-5, no. 1, January 1984. [3] S. Liu and K. Singhal "A Statistical Model for MOSFETS" Proceedings of the IEEE International Conference on Computer-Aided Design, Santa Clara CA, 1985, pp. 78-80. [4] G. D. Hachtel, T. R. Scott and R. P. Zug "An Interactive Linear Programming Approach to Model Parameter Fitting and Worst-Case Circuit Design" IEEE Trans. Circuits and Systems, vol. CAS-27, no. 10, October 1980, pp. 871-882. [5] C. R. Rao "Linear Statistical Inference and Its Applications" John Wiley and Sons, 1973. [6] K. Singhal, S. Liu and V. Visvanathan "CENTER/ADVICE: A CAD System for Circuit Design Optimization" manuscript in preparation. [7] W. T. Nye, A. Sangiovanni, J. P. Spoto and A. L. Tits "DELIGHT SPICE: An Optimization Based System for the Design of Integrated Circuits" Proc. CICC'83, pp. 233-238. [8] A. J. Strojwas "Pattern Recognition Based Methods for IC Failure Analysis" Ph.D. Dissertation, Carnegie-Mellon University, 1982. [9] S. R. Nassif, A. J. Strojwas and S. W. Director "FABRICS II-A Statistically Based IC Fabrication Process Simulator" IEEE Trans. Computer-Aided Design, vol. CAD-3, no. 1, January 1984, pp. 40-46. [10] P. Cox, P. Yang, S. S. Mahant-Shetti and P. K. Chatterjee "Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits" IEEE Journal of Solid-State Circuits, vol. SC-20, no. 1, February 1985, pp. 391-398.


Models for a New, Profit-Based Methodology for Statistical Design of Integrated Circuits David C. Riley, Alberto Sangiovanni-Vincentelli University of California, Berkeley

Abstract A new statistical design methodology for integrated circuits is proposed, based on a multi-faceted generalization of conventional problem formulations in statistical design. In the new optimization-based methodology, the objective function is a measure of expected profit associated with the product being designed. A set of new assumptions, significantly relaxed relative to those commonly made in conventional formulations, are described. The new assumptions include that the number of performance categories of finished circuits is allowed to be arbitrary, and that the design parameters in the formulation are all that have a first-order affect on the expected profit of the product. The model for profit in terms of design parameters and random variables of the relevant statistical phenomena, is described, and constraints which must be imposed are identified. Also discussed are insights into IC product development, and applications to decision-making in nonparametric aspects of design. References [ANT81] K. J. Antreich and R. K. Koblitz "An interactive procedure to design centering" Proc. 1982 IEEE Int. Symp. Circuits and Systems, (Houston, TX), pp. 139-142, 1981. [BRA81] R. K. Brayton, G. D. Hachtel, and A. L. Sanglovanni-Vincentelli "A survey of optimization techniques for integrated-circuit design" Proc. of IEEE, vol. 69, no. 10, pp.1334-1362, Oct. 1981. [HOC83] D. E. Ilocevar, M. R. Lightner, and T. N. Trick "Monte Carlo based yield maximization with a quadratic model" Proc. 1983 IEEE Int. Symp. Circuits and Systems, (Newport Beach, CA), pp. 668 561, April 1983. [MES87] P. R. Messinger and D. C. Riley "An Approach to Modeling Market Demand for Integrated Circuits" in preparation. [NAS84] S. R. Nassif, A. J. Strojwas, and S. W. Director "FABRICS II, A Statistically Based IC Fabrication Process Simulator" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-3, No. 1, January, 1984. [NES78] S. H. Neslin "Linking product features to perceptions: applications and analysis of graded paired comparisons" Proc. of 1978 Educators Conf., American Marketing Association, Aug. 1978. [RIL86] D. C. Riley and A. Sanglovanni-Vincentelli "Models for a new, profit-based methodology for statistical design of Integrated circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-5, No. 1, pp. 131-169, January 1986. [SIN81] K. Singhal and J. F. Finel "Statistical design centering and tolerancing using parametric sampling" IEEE Transactions on Circuits and Systems, vol. CAS-28, pp.692-702, July 1981.

[STY81] M. A. Styblinski, J. Ogrodski, L. Opalski, and W. Strasz, "New methods of yield estimation and optimization and their application to practical problems" Proc. 1982 Int. Symp. Circuits and Systems (Houston, TX), pp. 131-134, April, 1981. [STY83] M. A. Styblinski "Stochastic approximation - a new tool for production yield optimization" Proc. 1983 IEEE Int. Symp. Circuits and Systems, (Newport Beach, CA), pp. 546 549, April 1983. [VID82] L. M. Vidigal and S. W. Director "A design centering algorithm for nonconvex regions of acceptability" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, No. 1, pp. 13-24, Jan. 1982.


Hierarchical Loose Routing for Gate Arrays K. Winter, D.A. Mlynski Universitat Karlsruhe, Kaiserstrasse 12 D-7500 Karlsruhe, West-Germany

Abstract In this paper we present a quasiparallel approach to the loose routing problem for gate array LSI design. It is based on a new modelling for the decomposition problem of each net using a small net graph. Since this net graph does not contain any feed throughs but only the connectivity information between net terminals it is a minimal net graph. A hierarchical approach is demonstrated, using this routing concept. This leads to a quasiparallel embedding of all nets. It also allows different routing priorities for single connections within multi terminal nets. References [1] K. Aoshima, E.S. Kuh "Multi channel optimisation in gate array LSI layout" Proc. ISCAS (1983) p.1005-1008. [2] S. Tsukiyama, I. Harada, M. Fukui, I. Shirakawa "A new global router for gate array LSI layout" IEEE Trans. CAD-2 (1983) p.313-321. [3] M. Wiesel "Loose routing for gate arrays" Proc. ISCAS (1983) p. 444-448. [4] H. Sadorf, H.J. Rothermel, D.A. Mlynski "An automatic routing system for gate array layout" Proc. ISCAS (1983) p.1001-1004. [5] A.V. Aho, J.E. Hopcroft, J.D. Ullman "The design and analysis of computer algorithms" AddisonWesley (1974). [6] S. Pallottino "Shortest path methods" Networks Vol 14 (1984) p.257-267. [7] U.G. Baitinger, D.A. Mlynski, S. Dao Trong "The MEGA system: An automated methodology for semi-custom VLSI chip design" Proc. ICCAD (1985) p.97-99.


An Enhanced Heuristic for Multi-Channel Optimization in Gate-Array Layout Lishin Lin, Sartaj Sahni University of Minnesota

Eugene Shragowitz Control Data Corporation

Abstract We present enhancements to the multi-channel optimization heuristic proposed by Aoshima and Kuh [AOSH83]. References [AOSH83] Aoshima, K. and Kuh, E.S. "Multi-Channel Optimization in Gate-Array LSI Layout" ICCAD'83, pp.1005-1008 (1983). [DEUT76] Deutsh, D.N. "A Dogleg Channel Router" Proc. 13th Design Automation Conference, pp. 425433 (1976). [RIVE82] Rivest, R.L. and Fiduccia, C.M. "A "Greedy" Channel Router" Proc. 19th Design Automation Conference, pp. 418-424 (1982). [HORO78] Horowitz, E. and Sahni, S. "Fundamentals of Computer Algorithms" Computer Science Press, Potomac, MD, (1978). [AKER76] Aker, S. "Routing" in "Design Automation of Digital System : Theory and Techniques, vol.1" ed. Breuer, M. Prentice-Hall, NJ. (1972).


Route Planner for Custom Chip Design Malgorzata Marek-Sadowska Electronics Research Laboratory, University of California, Berkeley, Ca 94720

Abstract We present here a routing algorithm for custom chip design environment. The router can be considered as a global router for multilayer (two and more layers) designs or as a route planner for a top-down chip design process (more than two layers). The model assumes the chip as a collection of rectilinear macros and wires are allowed to pass through them. The algorithm is based on a top-down hierarchical scheme. In each step of hierarchy, the current routing problem is partitioned (cut) into two subproblems. Linear assignment algorithm is used to assign nets to the boundaries which are included into the most recent cut line. The algorithm has been implemented in C language and preliminary results suggest that it can efficiently handle problems of practical size. The method is very general and can be applied to arbitrary (including non-slicing) floorplans and arbitrary shape and size rectilinear blocks. References [1] Vecchi, M.P. and S. Kirkpatrick "Global Wiring by Simulated Annealing" IEEE Trans. on ComputerAided Design, CAD-2, 1983. [2] Burstein, M. and R. Pelavin "Hierarchical Wire Routing" IEEE Trans. on Computer Aided Design, CAD-2, 1983. [3] Marek-Sadowska, M. "Global Router for Gate Array" Proc. IEEE Int. Conf. on Computer Design, CAD-3, 1984. [4] Marek-Sadowska, M. "Routing Multi Power Nets in Building Block Layout Environment" to appear. [5] Ousterhout, J.K. "Corner Stitching: A Data Structuring Technique for VLSI Layout Tools" IEEE Trans. on Computer Aided Design, CAD-1, 1984. [6] Hanan, M. "On Steiner's Problem with Rectilinear Distance" SIAM J. of Applied Math., 14 (March 1966). [7] Burkard, R.E. and U. Derigs "Assignment and Matching Problems : Solution Methods with FortranPrograms" Springer Verlag, 1980. [8] Luk, W.K., D.T. Tang, C.K. Wong "A Hierarchical Global Wiring Algorithm for Custom Chip Design" 23 DAC, 1986. [9] U. Lauther private communication, 1986.


A Routing System For High-Performance Computer Systems Norio Kuwahara, Shinichi Asami, Nobuo Takano, Minoru Nomura NEC Corporation, CAD Engineering Department, Computer Engineering Division, 1-10 Nisshincho, Fuchu City, Tokyo, 183 Japan

ABSTRACT This paper describes an automatic routing system which mainly considers crosstalk and propagation delay. For reducing crosstalk, two functions, Regular Interval Shield and Multi-Grid Routing are provided. The combination of these two functions can drastically reduce crosstalk noise without routability deterioration. For adjusting propagation delay, two other functions, Diagonal Routing and Detour Routing, are provided. Diagonal Routing and Detour Routing are respectively applied for assuring permissible maximum delay and minimum delay. Their use is automatically controlled, based on the timing estimation performed after placement. This routing system has successfully been applied for the layout design of high speed and high density digital circuit boards used in high-performance computer systems. REFERENCES [1] P.N. Veukatachalam "Pulse propagation properties of multilayer ceramic multichip modules for VLSI circuits" Proc. 33rd Electronic Components Conference, pp130-134; May 1983 [2] I. Catt "Crosstalk (noise) in digital systems" IEEE Trans. Electronic Computers, EC-16 pp743-763; December 1967 [3] A.J. Gruodis and C.S. Chang "Coupled lossy transmission line characterization and simulation" IBM J. Res and Develop., pp25-41; January 1982 [4] H.R. Kaupp "Pulse crosstalk between microstrip transmission lines" 7th Intl. Electronic Packaging Symp. record, Wescon 66; August 1966 [5] M. Nomura, S. Sato, N. Takano, T. Aoyama and A. Yamada "Timing verification based on delay time hierarchical nature" Proc. 19th Design Automation Conf., pp622-628; 1982


Automatic Generation of Controller Systems from Control Software Richard M. Marshall Dept. of Computer Science, University of Edinburgh, Edinburgh, Scotland, EH9 3JZ

Abstract Control computers are being used for increasingly demanding tasks. Despite the software being far more complex, the hardware is still being designed first. Getting the software right first time is becoming increasingly important as these controllers become integrated circuits and it is no longer possible to develop the code in situ. This paper presents a novel tool which simulates and synthesis complete microprocessor systems from the software they are to run. References [1] W.P. Birmingham and D.P. Siewiorek. "MICON: a knowledge based single board computer designer". In 21st Design Automation Conference, pages 565-571, 1984. [2] J.A. Bowen and M.F. Smith "Expert systems for analysis and design of microprocessor applications". Journal of Microcomputer Applications, 6(2):155-161, April 1983. [3] R. Bruck, B. Kleinjohann, T. Kathofer, and F.J. Rammig. "Synthesis of concurrent modular controllers from algorithmic descriptions". In 23rd Design Automation Conference, pages 285-292, June 1986. [4] M.R. Buric, C. Christensen, and T.G. Matheson. "The Plex project: VLSI layouts of microcomputers generated by a computer program". In Digest of Technical Papers, pages 49-50, International Conference on Computer Aided Design, 1983. [5] S. Evanczuk. "Core-based custom processors". VLSI Design, VI(5):20-38, May 1985. [6] D. Fay. "Interrupts and the hardware-software rendezvous -- microcomputer software engineering". Microprocessors and Microsystems, 9(2), March 1985. [7] E.F. Girczyc, R.J.A. Buhr, and J.P. Knight. "Applicability of a subset of Ada as an algorithmic HDL for graph based hardware compilation". IEEE Transactions on Computer Aided Design for Integrated Circuits, CAD-4(2):134-142, April 1985. [8] C.A.R. Hoare. "Communicating sequential processes". Communications of the ACM, 21(8):666-677, August 1978. [9] INMOS Ltd. Occam Programming Manual. Prentice Hall International, 1984. [10] T. Mano, F. Maruyama, et al. Occam To CMOS. Technical Report TR-093, Institute for New Generation Computer Technology, December 1984. [11] E.I. Organick, et al. "Transforming an Ada program unit into silicon and verifying its behavior in an Ada environment: a first experiment". IEEE Software, 1(1):31-50, January 1984. [12] L.D. Smith. The Elementary Structural Description Language. Technical Report CSR-53-80, University of Edinburgh, Department of Computer Science, January 1980.

[13] S. Trimberger and J. Rowson. "Automatic layout in an open design system". VLSI Design, VI(5):8898, May 1985.


Rescue: A Comprehensive Control Logic Layout Synthesis System Ching-Hao Shaw, Pat Bosshart, Vibhu Kalyan, Theodore W. Houston, Doug Matzke Texas Instruments Incorporated, Dallas, Texas 75265

ABSTRACT A new control logic layout synthesis system, RESCUE, has been used to synthesize the layout of the 12000-transistor control section of a microprocessor. RESCUE accepts input in the form of an RTL description which may include dynamic domino and static gates as well as registers. Combinational logic is implemented in a multiply-folded array, while domino output inverters, storage elements and buffers are implemented as tiles positioned above and below the array. Outputs may be fed back directly into the array so that arbitrary numbers of logic levels can be included in a clock cycle. The array's poly tracks are multiply folded by a heuristic permutation algorithm which minimizes a cost function of poly track length and signal order. The array layout is topologically compacted with flexible transistor placements. All registers are connected in a serial scan path, and special tiles provide control mechanisms for the associated datapath's scan system. The integration of tiles with the logic array promotes good chip floorplan. References [1] A. Weinberger. "Large Scale Integration of MOS Complex Logic." IEEE Solid-State Circuits, Vol. SC2, December 1967, pp. 182-190. [2] A. Lopez, and H. F. Law "A Dense Gate Matrix Layout Method for MOS VLSI" IEEE Solid-Static Circuits, Vol. SC-15, No. 4., August 1980, pp.736-740. [3] O. Wing, S. Huang, and R. Wang "Gate Matrix Layout" IEEE Trans. on Computer-Aided Design, Vol. CAD-4, July 1985, pp. 220-231. [4] C. Rowen, and J. L. Hennessy "SWAIMI: A Flexible Logic Implementation System" Proc. 22nd Design Automation Conference, June 1985, pp. 169-175. [5] J. D. Ullman [1984]. "Computational Aspects of VLSI" P.441, Computer Science Press, Inc., Rockville, Maryland.


Optimal Structuring of Hierarchical Control-Paths in a Silicon-Compiler System H. Joepen, M. Glesner Technische Hochschule Darmstadt, D-6100 Darmstadt, FR Germany

Abstract The automatic derivation of flexible control pathes from behavioural input descriptions is a central part of our work on the ALGIC (Automatic Layout Generation for Integrated Circuits) silicon compiler system. In this paper we describe new methods of restructuring control paths which have been constructed using a hierarchy structure which is isomorphous to the structure given by the input program. By this restructuring the sequential depth of the control path (and thereby its speed) and the size will be optimized. The restructuring algorithm has been implemented in the ALGIC system and has successfully been tested on several examples. It has shown area reductions of up to 60% of the initial control path solution. References: [1] D.E. Thomas et. al. "Automatic Data Path Synthesis" IEEE Computer, December 1983, pp. 59-70 [2] R. Jamier, A.A. Jerraya "Appollon, A Data Path Compiler" Proc. ICCD 86 Conference, Port Chester, October 1985 [3] Siskind, Southard, Crouch "Generating Custom High-Performance VLSI-Designs from Succinct Algorithmic Descriptions" Proc. Conference on Advanced Research in VLSI, MIT, January 1982 [4] Denyer, Renshaw, Bergmann "A Silicon Compiler for VLSI Signal Processors" ESSCIRC Proceedings, Brussels, 1982 [5] D. Johannsen "Bristle Blocks: A Silicon Compiler" Proc. 16th Design Automation Conference, June 1979 [6] M. Glesner, J. Schuck, H. Joepen "A Flexible Silicon Compiler for Digital Signal Processing Circuits" Proc. ICCD International Conf. on Computer Design, Port Chester, October 1984 [7] H. Joepen, M. Glesner "Architecture Construction for a General Silicon Compiler System" Proc. ICCD International Conf. on Computer Design, Port Chester, October 1985 [8] J. Schuck, M. Glesner, H. Joepen "ALGIC - A Flexible Silicon Compiler System" IEEE Workshop on VLSI Digital Signal Processing, Los Angeles, Nov. 1984 [9] M. Wei, H. Sholl "Extraction and Parallelism in Control Structures" IEEE Trans. on Computers, Vol. C31, No. 9, Sept. 1982

[10] T. Lange "Analyse, Optimierung und Transformation von hierarchischen Controller-Strukturen in einem Silicon Compiler System" Diplomarbeit, Institut fur Halbleiter-technik, TH Darmstadt, December 1985 [11] G. Grass "Some results on the design of regular structured sequential circuits" INTEGRATION Journal, 3(1985), pp. 189-210


A Simple and Accurate Node Reduction Technique for Interconnect Modeling in Circuit Extraction Shun-Lin Su, Vasant B. Rao, Timothy N. Trick Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 W. Springfield Avenue, Urbana, Ill. 61801

ABSTRACT A simple node reduction technique for RC tree networks is presented. This method computes the values of the resistances and capacitances in the reduced network using the concept of the Elmore time constant. Circuit simulations show that application of this technique can reduce complicated RC trees into simple lumped RC networks without significant loss in accuracy. Therefore, this technique is useful in circuit extraction, namely, it can be used to decrease the number of nodes in RC tree networks for modeling the interconnect regions in circuit layouts, thereby reducing the circuit simulation time in the next step of layout verification. A heuristic algorithm based on this technique has been implemented in our experimental circuit extractor. Simulation results show a good agreement in timing for RC networks obtained before and after applying this technique. REFERENCES [1] P. Penfield and J. Rubinstein "Signal Delay in RC Tree Networks" Proceedings of 18th DAC, 1981, pp. 613-617. [2] W. C. Elmore "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers" J. Appl. Physics, vol. 19, pp. 55-63, Jan. 1948. [3] R. Putatunda "AUTODELAY: A Program for Automatic Calculation of Delay in LSI/VLSI Chips" Proceedings of 19th DAC, 1982, PP. 616-621. [4] R. Putatunda "AUTODELAY: A Second-Generation Automatic Delay Calculation Program for LSI/VLSI Chips" Digest of Technical Papers, ICCAD 84, pp. 188-190, 1984. [5] E. Tamura, K. Ogawa, and T. Nakano "Path Delay Analysis for Hierarchical Building Block Layout System" Proceedings of 20th DAC, 1983, pp. 403-410. [6] N. Jouppi "Timing Analysis for NMOS VLSI" Proceedings of 20th DAC, 1983, pp. 411-418. [7] T. -M. Lin and C. A. Mead "Signal Delay in General RC Networks" IEEE Trans. on Computer-Aided Design, vol. CAD-3, no. 4, pp. 331-349, Oct. 1984. [8] J. L. Wyatt, C. A. Zukowski and P. Penfield, Jr. "Step Response Bounds for Systems Described By MMatrices, with Application to Timing Analysis of Digital MOS Circuits" Proceedings of 24th Conference on Decision and Control, pp. 1552-1557 Dec. 1985. [9] L. W. Nagel "SPICE2 : A Computer Program to Simulate Semiconductor Circuits" Electronics Research Report \#ERL-M520, University of California, Berkeley, May 1975.

[10] C. W. Ho, A. E. Ruehli, and P. A. Brennan "The Modified Nodal Approach to Network Analysis" IEEE Trans. on Circuits and Systems, vol. CAS-22, no. 6, pp. 504-509, June 1975. [11] J. L. Wyatt "Signal Delay in RC Mesh Networks" IEEE Trans. on Circuits and Systems, vol. CAS-32, no. 5, pp. 507-510, May 1985.


Charge Sharing Models for MOS Circuits Chorng-Yeong Chu, Mark Alan Horowitz Center for Integrated Systems, Stanford University, Stanford, California 94305

Abstract This paper addresses timing and glitch detection problems involving charge sharing in acyclic resistor-capacitor networks. Solutions to these problems are proposed and applied to real designs. Results are reported and compared with SPICE simulation. Our algorithms are intended for use in switch level simulators and timing verifiers which model transistors in digital VLSI designs as linear resistors. Computational complexity of our methods is also investigated. References [1] Chorng-Yeong Chu and Mark Alan Horowitz. Linear and Nonlinear Charge Sharing Models for MOS Circuits, Technical report in preparation, Stanford University. [2] Mark Alan Horowitz. Timing Models for MOS Circuits, PhD thesis, Stanford University, December 1983. [3] Norman Paul Jouppi. Timing Verification and Performance Improvement of MOS VLSI Designs, PhD thesis, Stanford University, October 1984. [4] Tzu-Mu Lin. A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems, PhD thesis, California Institute of Technology, August 1984. [5] Jorge Rubinstein, Paul Penfield, and Mark Alan Horowitz. Signal delay in RC tree networks, IEEE Transactions on Computer-Aided Design, CAD-2(3):202-211, July 1983. [6] Christopher Jay Terman. Simulation Tools for Digital LSI Design, PhD thesis, Massachusetts Institute of Technology, October 1983.


SPIDER - A CAD System for Checking Current Density and Voltage Drop in VLSI Metallization Patterns Joseph E. Hall, Dale E. Hocevar, Ping Yang Texas Instruments Inc. Semiconductor Process and Design Center, MS 369, P.O. Box 655621 Dallas, Texas 75265

Michael J. McGraw Texas Instruments Inc. Design Automation Division, MS 3668, P.O. Box 655621 Dallas, Texas 75265

ABSTRACT A system of CAD programs called SPIDER for insuring adequate current carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into DC electromigration equivalent values, and includes an algorithm for determining line width adjustments necessary for meeting specified median-time-to-failure (MTF) requirements. SPIDER also computes voltage drops with respect to a reference node and calls upon an optimization algorithm for correcting violations of a voltage drop specification. REFERENCES [1] J. W. McPherson and P. B. Ghate "A Methodology for the Calculation of Continuous DC Electromigration Equivalents from Transient Current Waveforms" Proceedings of the Symposium on Electromigration of Metals, published in J. Electrochemical Society, Vol 85-6, p. 64, 1985. [2] S. Chowdhury and M. A. Breuer "The Construction of Minimal Area Power and Ground Nets for VLSI Circuits" Proceedings of the 22nd Annual Design Automation Conference, 1985, pp. 794-797. [3] A. H. Shah, C. -P. Wang, R. H. Womack, J. D. Gallia, H. Shichijo, H. E. Davis, M. Elahy, S. K. Banerjee, G. P. Pollack, W. F. Richardson, D. M. Bordelon, S. D. S. Malhi, C. Pilch, B. Tran, and P. K. Chatterjee "A 4Mb DRAM with Cross-point Trench Transistor Cell" IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1986, pp. 268-269.


A Testing Strategy for Bit-Serial Arrays Joseph T. Scanlon, W. Kent Fuchs Computer Systems Group, Coordinated Science Laboratory, University of Illinois, Urbana, IL 61801

ABSTRACT Bit-serial processors are receiving increasing attention as alternatives to conventional bitparallel processors due to their efficient use of area and amenability to implementation by CAD algorithms. However, bit-serial processors and logic arrays, such as bit-serial multipliers, offer difficulties in testing due to their inherent low observability and controllability. In this paper, an approach to generation of efficient tests for iterative arrays of bit-serial circuits is presented. This approach is based on a comprehensive fault model and is appropriate for computer-aided test generation. Tests consist of a linear segment for initialization/propagation and a constant-length segment of test patterns repeating every k cells. The length of the initialization/propagation segment is typically n or 2n for an n-cell array. The testing strategy is illustrated by application to the PBS-1 bit-serial multiplier developed by the authors. REFERENCES [1] J. R. Jasica, S. Noujaim, R. Hartley, and M. J. Hartman "A Bit-Serial Silicon Compiler" Proc. of the IEEE Int'l Conf. on Computer-Aided Design, pp. 91-93, Nov. 1985 [2] J. T. Scanlon and W. K. Fuchs "High-Performance Bit-Serial Multiplication" Proc. of the IEEE Int'l Conf. on Computer Design (to appear), October 1986. [3] A. F. Murray, P. B. Denyer, and D. Renshaw "Self-Testing in Bit-Serial Parts: High Coverage at Low Cost" Proc. of the 1983 IEEE Int'l Test Conf., pp. 260-268, November 1983. [4] N. Kanopoulos "A Bit-Serial Architecture for Digital Signal Processing" IEEE Trans. on Circuits and Systems, vol. CAS-32, No.3, pp. 289-291, March 1985. [5] T. A. Davis, R. P. Kunda, and W. K. Fuchs "Testing of Bit-Serial Multipliers" Proc. of the IEEE Int'l Conf. on Computer Design, pp. 430-434, Oct. 1985. [6] F. C. Hennie "Fault Detecting Experiments for Sequential Circuits" Proc. of the Symposium on Switching Circuit Theory and Logical Design, pp. 95-110, 1964.


C-Testability for Generalized Tree Structures with Applications to Wallace Trees and Other Circuits Abhijit Chatterjee General Electric Research and Development Center, Schenectady, N.Y.

Jacob A. Abraham University of Illinois at Urbana-Champaign

ABSTRACT This paper investigates the C-testability of a class of generalized tree structures called Wallace Trees, identifying those circuit properties that make them testable with a constant number of vectors irrespective of the circuit size (C-testable). In these circuits, node fanout is allowed and assumptions regarding circuit regularity are not as rigid as in 1 or 2-D Iterative Logic Arrays. Some techniques for generating constant test sets are discussed. REFERENCES [1] Arthur D. Friedman "Easily Testable Iterative Systems" IEEE Transactions on Computers, Vol C-22, No 12, December 1973. [2] W.H Kautz "Testing for Faults in Cellular Logic Arrays" Proc, 8'th Annual Symp on Switching and Automata Theory, 1967. [3] Wu Tung Cheng "Testing and Error Detection in Iterative Logic Arrays" Ph.D Thesis, University of Illinois at Urbana-Champaign, 1985. [4] Francisco J.O Dias "Truth Table Verification of an Iterative Logic Array" IEEE Transactions on Computers, Vol C-25, No 6, June 1976. [5] John Paul Shen and Joel Ferguson "Easily Testable Array Multipliers" Proc of the 13'th Int'l Symposium on Fault Tolerant Computing, June 1983. [6] Hasan Elhuni, Anastasios Vergis, Larry Kinney "C-Testability of Two-Dimensional Arrays of Combinational Cells" Proc ICCAD, 1985. [7] J.A Abraham, D.D Gajski "Design of Testable Structures Defined by Simple Loops" IEEE Transactions on Computers, Vol C-33, pp 875-884, Nov 1981. [8] S.C Seth, K.L Kodandapani "Diagnosis of Faults in Linear Tree Networks" IEEE Transactions on Computers, Vol C-26, pp 29-33, Jan 1977. [9] Dadda L "Some Schemes for Parallel Multipliers" Alta Freq, pp 349-356, May 1965.


Fault Diagnosis of Switches in Wafer-Scale Arrays Yoon-Hwa Choi, Donald S. Fussell, Miroslaw Malek The University of Texas at Austin, Austin, Texas 78712

Abstract Recent advances in integrated circuit technology have motivated the search for ways to exploit the economic potential of wafer-scale integration. To cope with the expected low yield, researchers have proposed several designs of fault-tolerant array machines. A typical assumption in this research is that all switches employed are fault-free. In this paper, a computer-aided heuristic testing method of programmable switches for waferscale arrays is proposed. The method achieves high location capability of fault-free switches and fault-free links so that subsequent testing of processing elements can be done through the known fault-free paths. Only local neighbor-to-neighbor communication between cells is assumed. The performance of the method has been analyzed. References [1] C. Mead and L. Conway. Introduction to VLSI Systems. Reading, MA, Addison-Welsey, 1980. [2] H.T. Kung "Why systolic architectures?" IEEE Computer 15, 1 Jan. 1982, pp. 37-64. [3] H.T. Kung and M.S. Lam "Fault-tolerance and two-level pipelining in VLSI systolic arrays" MIT Conf. on Adv. Research in VLSI, Jan. 1984, pp. 74-83. [4] L. Snyder "Introduction to the configurable, highly parallel computer" Computer, Jan. 1982, pp. 47-56. [5] R.C. Aubusson and I. Catt "Wafer-scale integration- A fault-tolerant procedure" IEEE J. Solid-State Circuits SC-13, 3 June 1978, pp. 339-344. [6] D.S. Fussell and P.J. Varman "Fault-tolerant wafer-scale architectures for VLSI" Ninth Annual Symposium on Comput. Arch., April 1982, pp. 190-198. [7] J.W. Greene and A.El Gamal "Area and delay penalties in restructurable wafer-scale arrays" Third Caltech Conf. on Very Large Scale Integration 1983, pp. 165-183. [8] K.S. Hedlund and L. Snyder "Wafer-scale integration of configurable, highly parallel (CHIP) processors" 1982 Int'l Conf. Parallel Processing, pp. 262-264. [9] I. Koren "A reconfigurable and fault-tolerant VLSI multiprocessor array" Eighth Annu. Symp. on Computer Arch. (April 1981) pp. 425-440. [10] F.T. Leighton and C.E. Leiserson "Wafer-scale integration of systolic arrays" 23rd Annu. Symp. on Found. of Computer Science (1982) pp. 297-311. [11] T.E. Mangir and A. Avizienis "Fault-tolerant design for VLSI: Effect of interconnect requirements on yield improvements of VLSI design" IEEE Trans. Comput. C-31, 7 July 1982, pp. 609-615.

[12] F.B. Manning "An approach to highly integrated computer-maintained celluar arrays" IEEE Trans. Comput. C-26, 6, (June 1977) pp. 536-564.


YNCC: A New Algorithm for Device-Level Comparison between Two Functionally Isomorphic VLSI Circuits Yehuda Shiran SILVAR-LISCO/NCA Corporation, Santa Clara, CA

ABSTRACT A new program for the comparison of two netlists is described. The program differs from other netlist comparison programs in that it is capable of matching functionally isomorphic netlists while other programs can handle only topologically isomorphic netlists. YNCC handles important problems such as subcircuit nested permutation and arbitrary matching. This paper describes the algorithm for automatically deriving these permutations. YNCC is as fast as other comparison programs and its report is geared towards pinpointing inconsistencies quickly. References [1.] C. Ebeling and O. Zajicek "Validating VLSI Circuit Layout by Wirelist Comparison" (GEMINI) Digest of Tech. Papers ICCAD '83, pp. 172-173. [2.] R.L. Spickelmier and A.R. Newton "WOMBAT: A New Netlist Comparison Program" Digest of Tech. Papers ICCAD '83, pp. 170-171.


Validating the Functional Correctness of Incomplete Logic Circuits with the Aid of a Verification System. Nam Sung Woo AT&T Bell Laboratories, Murray Hill, New Jersey 07974.

This paper presents an attempt to fill the gap between top-down circuit design and bottom-up circuit verification. We report preliminary result on the functional verification of incomplete logic circuits with the aid of the VeryFun system [1], which is a rule-based functional verification system. Our approach of dealing with incomplete logic circuits is to allow users to tailor generic definitions provided by the verification system. References [1] N. Woo "A Prolog Based Verifier for the Functional Correctness of Logic Circuits" Proc. of ICCD85, pp.203-207, October 1985. [2] M. Fujita, H. Tanaka, T. Moto-oka "Verification with Prolog and Temporal Logic" Computer Hardware Description Languages and Their Applications, (T. Uehara, M. Barbacci eds.), pp.103-114, North-Holland, 1983. [3] F. Maruyama, M. Fujita "Hardware Verification" Computer, 18, 2, pp.22-32, February 1985. [4] H. Barrow "Proving the Correctness of Digital Hardware Designs" Proc. of AAAI-83, pp.17-21, 1983. [5] R. Shostak "Formal Verification of Circuit Designs" Computer Hardware Description Languages and Their Applications, (T. Ushara, M. Barbacci eds.), pp.13-20, North-Holland, 1983.


PROVE: Prolog Based Verifier Nagendra C. E. Srinivas, Vishwani D. Agrawal AT&T Bell Laboratories, Murray Hill, NJ 07974

ABSTRACT PROVE (PROlog based VErifier) is a rule based system that formally verifies the functional correctness of circuits. The procedure involves automatically generating Boolean expressions to characterize the functional description. From the logic level connectivity description of the implementation, another set of Boolean expressions is generated using symbolic simulation. The two sets of expressions are then checked for logical equivalence by performing the exclusive-or operation. The resulting Boolean expression is simplified until it reduces either to "false" or to some other expression. If the result of simplification is false, then the two expressions are logically identical. Written in C-Prolog, PROVE incorporates several simplification rules that employ pattern matching to speed up the Boolean simplification process. It also supports hybrid simulation performed by assigning logic values to certain inputs and symbols to the rest of the inputs. This reduces the memory requirements while further speeding up the expression comparison process. To facilitate the use of hybrid simulation, a strategy that analyzes the circuit and recommends input assignments of symbols or logic values has been developed. REFERENCES [1] M. A. d'Abreu "Gate-Level Simulation" IEEE Design & Test of Computers, Vol. 2, pp. 63-71, December 1985. [2] V.D. Agrawal "Synchronous Path Analysis in MOS Circuit Simulator" Proc. 19th Des. Auto. Conf., June 1982, pp. 629-635. [3] H. G. Barrow "Proving the Correctness of Digital Hardware Designs" Proceedings of the AAAI Conf., 1982, pp. 17-21. [4] N. S. Woo "A Prolog Based Verifier for the Functional Correctness of Logic Circuits" Proceedings of Int. Conf. on Computer Design (ICCD), October 1985, pp. 203-207. [5] F. Maruyama and M. Fujita "Hardware Verification" Computer, Vol. 18, pp. 22-32, February 1985. [6] N. Suzuki "Concurrent Prolog as an Efficient VLSI Design Language" Computer, Vol. 18, pp. 33-40, February 1985. [7] G. Odawara, M. Tomita, O. Okuzawa, T. Ohta, and Z. Zhuang "A Logic Verifier Based on Boolean Comparison" Proceedings of 23rd Design Automation Conference, June 1986, pp. 208-214. [8] S. Bapat and G. Venkatesh "Reasoning about Digital Systems using Temporal Logic" Proceedings of 23rd Design Automation Conference, June 1986, pp. 215-219.

[9] W. F. Clocksin and C. S. Mellish. Programming in Prolog, Second Edition, New York: SpringerVerlag, 1984. [10] J. Dussault, C-C Liaw, and M. Tong "A High Level Synthesis Tool for MOS Chip Design" Proc. 21st Design Automation Conf., June 1984, pp. 308-314. [11] D. L. Dietmeyer. Logic Design of Digital Systems, Second Edition, Boston, MA: Allyn and Bacon, 1978.


An Efficient Approach to Gate Matrix Layout D.K. Hwang, W.K. Fuchs, S.M. Kang Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL 61801

ABSTRACT Gate matrix layout was first introduced by Lopez and Law in 1980 [1]. It simplifies and unifies the layout procedure by using an orderly structure composed of intersecting rows and columns. This paper introduces the dynamic net-list representation, which allows netbinding to be delayed until the gate-ordering has been determined. Based on the dynamic net-list representation, a modified min-net-cut algorithm is presented to solve the gate ordering problem for gate matrix layouts. Area savings of 20% to 25% over published results are derived by using the min-net-cut algorithm with the dynamic net representation. The time complexity of the algorithm is shown to be O(N logN), where N is the total number of transistors and gate-net contacts of the circuit. REFERENCES [1] A. D. Lopez and H-F. S. Law "A Dense Gate Matrix Layout Method for MOS VLSI" IEEE Trans. Electron Devices, vol. ED-27, pp. 1671-1675, Aug. 1980. [2] S. M. Kang, R. H. Krambeck, H-F. S. Law, and A. D. Lopez "Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design" IEEE Trans. of Computer Aided Design, vol. CAD-2, No. 1, pp. 18-29, Jan. 1983. [3] O. Wing, S. Huang, and R. Wang "Gate Matrix Layout" IEEE Transactions On Computer-Aided Design, vol. CAD-4, No.3, pp. 220-231, July 1985. [4] J. T. Li "Algorithms for Gate Matrix Layout" IEEE Proc. of Intl. Symposium on Circuits and Systems, pp. 1013-1016, July 1983. [5] N. Deo, M. S. Krishnamoorthy, and M. A. Langston "Exact and Approximate Solutions for the Gate Matrix Layout Problem" Manuscript. [6] B. W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" Bell System Technical Journal, vol. 49, pp. 291-307, Feb. 1970. [7] C.M. Fiduccia and R.M. Mattheys "A Linear-Time Heuristic for Improving Network Partitions" Proc. 19th Design Automation Conference, pp. 175-181, 1982. [8] H. W. Leong and C. L. Liu "Permutation Channel Routing" IEEE Proc. Intl. Conf. on Computer Design, pp. 579-584, Oct. 1985. [9] A. Hashimoto and J. Stevens "Wire Routing by Optimizing Channel Assignment with large Apertures" Proc. ACM/IEEE Design Automation Workshop. pp. 155-169, July 1971. [10] D. G. Schweikert and B. W. Kernighan "A Proper Model for the Partitioning of Electrical Circuits" Proc. of the 9th Annual Design Automation Workshop, pp. 57-62, 1972.


A New Algorithm for Gate Matrix Layout H. W. Leong Department of Computer Science, University of Illinois at Urbana-Champaign, 1304 W. Springfield, Urbana, IL 61801

Abstract We consider the layout of MOS circuits in the style of Gate Matrix in minimum area. This problem is known to be NP-complete. Previous algorithms solve the problem in a number of independent sub-steps. In this paper, we propose a generalized formulation that combines many of these sub-steps. We show that the new formulation is indeed superior to the previous formulation. We also present an algorithm for the problem in the new formulation that simultaneously considers gate permutation, dynamic binding, and net merging. Our algorithm employs the technique of simulated annealing and uses a cost function that minimizes both the layout area and the total wire length. The algorithm has been implemented and tested using various benchmark problems from the literature. In all the problems tested, our algorithm performs as well as, or better than previous methods. In particular, for a large problem with 71 gates, 131 nets, and 306 transistors, our algorithm obtained a 27.5% improvement in the layout area; from 40 tracks to 29 tracks. References [Golu80] Golumbic, M. C. Algorithmic Graph Theory and Perfect Graphs, Academic Press, (1980). [HaSt71] Hashimoto, A. and J. Stevens "Wire Routing by Optimizing Channel Assignment with Large Apertures" Proc. 8th Design Automation Workshop, IEEE, (1971), 155-169. [HwFK86] Hwang, D. K., W. K. Fuchs, and S. M. Kang "An Efficient Approach to Gate Matrix Layout" this proceeding. [KaFu79] Kashiwabara, T., and T. Fujisawa "An NP-complete Problem on Interval Graphs" Proc. IEEE Symp. on Circuits and Systems, (1979), 82-83. [KiGV83] Kirkpatrick, S., C. D. Gelatt, and M. P. Vecchi "Optimization by Simulated Annealing" Science (1983), Vol. 220, 671-680. [LeLi83] Leong, H. W., and C. L. Liu "A New Channel Routing Problem" Proc. 20th Design Automation Conf., IEEE, (1983), 584-590. [LeLi85] Leong, H. W., and C. L. Liu "Permutation Channel Routing" Proc. IEEE Intl. Conf. on Computer Design (1985), 579-584. [LeWL85] Leong, H. W., D. F. Wong, and C. L. Liu "A Simulated-Annealing Channel Router" Proc. IEEE Intl. Conf. on Computer-Aided Design (1985), 226-228. [Li83] Li, J. T. "Algorithms for Gate Matrix Layout" IEEE Intl. Symp. on Circuits and Systems (1983), 1013-1016.

[LoLa80] Lopez, A. D., and H. F. S. Law "A Dense Gate Matrix Layout Method for MOS VLSI". IEEE Trans. on Electronic Devices (1980), Vol. ED-27, No. 8, 1671-1675. [OhMK79] Ohtsuki, T., H. Mori, E. Kuh, O. Kashiwabara, and T. Fujisawa "One-Dimensional Logic Gate Assignment and Interval Graphs" IEEE Trans. on Circuits and Systems, (1979), Vol. CAS-26, No. 9, 675684. [VeKi83] Vecchi, M. P., and S. Kirkpatrick "Global Wiring by Simulated Annealing". IEEE Trans. on Computer-Aided Design (1983), Vol. CAD-2, 215-222. [WiHW85] Wing, O., S. Huang, and R. Wang "Gate Matrix Layout". IEEE Trans. on Computer-Aided Design (1985), Vol. CAD-4, No. 3, 220-231. [Wing82] Wing, O. "Automated Gate Matrix Layout". Intl. Symp. on Circuits and Systems (1982), 681685. [Wing83] Wing, O. "Interval Graph Based Gate Matrix Layouts". IEEE Intl. Conf. on Computer-Aided Design (1983), 84-85. [WoLL86] Wong, D. F., H. W. Leong, and C. L. Liu "Multiple PLA Folding by the Method of Simulated Annealing" Proc. 1986 Custom Integrated Circuits Conf., IEEE, (1986), 351-355.


Improved Gate Matrix Layout Shuo Huang, Omar Wing Columbia University Department of Electrical Engineering, 1312, Mudd New York, New York 10027

Abstract A new approach to gate matrix layout is presented. It consists of two stages: the determination of an optimal gate sequence and an assignment of nets to rows such that the nets are realizable. The gate sequence algorithm is based on Asano's approximate search [8]. Modifications are made to it to take into account constraints of transistor sizing, serial subcircuit's conflicts [9], I/O gates, and I/O nets. The net assingment algorithm, called "zone-net assignment algorithm", assigns nets to a minimum number of rows determined by the gate sequence. It also provides a means to resolve vertical conflicts in the layout. Power connections are implemented using the first or the second layer of metal depending on the fabrication technique to be used. Results of examples show that the new approach can acheive a considerable improvement compared to earlier algorithms [5] [6] [7] [9]. Reference [1] A.D. Lopez and H-F S. Law "A Dense Gate Matrix Layout Method for MOS VLSI" IEEE Trans. Electron Devices, vol. ED-27, pp.1671-1675, Aug. 1980. [2] O. Wing "Automated Gate Matrix Layout" in Proc. of Intl. Symposium on Circuits and Systems, Rome, Italy, pp.681-685, May 1982. [3] T. Ohtsuki, H. Mori, E.S. Kuh, T. Kashiwabara, and T. Fujisawa "One-demensional Logic Gate Assignment and Inteval Graphs" IEEE Trans. on Circuits and Systems; vol. CAS-26. No. 9, pp.675-684, Sept. 1979. [4] T. Kashiwabara and T. Fujisawa "An NP-complete Problem on Inteval Graphs" in Proc. 1979 IEEE Int. Symp. Circuits and Systems, Tokyo, Japan, pp.82-83, July 1979. [5] O. Wing "Interval Graph Based Gate Matrix Layout" in Proc. 1983 IEEE Int. Conf. CAD, Santa Clara, CA, Sept. 1983. [6] J.T. Li "Algorithms for Gate Matrix Layout" in Proc. 1983 IEEE Int. Symp. Circuits and Systems, Newport Beach, CA, pp.1013-1016, 1983. [7] S. Kirkpatrick, C.D. Gelatt, Jr., and M.P. Vecchi "Optimization by simulated annealing" Science, vol.220, pp.671-680, 13 May 1983. [8] T. Asano "An Optimum Gate Placement Algorithm for MOS One-demensional Arrays" J. Digital Syst., vol.VI, pp.1-27, 1981. [9] O. Wing, S. Huang, and R. Wang "Gate Matrix Layout" IEEE Trans. on CAD, vol. CAD-4, pp.220-231, July 1985. [10] Ellen Yoffa, Peter S. Hauge "ACORN: A Local Customization Approach to DCVS Physical Design" Proc. 1985 Design Automation Conference, pp.32-38, 1985.

[11] A. Hashimoto and J. Stevens "Wire Routing by Optimizing Channel Assignment within Large Apertures" Proc. 8th Design Automation Workshop, pp.155-169, 1971. [12] T. Yoshimura and E.S. Kuh "Efficient Algorithms for Channel Routing" IEEE Transactions on CAD., vol. CAD-1, No.1, pp.25-35, Jan 1982. [13] A.V. Aho. The Design and Analysis of Computer Algorithms, Addison-Wesley Publishing Company, pp.172-176, 1974.


A Heuristic Algorithm for Gate Matrix Layout Koh'ichi Nakatani, Takashi Fujii, Tohru Kikuno, Noriyoshi Yoshida Faculty of Engineering, Hiroshima University, Higashi-Hiroshima, 724 Japan

ABSTRACT For the gate matrix layout problem, several heuristic algorithms have already been developed. These algorithms consider the area needed for only either p-MOSFETs or nMOSFETs. This paper proposes a new heuristic algorithm to solve a gate matrix layout problem for circuits composed of NAND gates, NOR gates and inverters. The goal of the proposed algorithm, called Algorithm GML, is the minimization of the area needed for both pMOSFETs and n-MOSFETs. The time complexity of Algorithm GML is 0(n3 · g), where n and g are the numbers of gate lines and gate nets, respectively. Algorithm GML is implemented on the Data General ECLIPSE MV/4000 computer system. The experimental results show that Algorithm GML is very effective in totally minimum area and sufficiently useful from a practical point of view. REFERENCES [1] T. Fujii, et al. 'A heuristic algorithm for one-dimensional gate assignment’ Proc. 1985 Int. Symp. on Circuits and Systems, pp.1451-1454, 1985. [2] T. Fujii, et al. 'A heuristic algorithm for gate line assignment in gate matrix' TGCAS85-151, IECEJ, pp.25-32, 1986. [3] A. Hashimoto and J. Stevens 'Wire routing by optimizing channel assignment within large apertures' Proc. 8th Design Automation Workshop, pp.155-169, 1971. [4] J.-T. Li 'Algorithms for gate matrix layout' Proc. 1983 Int. Symp. on Circuits and Systems, pp.10131016, 1983. [5] A.D. Lopez and H.-F.S. Law 'A dense gate matrix layout method for MOS VLSI' IEEE J. Solid-State Circuits, SC-15, 4, pp.736-740, 1980. [6] K. Ueda, et al. 'Layout strategy, standardization, and CAD tools' in 'Layout Design and Verification' Advances in CAD for VLSI, Vol. 4, ed. T. Ohtsuki, North-Holland, 1986. [7] A. Weinberger 'Large scale integration of MOS complex logic: A layout method' IEEE J. Solid-State Circuits, SC-2, 4, pp.182-190, 1967. [8] O. Wing, et al. 'Gate matrix layout' IEEE Trans. on Computer-Aided Design, CAD-4, 3, pp.220-231, 1985.


Fast Fault Simulation in Combinational Circuits Kurt J. Antreich, Michael H. Schulz Institute of Computer Aided Design, Department of Electrical Engineering, Technical University of Munich, D-8000 Munich 2, West Germany

Abstract Based upon the well-known concept of restricting fault simulation to the fanout stems and combining it with a critical path tracing method inside the fanout free regions of the circuit, proposals will be made to further accelerate fault simulation and fault grading. These proposals aim at a parallel evaluation of the binary signal values by utilizing the full length of machine words for bit-string operations and at a reduction of the number of fanout stems for which a fault simulation has to be carried out. References [1] E. B. Eichelberger and T. W. Williams "A Logic Design Structure for LSI Testability" Proceedings of the 14th Design Automation Conference, pp. 462-468, June 1977. [2] Se June Hong "Fault Simulation Strategy for Combinational Logic Networks" 8th International Symposium on Fault-Tolerant Computing, Digest of Papers, pp. 96-99, 1978. [3] D. B. Armstrong "A Deductive Method for Simulating Faults in Logic Circuits" IEEE Transactions on Computers, Vol. C-21, pp. 464-471, May 1972. [4] Takao Nishida, Shunsuke Miyamoto, Tokinori Kozawa, and Katsuya Sato "RFSIM: Reduced Fault Simulator" IEEE International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 1315, November 1985. [5] S. Koppe and C.W. Starke "Logiksimulation komplexer Schaltungen fur sehr groBe Testlangen" NTGFachberichte GroBintegration, pp. 73-80, VDE-Verlag GmbH, Marz 1985. [6] John A. Waicukauski, Edward B. Eichelberger, Donato O. Forlenza, Eric Lindbloom, and Thomas McCarthy "Fault Simulation for Structured VLSI" VLSI Systems Design, pp. 20-32, December 1985. [7] Franc Brglez, Philip Pownall, and Robert Hum "Application of Testability Analysis: From ATPG to Critical Delay Path Tracing" Proceedings 1984 International Test Conference, pp. 705-712, October 1984. [8] Franc Brglez "A Fast Fault Grader: Analysis and Applications" Proceedings 1985 International Test Conference, November 1985. [9] M. Abramovici, P. R. Menon, and D. T. Miller "Critical Path Tracing - An Alternative to Fault Simulation" Proceedings of the 20th Design Automation Conference, pp. 214-220, June 1983. [10] Sunil K. Jain and Vishwani D. Agrawal "STAFAN: An Alternative to Fault Simulation" Proceedings of the 21st Design Automation Conference, pp. 18-23, June 1984. [11] Vishwani D. Agrawal "Sampling Technique for Determining Fault Coverage in LSI Circuits" Journal of Digital Systems, Vol. V, No. 3, pp. 189-202, 1981.

[12] Melvin A. Breuer and Arthur D. Friedman "Diagnosis & Reliable Design of Digital Systems" Computer Science Press, Inc., 1976. [13] F. Brglez and H. Fujiwara "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran" Proceedings IEEE International Symposium on Circuits and Systems; Special Session on ATPG and Fault Simulation, June 1985.


Advanced Techniques for Concurrent Multilevel Simulation Silvano Gai CENS - CNR Politecnico di Torino, Corso Duca degli Abruzzi 24 I-10129 Torino Italy

Fabio Somenzi SGS Microelettronica Central R & D, Via Camillo Olivetti 2 I-20041 Agrate Brianza (Mi) Italy

Ernst Ulrich Digital Equipment Corporation, 100 Minuteman Road Andover, MA USA

Abstract This paper describes new techniques crucial for the concurrent simulation of large circuits described at multiple levels of abstraction (RT, gate, switch). Work reported in [1] [2] [3] [4] [5] [6] [7] [8] [9] [12] is extended. Based on the techniques of Multi-List Traversal, Frontier Traversal, Fraternal Events, List Events, Levelizing, and Ordered Activity Propagation, advances are presented in simulation speed, accuracy and generality. Relative to classical selective trace logic simulation the settling process often occurring in combinational parts of typical networks can usually be avoided. This suppresses the unnecessary simulation of irrelevant activity but maintains the accuracy of structural (interconnect) logic simulation. As implemented in MOZART this allows, for example, the simulation of 7744 faulty machines in less than twice the time used for the good machine. Detailed experimental results are reported. The approach presented is general - not restricted to Fault Simulation - and thus applicable to the new area of Concurrent Case Simulation. REFERENCES [1] M. Abramovici, M.A. Breuer, K. Kumar "Concurrent Fault Simulation and Functional Level Modeling" Proceedings of 14th DAC, New Orleans (LA), June 1977, pp. 128-137. [2] R.E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Trans. on Comput., Vol. C-33, Feb. 1984, pp. 160-177. [3] M.D. Schuster, R.E. Bryant "Concurrent Fault Simulation of MOS Digital Circuits" Proc. of Conference on Advanced Research in VLSI, Massachusetts Institute of Technology (MA), January 1984. [4] E. Ulrich, M. Kearney, G. Tellier, S. Demba "Design Verification for Very Large Digital Networks based on Concurrent Simulation and Clock Suppression" Proc. IEEE Conference on Computer Design, 1983. [5] E. Ulrich "Event Manipulation for Discrete Simulations requiring Large Number of Events" Communications of the ACM, Vol. 21, No. 9, September 1978, pp. 777-785. [6] N.D. Phillips, J.G. Tellier "Efficient Event Manipulation - the Key to Large Scale Simulation" Proc. International Test Conference, Cherry Hill (NJ), October 1978, pp. 266-273. [7] E. Ulrich "Table-Lookup Techniques for Fast and Flexible Digital Logic Simulation" Proc. 17th DAC, Minneapolis (MINN), June 1980, pp. 560-563.

[8] E. Ulrich "Concurrent Simulation at the Switch, Gate and Register Levels" Proc. International Test Conference, Philadelphia (PA), November 1985. [9] E. Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven "High speed Concurrent Fault Simulation with Vectors and Scalars" Proc. 17th DAC, Minneapolis (MINN), June 1980, pp. 374380. [10] D.M. Schuler, R.K. Cleghorn "An Efficient Method of Fault Simulation for Digital Circuit Modeled from Boolean Gates and Memories" Proc. 14th DAC, New Orleans (LA), June 1977, pp. 230-238. [11] M.A. Breur, A.D. Friedman "Diagnosis and Reliable Design of Digital Systems" Computer Science Press, Rockville, MD, 1976. [12] S. Gai, F. Somenzi, M. Spalla "Fast and Coherent Simulation with Zero Delay Elements" to appear in IEEE Transactions on CAD/ICAS. [13] F. Brglez, H. Fujiwara "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN" Special Session on ATPG and Fault Simulation, Proc. 1985 IEEE Int. Symp. Circuits and Systems, Kyoto, Japan, June 5-7, 1985.


WRAP: An Algorithm for Hierarchical Compression of Fault Simulation Primitives John F. Guzolek, William A. Rogers, Jacob A. Abraham Computer Systems Group Coordinated Science Laboratory, University of Illinois, Urbana, Illinois 61801

Abstract WRAP is a programmed algorithm which takes a hierarchical circuit description and recursively wraps (compresses) leaf primitives into their parent nodes. The result is a circuit representation with fewer, more complex primitives, yielding faster fault simulation with the concurrent hierarchical fault simulator CHIEFS. WRAP works with both combinational and sequential circuits. Wrapped circuit primitives retain all functional and fault behavior of the underlying primitives of which they are composed. Results obtained from a 24 bit fast multiplier composed of 3900 gate-level primitives show a factor of three speedup for fault simulation of the wrapped (493 primitives) versus the unwrapped circuit (3900 gate-level primitives). References [1] T. W. Williams and K. P. Parker "Design for Testability - A Survey" Proceedings of the IEEE, vol. 71, pp. 98-112, January 1983. [2] W. A. Rogers and J. A. Abraham "A Performance Model for Concurrent Hierarchical Fault Simulation" Proceedings International Conference on Computer Aided Design, November 1986. [3] J. F. Guzolek "WRAP: An Algorithm for Hierarchical Compression of Fault Simulation Primitives" CSG Technical Report CSG-53, University of Illinois, Urbana-Champaign, 1986. [4] W. A. Rogers and J. A. Abraham "High-Level Hierarchical Fault Simulation Techniques" in Proceedings of the ACM Spring Computer Science Conference, New Orleans, pp. 89-97, March 1985. [5] W. A. Rogers and J. A. Abraham "CHIEFS: A Concurrent Hierarchical and Extengible Fault Simulator" Proceedings International Test Conference, pp. 710-716, November 1985. [6] T. M. McWilliams, J. R. Rubin, L. C. Widdoce, and S. Correl. SCALD II User's Manual, Lawrence Livermore Laboratory, 1979. [7] David Waltz "Understanding Line Drawings of Scenes with Shadows" in The Pyschology of Computer Vision, New York, 1975. [8] Patrick Henry Winston. Artificial Intelligence. Reading, Mass.: Addison-Wesley, 1977, pp. 45-112.


A Performance Model for Concurrent Hierarchical Fault Simulation William A. Rogers, Jacob A. Abraham Computer Systems Group Coordinated Science Laboratory, University of Illinois, 1101 W. Springfield Ave. Urbana, Illinois 61801

ABSTRACT This paper develops a performance model for concurrent hierarchical fault simulation based on the number of module evaluations performed during the simulation. This model shows why hierarchical concurrent fault simulation runs in approximately n log(n) time as opposed to approximately n2 time for flat concurrent fault simulation. Experimental data for a 4000 gate mantissa multiplier is presented which support the feasibility of this model. REFERENCES [1] W. A. Rogers and J. A. Abraham "High-Level Hierarchical Fault Simulation Techniques" Proceedings of the ACM Spring Computer Science Conference, pp. 89-97, March 1985. [2] W. A. Rogers and J. A. Abraham "CHIEFS: A Concurrent Hierarchical and Extensible Fault Simulator" Proceedings of the International Test Conference, pp. 710-716, November 1985. [3] Y. H. Levendel and P. R. Menon "Fault-Simulation Methods - Extensions and Comparison" Bell System Technical Journal, vol. 60, pp. 2235-2259, November 1981. [4] H. Y. Chang, S. G. Chappell, C. H. Elmendorf, and L. D. Schmidt "Comparison of Parallel and Deductive Fault Simulation Methods" IEEE Transactions on Computers, vol. C-23, pp. 1132-1138, November 1974. [5] M. A. Breuer and A. D. Friedman. Diagnosis and Reliable Design of Digital Systems. Rockville, Maryland: Computer Science Press, 1976. [6] P. Goel "Test Generation Costs Analysis and Projections" in 17th Design Automation Conference, Minneapolis, pp. 77 - 84, June 1980. [7] T. W. Williams and K. P. Parker "Design for Testability - A Survey" Proceedings of the IEEE, vol. 71, pp. 98-112, January 1983. [8] J. F. Guzolek, W. A. Rogers, and J. A. Abraham "WRAP: An Algorithm for Hierarchical Compression of Fault Simulation Primitives" in Proceedings of the International Conference on Computer-Aided Design, Santa Clara, Ca., November 1986.


Logic Minimization Using Simulated Annealing Jimmy Lam Department of Computer Science, Yale University, New Haven, CT 06520

Jean-Marc Delosme Department of Electrical Engineering, Yale University, New Haven, CT 06520

Abstract This paper describes a simple multi-level logic minimizer for NMOS implementations of multiple-output functions that employs the simulated annealing technique for global optimization. Simulated annealing provides high quality results and a high degree of design flexibility through freedom in the choice of objective function. However heavy computational requirements have hindered its use. We reduce the computation time through the selection of efficient movement strategies that uncover sharable subexpressions and the application of a new optimal annealing schedule. References [1] R. Brayton, G. Hachtel, C. McMullen and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984. [2] J.D. Ullman. Computational Aspects of VLSI, Section 8.3, Computer Science Press, 1984. [3] H.M. Lipp "Methodical Aspects of Logic Synthesis" Proc. IEEE, Vol. 71, No.1, pp. 88-97, Jan. 1983. [4] S. Kirkpatrick, C. Gelatt Jr. and M. Vecchi "Optimization by Simulated Annealing" IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 1982. [5] C. Rowen and J. Hennessy "SWAMI: A Flexible Logic Implementation System" Proc. 22nd Design Automation Conference, pp. 169-175, 1985. [6] J. Lam and J-M. Delosme "Optimal Annealing Schedule" Report 8608, Department of electrical Engineering, Yale University, Sept. 1986. [7] S. White "Concepts of Scale in Simulated Annealing" Proc. IEEE Int. Conf. on Computer Design, pp. 646-651, Oct. 1984. 8] D. Mitra, F. Romeo and A. Sangiovanni-Vincentelli "Convergence and Finite-Time Behavior of Simulated Annealing" Proc. 24th Conf. on Decision and Control, pp. 761-767, Dec. 1985. [9] The TTL Data Book for Design Engineers, 2nd Edition, Texas Instruments Inc., 1976.


Exact Minimization of Multiple-Valued Functions for PLA Optimization Richard Rudell, Alberto Sangiovanni-Vincentelli University of California, Berkeley, CA 94720

Abstract We present an algorithm for determining the minimum representation of an incompletelyspecified, multiple-valued input, binary-valued output, function. The overall strategy is similar to the well-known quine-McCluskey algorithm; however, the techniques used to solve each step are new. The advantages of the algorithm include a fast technique for detecting and eliminating from further consideration the essential prime implicants and the totally redundant prime implicants, and a fast technique for generating a reduced form of the prime implicant table. The minimum cover problem is solved with a branch and bound algorithm using a maximal independent set heuristic to control the selection of a branching variable and the bounding. Using this algorithm, we have derived minimum representations for several mathematical functions whose unsuccessful exact minimization has been previously reported in the literature. The exact algorithm has been used to determine the efficiency and solution quality provided by the heuristic minimizer Espresso-MV [1]. Also, a detailed comparison with McBoole [2] shows that the algorithm presented here is able to solve a larger percentage of the problems from a set of industrial examples within a fixed allocation of computer resources. References [1] R. L. Rudell and A. Sangiovanni-Vincentelli "Espresso-MV: Algorithms for Multiple-Valued Logic Minimization" Proc. IEEE Cust. Int. Circ. Conf. (CICC), Portland, May, 1985. [2] Michel R. Dagenais, Vinod K. Agarwal and Nicholas C. Rumin "McBoole: A New Procedure for Exact Logic Minimization" IEEE Trans. on CAD, January 1986, 229-238. [3] H. Fleisher and L. I. Maissel "An Introduction to array logic" IBM Journal of Research and Development 19 (March 1975), 98-109. [4] Tsutomu Sasao "Input Variable Assignment and Output Phase Optimization of PLA's" IEEE Transactions on Computers c-33 (October 1984), 879-894. [5] E. J. McCluskey "Minimization of Boolean Functions" Bell System Technical Journal 35 (November 1956), 1417 1444. [6] S. J. Hong, R. G. Cain and D. L. Ostapko "MINI: A Heuristic Approach for Logic Minimization" IBM Journal of Research and Development, September 1974, 443-458. [7] R. K. Brayton, Curt McMullen, G. D. Hachtel and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984. [8] G. D. Hachtel, A. R. Newton and A. Sangiovanni-Vincentelli "An Algorithm for Optimal PLA Folding" IEEE Trans. on CAD, January 1982, 63-76.

[9] W. V. Quine "A Way to Simplify Truth Functions" Am. Math. Monthly 62 (November 1955), 627. [10] Tsutomu Sasao "An Application of Multiple-Valued Logic to a Design of Programmable Logic Arrays" Proc. 8th Int. Symp. on Mult. Val. Logic (ISMVL), 1978. [11] Y. H. Su and P. T. Cheung "Computer Minimization of multi-valued Switching functions" IEEE Transactions on Computers c-21 (1972), 995-1003. [12] R. L. Rudell "Multiple-Valued Logic Minimization for PLA Synthesis" Masters Report, University of California, Berkeley, 1986. [13] Tsutomu Sasao "An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs" IEEE Transactions on Computers c-34 (February 1985), 131-140. [14] P. Tison "Generalization of Consensus Theory and Application to the minimization of Boolean Functions" IEEE Transactions on Computers c-16 (August 1967), 446. [15] R. K. Brayton and et. al. "Fast Recursive Boolean Function Manipulation" Proc. Int. Symp. Circ. Syst. (ISCAS), Rome, May 1982, 58. [16] J. P. Roth. Computer Logic, Testing, and Validation, Computer Science Press, 1980. [17] Tsutomu Sasao "Tautology Checking Algorithms for Multiple-Valued Input Binary Functions and Their Application" Proc. 14th Int. Symp. on Mult. Val. Logic (ISMVL), 1984. [18] Tsutomu Sasao "Comparison of Minimization Algorithms for Multiple-Valued Expressions" Draft, 1982.


Multiple-Level Logic Optimization System R. Brayton IBM Research, Yorktown NY

E. Detiens Phillips Research Labs., Sunnyvale CA

S. Krishna, T. Ma, P. McGeer, L. Pei University of California, Department of Electrical Engineering and Computer Sciences, Berkeley, CA 94720

N. Phillips Digital Equipment Corp., Hudson MA

R. Rudell, R. Segal, A. Wang, R. Yung, A. Sangiovanni-Vincentelli University of California, Department of Electrical Engineering and Computer Sciences, Berkeley, CA 94720

Abstract MIS is a multi-level logic synthesis and minimization system and is an integral part of the Berkeley Synthesis Project. MIS starts from a description of a combinational logic macro-cell and produces an optimized set of logic equations which preserves the inputoutput behavior of the macro-cell. The system includes algorithms for minimizing the area required to implement the logic equations, and a global timing optimization step which is used to change the form of the logic equations along the critical path in order to meet system-level timing constraints. This paper provides an overview of the optimization system including the input language, the algorithms which minimize the area of the implementation, and the algorithms used to re-structure the logic network to meet the system-level timing constraints. Although the system is still under development, pieces of an industrially designed chip have been re-synthesized with MIS and the results compare favorably with the manual designs. References [1] D. Harrison, P. Moore, R. Spickelmier and A. R. Newton "Data Management and Graphics Editing in the Berkeley Design Environment" Proc. IEEE Int. Conf. on Comp. Aid. Des. (ICCAD), Nov. 1986. [2] Randy H. Katz, Editor, Proceedings of CS292i: Implementation of VLSI Systems, University of California, Spring 1985. [3] D. Patterson and C. Sequin "A VLSI RISC" Computer 15-9 (1982), 8-21. [4] R. K. Brayton and Curt McMullen "The Decomposition and Facorization of Boolean Expressions" Proc. Int. Symp. Circ. Syst. (ISCAS), Rome, May 1982, 49-54. [5] R. K. Brayton, Curt McMullen, G. D. Hachtel and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.

[6] R. K. Brayton and Curt McMullen "Synthesis and Optimization of Multistage Logic" Proc. IEEE Int. Conf. on Comp. Des. (ICCD), Rye, 1984, 23-28. [7] K. Bartlett, R. Brayton, R. Jacoby, G. Hachtel, R. Rudell, A. Sangiovanni-Vincentelli and A. Wang "Multiple-Level Minimization" Proc. Int. Conf. Comp. Des. (ICCD), October 1986, To appear.


TDS: An Expert System to Automate Timing Design for Interfacing VLSI Chips in Microcomputer Systems Atsushi Kara NEC Corporation, Tokyo, Japan

Ravi Rastogi, Kazuhiko Kawamura Center for Intelligent Systems, Vanderbilt University, Nashville, TN 37235

ABSTRACT This paper presents a new approach for automating timing design for interfacing VLSI chips in microcomputer systems based on the manufacturer's specification sheets. A Prolog-based expert system called TDS (Timing Design System) which incorporates the heuristic knowledge of the hardware designer is described. TDS is a rule-based system which interprets the specification sheets of VLSI chips and can synthesize, diagnose and verify timing charts at the level of the expert designer. TDS is a novel implementation of the functional modeling of the VLSI based on given timing specifications in contrast to other models which require structural information. The approach can be used for design aid, design verification, diagnosis/repair of faulty circuits, etc. Thus, the system is a powerful CAD tool for hardware engineers. REFERENCES [1] A.R. Newton and A.L. Sangiovanni-Vincentelli "Computer-Aided Design for VLSI Circuits" Computer, 19:38-60, April 1986. [2] W.M. vanCleemput, and H. Ofek "Design Automation for Digital Systems" Computer, 17(10):114-121, Oct. 1984. [3] R.B. Hitchcock, Sr., G.L. Smith, and D.D. Cheng "Timing Analysis of Computer Hardware" IBM Journal of Research and Development, pp. 100-105, January 1982. [4] M.A. Breuer, (Ed.) Design Automation of Digital Systems, Volume One: Theory and Techniques, Prentice-Hall Inc., 1972. [5] M.J. Flynn et al., (Ed.) Microcomputer System Design, Springer-Verlag 1984. [6] T.I. Kirkpatric and N.R. Clark "PERT as an Aid to Logic Design" IBM Journal of Research and Development, pp. 135-141, March 1966. [7] S. Ghosh "Software Techniques in Ada for High-Level Hardware Descriptions" IEEE Circuits and Devices Magazine, pp. 32-47, March 1986. [8] H.W. Carter "Computer-Aided Design of Integrated Circuits" Computer, 19:19-36, April 1986. [9] W.F. Cloksin, and C.S. Mellish. Programming in Prolog, 2nd Edition, Springer-Verlag, 1984. [10] F. Pereira (Ed.) C-Prolog User's Manual, EdCAAD, University of Edinburgh, February 1984. [11]

IC

Memory

1985,

IA-107G,

JAN.-10-85P,

NEC

Corporation,

Japan.


An AI System for Improving the Performance of Complex Transmission Line Networks Evangelos Simoudis AI Applications Group, Digital Equipment Corporation, 77 Reed Rd., Hudson, MA., 01749

Barbara Bee, Richard Evans, Donald Vonada Signal Transmission Technology Group, Digital Equipment Corporation, 77 Reed Rd., Hudson, MA., 01749

Abstract A technology independent methodology for troubleshooting circuits with signal integrity problems is presented. Two key aspects of this methodology are: 1) its range of applicability, and 2) the use of AI technology to accomplish the troubleshooting process. Troubleshooting signal integrity problems in digital networks is a difficult process. These problems include violations of logic device noise margins, and timing requirements as a result of transmission line effects and coupling between signal paths. The troubleshooting process has been divided to an analysis and a redesign task. AI techniques were used for the implementation of the methodology. In particular, object-oriented programming was used for the representation of the circuits. Rule-based, systems were used for the implementation of the analysis and redesign tasks. Signal integrity problems have been organized into a hierarchy and an architecture has been devised for its implementation. REFERENCES [1] VLSI SYSTEMS DESIGN Staff "Survey of Circuit Board CAD Systems" in VLSI Systems Design, Vol. 7, No. 3, March 1986, pp. 62-77. [2] Poltz, J., Wexler, A. "Transmission-Line Analysis of PC Boards" in VLSI Systems Design, Vol. 7, No. 3, March 1986, pp. 38-43. [3] Vladimirescu, A., Zhang, K., Newton, A.R., Pederson, D. O., Sangiovanni-Vincentelli, A. "SPICE Version 2G User's Guide" Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA., 1981. [4] Homren, W. K., Winters, S. M., Conlin, M. J. "A Digital Network Analysis Assistant" to appear in Proceedings of NAECON'86, Dayton, Ohio, 1986. [5] Allen, E., Trigg, R., Wood, R., Maryland Franzlisp Environment, TR 11226, Computer Science Dept., University of Maryland, Nov. 1983. [6] Fickas, S. "Design Issues in a Rule-Based System" in ACM Symposium on Programming Languages and Programming Environments, Seattle, 1985. [7] Simoudis, E., and Fickas, S. "The Application of Knowledge-Based Design" in Proc. IEEE ICCAD, Nov. 1985.


SYMBL: An Optimized Layout System For Partially Symmetric Functions Joseph Ja'Ja', Sau-Mou Wu Department of Electrical Engineering, University of Maryland, College Park Md 20742

Abstract In this paper we present a new software system SYMBL written in C to layout Boolean functions. SYMBL is based on a novel strategy that first partitions the set of input variables into equivalence classes with the given functions being symmetric with respect to each equivalence class. A heuristic minimizer then finds a near optimal symmetric cover for the functions. Finally, the last phase performs the placement and routing designed to optimize our layout structure consisting of a combination of Weinberger arrays, PLA's and special tree blocks. SYMBL will provably outperform any PLA-based approach for any set of functions that have a moderate degree of symmetry. References [1] A. Weinberger "Large Scale Integration of MOS Complex Logic: A Layout Method" IEEE J. Solid State Circuits SC-2(Dec. 1967), 182-190. [2] C. Rowen & J.L. Hennessy "SWAMI: A Flexible Logic Implementation System" Proc. 22nd Design Automation Conference (1985). [3] J. Ja'Ja', S.M. Wu & C. Chakrabarti "A new approach for compiling Boolean functions" Electrical Engineering Department, University of Maryland, Technical report, Feb. 1986. [4] Kohavi. Switching and Finite Automata Theory, McGraw-Hill, Reading, 1978. [5] Das & Sheng "On Detecting Total or Partial Symmetry of Switching Functions" IEEE T. Computer C20 (1971), 352-355. [6] S.J. Hong, R.G. Cain & D.L. Ostapko "MINI: a heuristic approach for logic minimization" IBM J. of Res. and Dev. 18 (September 1974), 443-458. [7] R. Brayton, G.D. Hachtel, C.T. McMullen & A.L. Sangiovanni-Vincentelli. Logic Minimization Algorithm for VLSI Synthesis, Kluwer Academic Publishers, Reading, 1984. [8] B.T. Preas & W.M. vanCleenput "Placement algorithms for arbitarily shaped blocks" Design Automation Conference (1979). [9] U. Lauther "A min-cut placement algorithm for general assemblies based on a graph representation" Design Automation Conference (1979). [10] N.J. Nilsson "Principles of Artificial Intelligence" Tioga Publishing Co, Reading (1980).


A Standard Cell Placement Algorithm with Predictive Row Width Equalization Masami Murakata, Atsushi Tanaka, Masaaki Yamada, Takashi Mitshuhashi VLSI Research Center, TOSHIBA Corporation, 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 210 JAPAN

ABSTRACT This paper describes a novel placement method, which realizes predictive row width equalization in addition to chip size minimization. The method, which takes into account the capacity of over-the-cell wirings, predicts the number of required feedthrough cells and makes the row width, including the added area, uniform. This proposed method yielded up to 9 percent chip size reduction, compared with a method without predictive row width equalization. A placer, based on this method, has been implemented in a VLSI layout system and applied to VLSI design. References [1] R. Putatunda., et al "An Optimized and Unique Placement Approach for Very Large Semicustom IC Designs" Proc. of ICCD 85., pp440-444, 1985. [2] C. Sechen and A. Sangiovanni-Vincentelli "The TimberWolf Placement and Routing Package" IEEE. J. of Solid-State Circuit. vol. sc-20. no.2. pp510-521, April 1985. [3] T. Kambe., et al "A Placement Algorithm for Polycell LSI and Its Evaluation" Proc. 19th DA Conf., pp655-661, 1982. [4] T. Hiwatashi, M. Yamada and T. Mitsuhashi "A Hierarchical Routing System for VLSIs Including Large Macros" Proc. of CICC 86., pp285-288, 1986. [5] A. E. Dunlop and B. W. Kernighan "A Procedure for Placement of Standard-Cell VLSI Circuits" IEEE Trans. on CAD, vol. CAD-4, no. 1, pp92-98, Jan. 1985. [6] T. Kambe., et al "A Global Routing Scheme for Poly-cell LSI" Proc. of ISCAS 85., pp187-190, 1985. [7] M. Yamada, T. Hiwatashi, T. Mitsuhashi and K. Yoshida, "A Multi Layer Router for Standard Cell LSIs" Proc. of ISCAS 85., pp191-194, 1985. [8] M. A. Breuer "Min-Cut Placement" J. Design Automation & Fault-Tolerant Computing. vol. 1, no. 4, pp343-362, Oct. 1977. [9] Sungo Kang "Linear Ordering and Application to Placement" Proc. 20th DA Conf., pp457-464, 1983. [10] B. W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" Bell Syst. Tech. J., vol. 49, no. 2, pp291-308, 1970.

1986 ICCAD, 378-380

A New Simulated Annealing Algorithm for Standard Cell Placement Lov K. Grover AT&T Bell Laboratories, Murray Hill NJ 07974

Abstract Simulated annealing is a powerful general purpose optimization technique, based on the annealing process used for crystallization in physical systems. Its main disadvantage is the long time it takes to converge. This paper shows how the probabilistic nature of the algorithm can be exploited to reduce the computer time the algorithm takes, by doing cost calculations approximately instead of exactly. This idea has been used to design a standard cell placement algorithm in LTX2, a VLSI layout system, and it yields a 20-40% improvement in routing area as compared to a min-cut placement algorithm. Preliminary comparisons show that the program compares favorably (3 to 5 times faster for results of the same quality) with other simulated annealing placement programs. REFERENCES [1] S. Kirckpatrick "Optimization by simulated annealing" Science, vol. 220, pp.671-680, 1983. [2] C. Sechen & A Sangiovanni Vincentelli "The Timberwolf Placement and Routing Package" Proc. 1984 Custom Integrated Circuit Conference, Rochester, 1984. [3] Lov K. Grover "Standard Cell Placement using Simulated Annealing with Approximate Calculations" AT&T Bell Labs Technical Memorandum, April 10, 1986 (submitted for publication to IEEE Transactions on Computer Aided Design). [4] S. Goto "An efficient algorithm for the two-dimensional placement problem in electrical circuit layout" IEEE Transactions on Circuits & Systems, vol. CAS-28, No. 1, January 1981. [5] A. E. Dunlop & B. W. Kernighan "A Placement procedure for Polycell VLSI Circuits" Proceedings of the ICCAD, pp.1245-1248, 1983. [6] A. E. Dunlop "Automatic layout of Gate Arrays" ISCAS, May 1983, pp.1245-1248. [7] B.W. Colbry & J. Soukup "Layout aspects of The VLSI Microprocessor Design" International Symposium on Circuits and Systems, May 1982, pp.1214-1228.


An Efficient General Cooling Schedule for Simulated Annealing M. D. Huang Philips Research Labs. Signetics Corporation, Sunnyvale, CA

F. Romeo, A. Sangiovanni-Vincentelli Dept. of Electrical Engineering and Computer Science, University of California, Berkeley

Abstract An efficient annealing process for simulated annealing has been developed. The unique features of this new process include (1) a dynamic temperature decrement control to avoid quenching, (2) a dynamic adjustment of the Markov-Chain length to assure establishment of equilibrium, and (3) reliable detection of frozen condition. Since only statistical quantities are used as the control parameters, the schedule is applicable to general combinatorial optimization problems. Applications to the traveling-salesman problem and the standard-cell placement problem indicate a speedup of two to ten times when compared with algorithms and programs available in the literature. References [AAR85] E.H.L. Aarts and P.J.M. van Laarhoven "Statistical Cooling: A General Approach To Combinatorial Optimization Problems" Philips J. Res., Vol. 40, pp.193-226, 1985. [FEL70] W. Feller "An Introduction to Probability Theory and Applications" J. Wiley, 3rd Edition, 1970. [GEM84] S. Geman, D. Geman "Stochastic Relaxation, Gibbs Distributions, and the Bayesian Restoration of Images" IEEE Trans. Pattern An. and Mach. Intel., Vol 6 pp. 721-741, 1984. [GRE84] J.W. Greene and K.J. Supowit "Simulated Annealing Without Rejected Moves" IEEE Trans. on Computer Aided Design, Vol. CAD-5, No.1 Jan. 1986. Port Chester, New York, pp.658-663, 1984. [KIR83] S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi "Optimization by Simulated Annealing" Science, Vol. 220, N. 4598, pp. 671-680, 13 May 1983. [LUN84] M. Lundy, A. Mees "Convergence of the Annealing Algorithm" Simulated Annealing Workshop, Yorktown Heights, April 1984. [MIT85] D. Mitra, F. Romeo and A. Sangiovanni-Vincentelli "Convergence and Finite-Time Behavior of Simulated Annealing" Proc. 1985 Cont. Dec. Conf., Dec. 1985 also J. of Applied Probability, to appear. [OTT84] R. H.J.M. Otten and L.P.P.P. van Ginneken "Simulated Annealing: The Algorithm" unpublished manuscript, 1984. [REI65] F. Reif "Statistical and Thermal Physics" McGraw Hill Inc., New York, 1965, p. 213. [ROM85] F. Romeo, A. Sangiovanni Vincentelli "Probabilistic Hill Climbing Algorithms: Properties and Applications" 1985 Chapel Hill Conference on Very Large Scale Integration, H. Fuchs ed. Computer Sciences Press, Chapel Hill, N.C., 1985. [SEC84] C. Sechen and A.L. Sangiovanni-Vincentelli "The TimberWolf Placement and Routing Package" Proc. 1984 Custom Int. Circuit Conf., May 1984.

[WHI84] S. White "Concept of Scale in Simulated Annealing" IEEE Int. Conf. on Computer Design, Port Chester, New York, pp. 646-651, 1984.


A High Performance Hardware Accelerator for Circuit Level Simulation of VLSI Circuits David M. Lewis Department of Electrical Engineering, University of Toronto, Toronto, Canada

Abstract Switch level simulation of VLSI circuits often produces poor timing estimates and logical errors. Circuit level simulation is more accurate, but generally too expensive to perform on entire VLSI design. Awsim-2 is a hardware accelerator which is capable of performing circuit level simulation of large VLSI circuits. It makes use of a multiprocessor structure and a a high bandwidth interconnection network. Each processor uses a simple circuit simulation algorithm that exploits circuit inactivity. This allows good processor utilization with fine grained partitioning of the circuit among the processors. Interactive circuit simulations of hundreds of thousands of transistors are possible in fractions of a second per simulated clock cycle. As a result, circuit level simulation is possible at speeds previously only possible in gate level simulation accelerators. REFERENCES [1] David M. Lewis "A Hardware Engine for Analogue Mode Simulation of MOS Digital Circuits" Proceedings of the 22nd IEEE Design Automation Conference, 1985 [2] C.J. Terman "Simulation Tools For Digital LSI Design" MIT Laboratory for Computer Science, MIT/LCS/304 [3] Randal E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" California Institute of Technology, 5065:TR:93, 1983 [4] Jeffery M. Arnold "The Parallel Simulation of Digital LSI Circuits" MIT Laboratory for Computer Science, MIT/LCS/TR-333 [5] Bryan D. Ackland, Sudhir R. Ahuja, Teri L. Lindstrom, and Deborah J. Romero "CEMU - A Concurrent Timing Simulator" Proceedings of ICCAD, 1985 [6] W. J. Dally "The MOSSIM Simulation Engine Architecture and Design" Caltech Report \#5123:TR:84, 1984 [7] A. Vlaimirescu and S. Lui "The Simulation of MOS Integrated Circuts using SPICE2" Electronics Research Laboratory Memo UCB/ERL M80/7, University of California, Berkeley, 1980 [8] G. F. Pfister "The Yorktown Simulation Engine, Introduction" Proceedings of the 19th Design Automation Conference, 1982, pp. 51-54 [9] Z. Barzilai, L. Huisman, G. Silberman, D. Tang and L. Woo "Simulating Pass Transistor Circuits Using Logic Simulation Machines" Proceedings of the 20th Design Automation Conference, 1983, pp. 157-163 [10] Zycad Corp LE-004 technical product description

[11] David R. Jenkins and Steven G. Morton "Transistor Level Simulation Using the Zycad Logic Evaluator" Proceedings of ADEE East Conference, Oct. 1985, pp 154-163 [12] B. R. Chawla, H. K. Gummel, and P. Kozak "MOTIS - A MOS Timing Simulator" IEEE Transactions on Circuits and Systems, 22-12, Dec 1975, pp 751-756 [13] A. R. Newton and A. L. Sangiovani-Vincentelli "Relaxation-Based Electrical Simulation" IEEE Transactions on Computer Aided Design, 3-4, Oct 1984, pp 308-331 [14] B. Hennion, P. Senn, and D. Coquelle "A New Algorithm for Third Generation Circuit Simulators: The One Step Relaxation Method" Proceedings of the 22nd Design Automation Conference, 1985, pp 137143


Hardware Implementation of Velvet on the Hitachi S-810 Supercomputer Shigeo Nagashima, Takayuki Nakagawa, Koichiro Omota, Shunsuke Miyamoto Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan

Shun Kawabe, Yoji Tsuchiya Kanagawa Works, Hitachi, Ltd., Hadano, Kanagawa 259-13, Japan

ABSTRACT A newly developed vectorized processing system for logic verification, called VELVET, is described, in particular its hardware implementation on the HITACHI S-810 supercomputer. In order to develop in a short period a VLSI or a computer utilizing a number of LSIs, logic errors in the LSIs must be eliminated as much as possible before manufacturing. Logic simulation is a key technology to detect logic errors, but requires much CPU time for a software simulator to simulate the entire logic of a computer and to detect logic malfunctions. The VELVET system can simulate a great number of logic gates more than 100 times faster than a software simulator. This high performance has been realized due to a new vectorized algorithm and six vector instructions which are added to the S-810 vector processor to support this algorithm. REFERENCES [1] Pfister G. F., et al.'The Yorktown Simulation Engine: Introduction' 19th DA Conf. 1982 pp51-54. [2] Denneau, M. M., et al. 'The Yorktown Simulation Engine: Architecture and Hardware Description' 19th DA Conf. 1982 pp55-59. [3] Howard, J. K., et al. 'Introduction to the IBM Los Gatos Logic Simulation Machine' ICCD'83 1983 pp580-583. [4] Burggraff, T., et al. 'The IBM Los Gatos Logic Simulation Machine Hardware' ICCD'83 1983 pp584587. [5] Sasaki, T., et al. 'HAL: A Block Level Hardware Logic Simulator' 20th DA Conf. 1983 pp150-156. [6] Nagashima, S., et al. 'Design Consideration for a High-speed Vector Processor: The HITACHI S-810' ICCD'84 1984 pp238-243. [7] Ulrich, E. G. 'Exclusive Simulation of Activity in Digital Networks' Communications of ACM, Vol. 12, No. 2, pp102-110 (1969).


MegaFAULT: A Mixed-Mode, Hardware Accelerated Concurrent Fault Simulator Terence Chan, Edwin Law Daisy Systems Corporation

ABSTRACT In this paper we describe a hardware accelerated fault simulator, MegaFAULT, which has much higher speed and capacity than most software fault simulators, and it is more flexible than hardwired faulth simulators in its mixed-mode simulation and varieties of fault modeling capabilities. Specifically, MegaFAULT can fault simulate circuits consist of switch-level, functional-level, gate-level, behavioral-level and physical-level primitives, so that both IC and system-level designers can use the same fault simulator. Moreover, MegaFAULT employs a fault repartitioning methodology to overcome the unpredictable memory requirement problem of concurrent fault simulation algorithm. MegaFAULT also has the capabilities to support incremental fault simulation and distributed fault simulation. And the user can suppress unknown faulty signals propagation, as well as setting the number of times a fault is potentially detected before it is dropped in MegaFAULT. Finally, anothor advantage of MegaFAULT is its integration into a complete CAE design environment, where the same design database and a common library is used for schematic capture, logic simulation, timing verification, testability analysis, fault simulation and tester interfacing. REFERENCES [1.] G. Catlin and W. Paseman "Hardware Acceleration Of Logic Simulation Using A Data Flow Architecture" Proceeding ICCAD, November 1985, pp. 130-132 [2.] D.M. Schuler and R.K, Cleghorn "An Efficient Method Of Fault Simulation for Digital Circuits Modeled from Boolean Gates And Memories" Proc. 14th Design Automation Conference, June 1977, pp. 230 - 238 [3.] P. A. Stoll "PMX: A Hardware Solution To The VLSI Model Availability Problem" IEEE International Conference On Computer Design: VLSI In Computer, October 1985, pp. 719 – 723


A VLSI Artwork Analysis System Using Dedicated Hardware and Syntactic Pattern Recognition E. van Willigen, R. Nouta Delft University of Technology, Mekelweg 4 - 2628 CD Delft, The Netherlands

ABSTRACT We present a method for VLSI artwork analysis, based on techniques from the field of Syntactic Pattern Recognition (SPR). Fast implementation of this method is possible, because the proposed method can be used in conjunction with special purpose hardware. An artwork analysis system which is capable of circuit extraction, transistor extraction and measurement and parasitic capacitance measurement has been built to demonstrate this method. Experience with some LSI circuits is described. References [1] H. G. Adshead "Towards VLSI complexity: The DA algorithm scaling problem: Can special hardware help?" Proc. 19th Design Automation Conf., pp. 339-344 (June 1982). [2] S. J. Hong and R. Nair "Wire routing machines - New tools for VLSI physical design," Proc. IEEE 71 pp. 57-65 (Jan. 1983). [3] T. N. Mudge, R. A. Rutenbar, R. M. Lougheed, and D. E. Atkins, "Cellular image processing techniques for VLSI circuit layout validation and routing" Proc. 19th Design Automation Conf., pp. 537543 (June 1982). [4] C. Mead and L. Conway. Introduction to VLSI Systems, Addison-Wesley, Reading, Mass. (1980). [5] Thomas G. Szymanski and Christopher J. van Wyk "Goalie: A Space Efficient System for VLSI Artwork Analysis" IEEE Design an Test of Computers, pp. 64-72 (June 1985). [6] Anoop Gupta "ACE: A Circuit Extractor" Proc. of the 20th Design Automation Conference, pp. 721725 (1983). [7] Henry S. Baird "Fast algorithms for LSI artwork analysis" Journal of Design Automation and FaultTolerant Computing 2(2) pp. 179-209 (1978). [8] Ulrich Lauther "An O(N log N) algorithm for boolean mask operations" Proc. of the 18th Design Automation Conference, pp. 55-562 (1981). [9] Franco Preparata and Jurg Nievergelt "Plane-sweep algorithms for intersecting geometric figures" Communications of the ACM 25(10) pp. 739-747 (1982). [10] C. M. Baker and C. Terman "Tools for Verifying Integrated Circuit Designs" LAMBDA 1(3)(1980).

[11] James A. Wilmore "A hierarchical bit-map format for the representation of IC masks" Proc. of the 17th Design Automation Conference, pp. 585-580 (1980). [12] James A. Wilmore "Efficient boolean operations on IC masks" Proc. of the 18th Design Automation Conference, pp. 571-579 (1981). [13] Thomas G. Szymanski and Christopher J. van Wyk "Space Efficient Algorithms for VLSI Artwork Analysis" Proc. of the 20th Design Automation Conference, pp. 734-739 (1983). [14] Larry Seiler "A hardware assisted design rule check architecture" Proc. of the 19th Design Automation Conference, pp. 235-238 (1982). [15] R. A. Rutenbar, T. N. Mudge, and D. E. Atkins "A Class of Cellular Architectures to Support Physical Design Automation" IEEE Transactions on Computer-aided Design CAD-3(4)(Oct. 1984). [16] K. S. Fu. Syntactic Methods in Pattern Recognition, Academic Press, New York (1974). [17] R. C. Gonzalez and M. G. Thomason. Syntactic Pattern Recognition, An Introduction, AddisonWesley, Reading, Mass. (1978). [18] J. Serra. Image Analysis and Mathematical Morphology, Academic Press, London (1982). [19] K. Preston, M. J. B. Duff, S. Levialdi, P. Norgren, and J. Toriwaki "Basics of Cellular Logic with Some Applications in Medial Image Processing" Proc. IEEE 67 pp. 826-856 (May 1979). [20] P. P. Jonker and R. P. W. Duin. Considerations on a VLSI Architecture for Cellular Logic Operations, Pattern Recognition Group of the Department of Applied Physics, Delft University of Technology, The Netherlands [21] P. P. Jonker. VLSI for CLO, Pattern Recognition Group of the Department of Applied Physics, Delft University of Technology, The Netherlands [22] P. E. Danielsson and S. Levialdi "Computer Architectures for Pictorial Information Systems" Computer 14(11) pp. 53-67 (Nov. 1981). [23] R. M. Lougheed, D. L. McCubbrey, and S. R. Sternberg "Cytocomputers: Architectures for parallel image processing" Proc. IEEE Workshop on Picture Data Description and Management, (Aug. 1980). [24] Brian W. Kernighan and Dennis M. Ritchie. The C Programming Language, Prentice-Hall (1978). [25] F. de Lange and J. Annevelink "A Technology Independent Hierarchical Layout to Circuit Extractor Using a Finite State Approach" pp. 2.51-2.92 in The Integrated Circuit Design Book, ed. P. Dewilde, Delft University Press, Delft, The Netherlands (1986). [26] A. J. van Genderen and A. C. de Graaf "sls: a switch-level timing simulator" pp. 2.93-2.146 in The Integrated Circuit Design Book, ed. P. Dewilde, Delft University Press, Delft, The Netherlands (1986).


A Data Structure Processor for VLSI Geometry Checking Erik C. Carlson, Rob A. Rutenbar Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA 15213

Abstract This paper describes a processor architecture to support VLSI mask checking. Rather than recast the entire verification task in hardware, we identify primitives around which geometry checking tools can be built, and accelerate these primitives. The architecture is a based on a restructuring of classical scanline-sweep methods for direct hardware interpretation. Boolean operations and region numbering are supported for masks with restricted oblique geometry. Simulation benchmarks suggest practical speedups are attainable. References [1] T. Blank "A Survey of Hardware Accelerators Used in Computer-Aided Design" IEEE Design and Test, August 1984, pp. 21-39. [2] E. Carlson "A Data Structure Processor for VLSI Geometry Checking" Master's thesis, Dept. of Electrical and Computer Engin., Carnegie Mellon Univ., 1986. [3] P. T. Chapman and K. Clark Jr. "The Scanline Approach to Design Rules Checking: Computational Experiences" Proc. 21st Design Automation Conf., 1984, pp. 235-241. [4] A. L. Fisher, et al. "Design of the PSC: A Programmable Systolic Chip" in Proc. Third Caltech Conf. on VLSI Systems, R. Bryant, ed., Computer Science Press, 1983, pp. 287-302. [5] R. Kane and S. Sahni "A Systolic Design Rule Checker" Proc. 21st Design Automation Conf., 1983, pp. 243-250. [6] U. Lauther "An O(N log N) Algorithm For Boolean Mask Operations" Proc. 18th Design Automation Conf., 1981, pp. 555-562. [7] C. Mead and L. Conway. Introduction to VLSI Systems, Addison-Wesley, 1980. [8] J. Nievergelt, F.P. Preparata "Plane-Sweep Algorithm For Intersecting Geometric Figures" CACM, 1982, pp. 739-741. [9] T. G. Szymanski and C. J. Van Wyk "GOALIE: A Space-Efficient System for VLSI Artwork Analysis" IEEE Trans. CAD of ICs and Systems, 1984, pp. 278-280.


A Range Searching Sub-System Used to Perform Efficient VLSI Design Checks. J. Berger, G. Mazare Laboratoire de Genie Informatique/IMAG/CNRS, BP 68 38402. Saint Martin d'heres cedex France

ABSTRACT I.C. design methodologies in use today have a number of serious defects with respect to design verifications. Most of them defer design rule checks (DRC) and electrical connectivity tests until the end of the design process. This is necessary since the possibility of another item overlapping a prechecked item cannot be ruled out. This paper proposes a new method using design hierarchy, signal connectivity information, and geometrical data retrieval to perform incremental design rule checking and electrical node extraction upon cell hierarchies, in which subcells and basic items may overlap and be stacked several levels deep at any point of the design. These algorithms can be used in an interactive mode, offering the designer one-line design rule checks, electrical connectivity tests and signal checking all at hand, as well as in a final (global) mode. REFERENCES [1] J.L. BENTLEY "Multidimensional binary search trees used for associative searching" Communications of the ACM, Vol.18, Number 9, Sept.1975 [2] J.L. BENTLEY and J.H. FRIEDMAN "Data structures for range searching" ACM Computer Survey, Vol.11, NO4, 1979 [3] A.V. AHO, J.E. HOPCROFT and J.D. ULMAN "The Design and Analysis of Computer Algorithms" ADDISON-WESLEY, Reading, Mass. 1974. [4] A.M. BEYLS, B. HENNION, J. LECOURVOISIER, G. MAZARE, A. PUISSOCHET "A DESIGN METHODOLOGY BASED UPON SYMBOLIC LAYOUT AND INTEGRATED CAD TOOLS" 19th Design Automation Conference 1982. [5] J. BERGER "Quad-Tree hierarchy for circuit data retrival in structured design" IEEE International Conference on Computer Design 1985 [6] L.V. CORBIN "Custom VLSI Electrical Rule Checking in an intelligent terminal" 18th. DAC 81. [7] S. JOHNSON "Hierarchical design validation Based on Rectangles". 1982 Conference On Advanced Research on VLSI. M.I.T. [8] GERSON KEDEM "The Quad-tree: A Data Structure for Hierarchical On-Line Algorithms" 19th. DAC 82 [9.] S.MCCABE "A Program for Hierarchical Verification of VLSI Layouts" VLSI Design Aug.84. [10] J.MCGRATH and T.WHITNEY "Design Integrity and Immunity checking" 1980. [11] J.OUSTERHOUT "Corner stitching A data structuring technique for VLSI layout tools" IEEE Trans.CAD, Vol.CAD-3, pp 87-100, Jan.1984 [12] F. PREPARATA and M. SHAMOS "Computational geometry" Reading, Springer-Verlag 1985.

[13] J.B. ROSENBERG "Geographical Data Structures Compared A Study of Data Structures Supporting Regions Queries" Transaction on Computer Aided Design, VOL.CAD.4, NO.1, Jan.1985 [14] HANAN SAMET "The Quadtree and Related Hierarchical Data Structure" Computing Surveys, Vol.16, No.2, June 1984 [15] M.SCHLAG, Y.Z. LIAO and C.K. WONG "An Algorithm for optimal two-dimensional compaction of VLSI layouts" INTEGRATION, The VLSI journal 1, 1983. [16] G.S. TAYLOR AND JOHN K.OUSTERHOUT "Magic's Incremental design Rule Checker" 21st Design Automation Conference, 1984. [17] T.WHITNEY "A Hierarchical Design Rule Checking Algorithm" first quarter 81, LAMBDA.


Circuit Placements and Cost Bounds by Eigenvector Decomposition Jon Frankle, Richard M. Karp Computer Science Division, University of California Berkeley, CA 94720

Abstract We present new methods for finding low-cost circuit placements and for proving nearoptimality. The problem is to assign given modules to a stipulated set of positions so that the total of squared connection distances is minimized. We use linear algebra to express the problem in a transformed geometric setting. Each possible placement is represented by a point, and we seek the point furthest from the origin. We give a simple procedure that takes any "probe direction" in the transformed space and produces the legal placement whose point has the maximum projection in that direction. We describe a placement algorithm based on sequences of probes. For random graphs in which each edge appears independently with probability d/n, this algorithm consistently gives placements of slightly lower cost than does exhaustive pairwise interchange. For these graphs, previously known lower bounds on placement cost were a factor of two or three below the best costs produced by algorithms. Again using probes, we give lowerbound techniques that narrow the cost gap to less than 20%. References [1] D. Avis "A survey of heuristics for the weighted matching problem" Networks, vol. 13, pp. 475-493, 1983. [2] J.P. Blanks "Near-optimal placement using a quadratic objective function" in Proceedings of the 22nd Design Automation Conference, pp. 609-615, June 1985. [3] J.P. Blanks "Use of a quadratic objective function for the placement problem in VLSI design" Ph.D dissertation, Univ. of Texas at Austin, April 1985. [4] H.L. Charney and D.L. Plato "Efficient partitioning of components" Proceedings of the 5th Annual Design Automation Workshop, pp. 16-1 to 16-21, July 1968. [5] C.-K. Cheng and E.S. Kuh "Module placement based on resistive network optimization" IEEE Transactions on Computer-Aided Design, vol. CAD-3, no. 3, pp. 218-225, July 1984. [6] K.M. Hall "An r-dimensional quadratic placement algorithm" Management Science, vol. 17, no. 3, pp. 219-229, Nov. 1970. [7] K.M. Just, J.M. Kleinhans, and F.M. Johannes "On the relative placement and the transportation problem for standard-cell layout" in Proceedings of the 23rd Design Automation Conference, pp. 308-313, June 1986. [8] S. Kirkpatrick, C.D. Gelatt, Jr., and M.P. Vecchi "Optimization by simulated annealing" Science, vol. 220, no. 4598, May 13, 1983. [9] J. Munkres "Algorithms for the assignment and transportation problems" J. SIAM vol. 5, no. 1, March 1957.

[10] D.G. Schweikert and B.W. Kernighan "A proper model for the partitioning of electrical circuits" in Proceedings of the 9th Design Automation Workshop, pp. 56-62, June 1972. [11] C. Sechen and A. Sangiovanni-Vincentelli "TimberWolf3.2: a new standard cell placement and global routing package" Proceedings of the 23rd Design Automation Conference, pp. 423-439, June 1986. [12] J.E. Stevens "Fast heuristic techniques for placing and wiring printed circuit boards" Ph.D. dissertation, Computer Science Department, Univ. of Illinois, 1972.


Trivial Global Wiring of Large Chips: A Statistical Analysis Gregory B. Sorkin IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598

Abstract A 2-dimensional stochastic model of the global wiring of a VLSI chip or macro is defined; prominent in the definition is the property that the probability of connecting two pins is solely a function of the distance between the cells containing them. Given a global wiring, row and column widths (and macro size) are defined by the widest cells in each row and column. A lower bound is placed on the expected size of the macro with perfect wiring. An upper bound is placed on the expected size of the macro with a trivial (all "L"s) wiring scheme. From these bounds it is shown that the fraction difference between the trivial and perfect wirings approaches 0 as 1n(\#columns) References [Cr46] H. Cramer. Mathematical Methods of Statistics, Princeton, N.J.: Princeton University Press, 1946. [Do79] W. E. Donath "Placement and average interconnection lengths of computer logic" IEEE Trans. Circuits Syst., CAS-26, pp. 272-277, Apr. 1979. [Do81] W. E. Donath "Wire length distributions for placements of computer logic" IBM J. Res. Develop., vol. 25, no. 3, pp. 152-155, May 1981. [El81] A. El-Gamal "Two-dimensional stochastic model for interconnections in master slice integrated circuits"IEEE Trans. Circuits Syst., CAS-28, no.2, pp. 127-138, Feb. 1981. [Fe82] M. Feuer "Connectivity of random logic" IEEE Trans. Comput., C-31, no. 1, pp. 29-33, Jan. 1982. [HMD78] W. Heller, W. F. Mikhail, and W. E. Donath "Prediction of wire space requirements for LSI" in Design Automation and Fault-Tolerant Computing, pp. 117-144, 1978. [SaPa86] S. Sastry and A.C. Parker "Stochastic models for wireability analysis of gate arrays" IEEE Trans. Computer-Aided Design, CAD-5, No. 1, January 1986.


Genetic Placement James P. Cohoon, William D. Paris Department of Computer Science, University of Virginia, Charlottesville, VA 22903

ABSTRACT A placement algorithm, Genie, is presented for the assignment of modules to locations on VLSI chips. Genie is an adaptation of the genetic algorithm technique that has traditionally been a tool of the artificial intelligence community. We applied Genie to several different circuit instances and its solutions were observed to be uniformly good and in several cases optimal. REFERENCES [1] M. A. Breuer, Min-Cut Placement Design Automation & Fault-Tolerant Computing 1, 4 (October 1977), 343-362. [2] C. K. Cheng and E. S. Kuh. Module Placement Based on Resistive Network Optimization, IEEE Transactions on Computer-Aided Design CAD-3, 3 (July 1984), 218-225. [3] J. P. Cohoon and W. D. Paris. Genie: A Genetic Placement Algorithm, 86-14, Department of Computer Science, University of Virginia, 1986. [4] A. E. Dunlop and B. W. Kernighan. A Procedure for Placement of Standard-Cell VLSI Circuits, IEEE Transactions on Computer-Aided Design CAD-4, 1 (January 1985), 92-98. [5] J. J. Grefenstette, ed. Proceedings of an International Conference on Genetic Algorithms and Their Applications, Pittsburgh, PA, 1985. [6] M. Hanan and J. M. Kurtzberg. A Review of the Placement and Quadratic Assignment Problems, SIAM Review 14, 2 (April 1972), 324-342. [7] J. H. Holland. Adaptation in Natural and Artificial Systems, University of Michigan Press, Ann Arbor, MI, 1975. [8] S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi. Optimization by Simulated Annealing, Science 220, 4598 (May 13, 1983), 671-680. [9] N. R. Quinn. The Placement Problem as Viewed from the Physics of Classical Mechanics, 12th Design Automation Conference Proceedings, Boston, MA, 1975, 173-178.


CONES: A System for Automated Synthesis of VLSI and Programmable Logic from Behavioral Models Charles E. Stroud, Ronald R. Munoz, David A. Pierce AT&T Bell Laboratories, Naperville, Illinois 60566

ABSTRACT This paper describes CONES, an automated synthesis system that generates general sequential logic from behavioral models written in "C", then implements the resultant logic in the form of both VLSI structures (standard cell and Programmable Logic Array) and Programmable Logic Device (PLD) based circuit packs. CONES has been used in combination with behavioral simulation to design several semi-custom VLSI devices and production circuit packs. In this paper we present an overview of the CONES system and the results of its application to four production designs. REFERENCES [1] D. Gregory, K. Bartlett, A. de Geus, G. Hachtel "SOCRATES: A system for Automatically Synthesizing and Optimizing Combinational Logic" Proc. 23rd DAC, 1986, pp 79-85. [2] T. Sasao "MACDAS: Multi-level AND-OR Circuit Synthesis Using Two-Variable Function Generators" Proc. 23rd DAC, 1986, pp 86-93. [3] W. H. Joyner, L. H. Trevillyan, D. Brand, T. A. Nix, S. C. Gundersen, "Technology Adaptation in Logic Synthesis" Proc. 23rd DAC, 1986, pp 94-100. [4] T. Blackman, J. Fox, C. Roseburgh "The SILC Silicon Compiler: Language and Features" Proc. 22nd DAC, 1985, pp 232-237. [5] D. E. Krekelberg, G. E. Sobelman, C. S. Jhon "Yet Another Silicon Compiler" Proc. 22nd DAC, 1985, pp 176-182. [6] J. V. Rajan, D. E. Thomas "Synthesis By Delayed Binding of Decisions" Proc. 22nd DAC, 1985, pp 367-374. [7] C. Rowen, J. L. Hennessy "SWAMI: A Flexible Logic Implementation System" Proc. 22nd DAC, 1985, pp 169-175. [8] M. Holley "Smart Tools Ease PLD Design" Digital Design, June 1986, pp 72-75. [9] S. Weil, D. C. Sui, D. B. Pellerin, "Gate-Array Compiler Cuts Big Designs Down to Size" Electronic Design, June 26, 1986, pp 101-108. [10] D. A. Pierce, C. E. Stroud "Impact of Behavioral Modeling and Automated Synthesis on the Design Process" Proc. National Communications Forum, Sept. 1986. [11] A. J. de Geus "Logic Synthesis and Optimization Benchmarks for the 1986 Design Automation Conference" Proc. 23rd DAC, 1986, p. 78. [12] E. J. Frey "ESIM: A Functional Level Simulation Tool" Proc. ICCAD-84, 1984, pp 48-50.

[13] C. T. Bye, M. R. Lightner, D. L. Ravenscroft "A Functional Modeling and Simulation Environment Based on ESIM and C" Proc. ICCAD-84, 1984, pp 51-53. [14] B. R. Chawla, H. K. Gummel, and P. Kozak "MOTIS - An MOS Timing Simulator" IEEE Trans. on Circuits and Systems, Vol. CAS-22, Dec. 1975, pp 901-910. [15] R. K. Brayton, G. D. Hactel, C. T. McMullen, A. L. Sangiovanni-Vincentelli "Logic Minimization Algorithms for VLSI Synthesis" Kluwer Academic Publishers, 1984. [16] J. Dussault, C-C. Liaw, M. M. Tong "A High LEvel Synthesis Tool for MOS Chip Design" Proc. 21st DAC, 1984, pp 308-314.


The NS32332 CAD System : A Highway to UNIXTM Nahum Sharfman

National Semiconductor (Israel), P.O. Box 3007, Hertzeliya B 46104, Israel

ABSTRACT This paper presents the CAD system used in the design of the NS32332 microprocessor at National Semiconductor. Architectural considerations in the design of the system are discussed and exemplified by specific tool implementations. The system is characterized by low area/performance penalty tolerance on one hand, and high reliability constraints on the other. It has been matched with a strict design methodology. The majority of tools have been developed in house and integrated with a few commercial products. REFERENCES [1] E. Gudes "A GENERAL COMMAND INTERFACE FOR VLSI/CAD PROGRAMS" Proc. ICCAD84, pp. 215-217, 1984 [2] Y. Hollander "USING AN RTL SIMULATOR TO SIMPLIFY VLSI DESIGN" VLSI DESIGN, September 1983, pp. 60-66. [3] D.D. Hill "LANGUAGE AND ENVIRONMENT FOR MULTI-LEVEL SIMULATION" Technical Report No. 80-185, Stanford University Computer Systems LAb, 1980. [4] S. Wimer, N. Sharfman "HOPLA-PLA OPTIMIZATION and SYNTHESIS" Proc. 20th Design Automation Conf., pp. 790-793, 1983. [5] R. Brayton, G.D. Hachtel, C. Mcmullen and A.L. sangiovanni-Vincentelli "ESPRESSO-II: A New Logic Minimizer For Programmable Logic Arrays" Proc. Cust. Integr. Circ. Conf., Rochester, NY, pp 370376, May 1984. [6] J.K. Ousterhout "SWITCH LEVEL DELAY MODELS FOR DIGITAL MOS VLSI" Proc. 21st Design Automation Conf., pp. 542-548, 1984.


AUTODRAFT: Automatic Synthesis of Circuit Schematics Mira A. Majewski, Fred N. Krull, Thomas E. Fuhrman, Paul J. Ainslie Computer Science and Electronics Departments, General Motors Research Laboratories, Warren, MI 48090-9055

Abstract Autodraft was developed for use with a prototype silicon compiler, called AutoCircuit, under development at General Motors Research Laboratories. In the AutoCircuit environment, a gate-level description of a high level building block or module is generated automatically based on the specifications selected by a designer via an interactive graphic block editor. AutoDraft uses the circuit description to automatically generate a schematic diagram of a compiled module. The objective in schematic generation is to create a readable schematic, not to find the most compact placement. Each module schematic is created on a single sheet by arranging circuit components in a column by row layout. The signal routing in AutoDraft is done using channel routing techniques. The schematic generated is written into the database of a target standard cell workstation for viewing or editing by the designer. References [1] Paul J. Ainslie, Thomas E. Fuhrman, Mira A. Majewski, Fred N. Krull "Circuit Synthesis for Signal Processing Incorporating Architectural Choices" IEEE Workshop on VLSI Signal Processing, November 1986. [2] Alfred Iwainsky, Michael May, and Peter Mennecke "Placement and Routing for Logic Schematics" Computer-Aided Design, vol.15, no.3, pp.115-122, May 1983. [3] P. Spencer and R.G. Bennets "Automatic Reconstruction of Logic Circuit Diagrams for Test-Generation Purposes" European Conference on Electronic Design Automation (September 1981). [4] Ivan Oscar Tou, Automatic Formatting of Logic Schematics, M. Sc. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, May 1984. [5] Ernest S. Kuh and Takeshi Yoshimura "Efficient Algorithms for Channel Routing" IEEE Transactions on Comuter-Aided Design of Integrated Circuits and Systems, vol. CAD-1, pp.25-35, January 1982.


BBC: A Module Generator for Back-to-Back Cells Thomas A. Hughes, Roberto Salama, Wentai Liu Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC. 276957911

Abstract BBC is an automated system to translate CMOS transistor netlist into mask layouts. The circuit is partitioned into rows of cells which are not necessarily identical. Adjacent cells have like type transistors facing each other, (i.e. N to N, P to P), so that power and ground busses alternate between cells. Within a cell, area savings in the horizontal dimension is accomplished by ordering transistors so that adjacent source and drains can abut as much as possible, thus resulting in one or more "lines" of connected transistors. Further improvement of transistor placement is achieved by moving transistors vertically between rows and generating alternate sequences of lines of transistors. Routing within the cells and between cells is done with poly, metal 1, and metal 2, and each is allowed to jog with a relatively high degree of freedom. Topological routing is used to accomplish the three layer intermodule routing. Results show that BBC can produce two to three times denser layouts as compared with standard cell and custom layouts. References [1] A. D. Lopez and H-F. S. Law "A Dense Gate Matrix Layout Style for MOS LSI" IEEE Journal of Solid-State Circuits, vol. SC-15, no. 4, pp. 736-740, 1980. [2] W. A. Van Noije and G. J. Declereck "Advanced CMOS Gate Array Architecture Combining Gate Isolation and Programmable Routing Channels" IEEE Journal of Solid-State Circuits, vol. SC-20, no. 2, pp. 469-480, 1985. [3] Dwight D. Hill "Sc2: A Hybrid Automatic Layout System" ICCAD, pp. 172-174, 1985. [4] Harry J. M. Veendrick "Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits" IEEE Journal of Solid-State Circuits, vol. SC-19, no. 4, pp. 468-473, 1984. [5] J. Fishburn and A. Dunlop "Tilos: A Posynomial Programming Approach to Transistor Sizing" ICCAD, pp. 326-328, 1985. [6] O. Wing, S. Huang, and R. Wang "Gate Matrix Layout" IEEE Transactions on Computer Aided Design, vol. CAD-4, no. 3, pp. 220-231, 1985. [7] Paul W. Kollaritsch and Neil H. E. Weste "Topologizer: An Expert System Translator of Transistor Connectivity to Symbollic Cell Layout" IEEE Journal of Solid-State Circuits, vol. SC-20, no. 3, pp. 799804, 1985. [8] Takao Uehara and William M. vanCleemput "Optimal Layout of CMOS Funtional Arrays" IEEE Transactions on Computers, vol. C-30, no. 5, pp. 305-312, 1981. [9] B. W. Kernighan and S. Lin "An Efficient Heuristic Procedure for Partitioning Graphs" The Bell System Technical Journal, vol. 49, no. 2, pp. 291-307, 1970.

[10] Melvin A. Breuer "Min-Cut Placement" Design Automation on Faoult Tolerant Computing, vol. 1, no. 4, pp. 343-362, 1979. [11] Christos H. Papadimitrious and Kenneth Steiglitz. Combinatorial Optimization: Algorithms and Complexity, Englewood Cliffs: Printice Hall, Inc., 1982. [12] M. Lorenzetti. Algorithms and Models for a Topologically Based Interconnection Routing System, PhD Dissertation, University of Texas at Austin, May, 1983. [13] R. Hitchcock "Cellular Wiring and the Cellular Modeling Technique" 6th Design Automation Workshop Proceedings, June, 1969. [14] A. Hashimoto and J. Stevens "Wire Routing by Optimizing Channel Assignment Within Large Apertures" Design Automation Workshop, pp. 155-168, 1971. [15] D. A. Henlin, et al "A 16 Bit X 16 Bit Pipelined Multiplier Macrocell" IEEE Journal of Solid-State Circuits, vol. SC-20, no. 2, pp. 542-547, 1985. 16] L. A. Glasser and D. W. Dobberpuhl. Design and Analysis of VLSI Circuits, Addisson-Wesley Publishing Co., 1985.


A Methodology for Automated Layout of Switched-Capacitor Filters Hormoz Yaghutiel, Alberto Sangiovanni-Vincentelli, Paul R. Gray Department of Electrical Engineering and Computer Sciences, Electronics Research Laboratory, University of California, Berkeley, California 94720

Abstract A system for automatic generation of Switched-Capacitor (SC) filters is presented. The novel features of this system are its floor-planning strategy, its ability to generate compact array of capacitors with fixed area/perimeter ratio, and its router specifically developed for analog circuits. References [1] Robert W. Brodersen, Paul R. Gray, and David A. Hodges "MOS Switched-Capacitor Filters" Proceedings of IEEE, January, 1979, pp.61-75. [2] P. E. Allen "A Design Methodology For CMOS Analog Integrated Circuits" IEEE International Conference on Computer-aided Design, Santa Clara, CA, September 12-15 1983, pp. 217-219. [3] G. Kelson "Design Automation Techniques for Analog VLSI" VLSI Design, January, 1983, pp.78-82. [4] A. E. Dunlop et al "Features in LTX2 For Analog Layout" International Symposium On Circuits And Systems, Kyoto, Japan, June, 1985. [5] M. G. DeGrauwe, and W. M. C. Sansen "A Synthesis Program for Operational Amplifiers" IEEE International Solid-State Circuits Conference, February, 1984, pp. 18-19. [6] Hyunchul Shin and Alberto Sangiovanni-Vincentelli "MIGHTY: A 'Rip-Up and Reroute' Detailed Router" IEEE International Conference on Computer-aided Design, Santa Clara, CA, November 10-13 1986. [7] P. P. Moore "OCT Database Programmer's Manual" Internal Memorandum, University of California, Berkeley, January 1986.


Gate Array Macro Layout Automation Jim Rowson, Steve Trimberger, Kerry Pierce, Dam Vo VLSI Technology, Inc., San Jose, California.

ABSTRACT A new technique for automatically generating gate array macrocell layout from a transistor netlist has been developed. The technique uses place and route automation to build a symbolic macrocell route file together with a procedural design language to translate the macrocell route file to physical layout. The target gate array base was developed in conjunction with the layout automation. The automation has been used to convert netlists of a 254 cell standard cell library into gate array form. Approximately half of the cells were converted cleanly, the other half had only one or two unroutes which were fixed interactively. Comparison with hand layout shows a 10% loss in both area and routing resource use. Four different sets of cost function coefficients were used to convert the library. Experimentation shows that cost function coefficients can be found that give smaller than hand layout placements. However, these size-only coefficients gave placements that were difficult to route. REFERENCES [1] K. Sakashita et al. "A 10-K gate CMOS gate array with gate isolaton configuration" in Proc. CICC 83. (Rochester, NY), May 1983, pp. 14-18. [2] J. Nogatch and T. Hedges "Automated Design of CMOS Leaf Cells" VLSI Systems Design. November 1985, pp. 66-78.


Hierarchical Floor Planning for Building Block Layout Wei-Ming Dai, Ernest S. Kuh Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA 94720

ABSTRACT We present a new methodology for hierarchical floor planning of rectangular-shaped and arbitrary-sized building blocks. Unlike the traditional approach, which separates floor planning (or placement if the dimensions of all block are fixed) and global routing into two consecutive stages, our approach provides a simultaneous solution of floor planning and global routing in a hierarchical fashion. The floor planner with a maximum of five rooms per level has been implemented in the C language, running on a VAX 8650 under 4.3 BSD UNIX. The experimental results on examples with a large number of irregular blocks showed that our approach out-performed other well-known deterministic algorithms, and gave results comparable to the random-based algorithms but with computing time an order of magnitude less. Due to the unique goal-oriented and patterndirected features of our floor planner, it accepts specifications for overall aspect ratio and I/O pad positions, thus making our approach suitable for hierarchical design. References [1] M. Burstein "A Non 'Placement/Routing' Approach to Automation of VLSI Layout Design" in Proc. of 1982 IEEE International Symposium on Circuits and Systems, pp. 756-759, 1982. [2] M. Burstein and R. Pelavin "Hierarchical wire routing" IEEE Trans. on CAD, vol. CAD-2, no.4, pp.223-234, 1983 [3] N. P. Chen, C. P. Hsu and E. S. Kuh "The Berkeley building-block (BBL) layout system for VLSI design" in Dig. Tech. Papers, IEEE Int. Conf. on Computer-Aided Design, pp. 40-41, 1983. [4] B. W. Colbry and J. Soukup "Layout aspects of the VLSI microprocessor design" in Proc. of 1982 IEEE International Symposium on Circuits and Systems, pp. 1214-1228, 1982. [5] W. M. Dai, T. Asano, E. S. Kuh "Routing region definition and ordering scheme for building-block layout" IEEE Trans. on CAD, vol. CAD-4, no.3, pp. 189-197, 1985. [6] W. M. Dai "Steiner minimal tree problem in proper plane triangulated graph is NP-complete" unpublished manuscript, 1986. [7] W. M. Dai and E. S. Kuh "A linear-time algorithm for finding minimum steiner tree in partial 3-Tree" manuscript in preparation, 1986. [8] W. M. Dai, M. Sato and E. S. Kuh "A characterization theorem on partial 3-trees" unpublished manuscript, 1986. [9] W. R. Heller, G. Sorkin, and K. Maling "The planar package planner for system designers" in Proc. of the 19th Design Automation Conf., pp. 253-260, 1982.

[10] K. Kozminski and E. Kinnen "An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits" in Proc. of the 21th Design Automation Conf., pp. 655-656, 1984. [11] U. P. Lauther Private communication, 1986. [12] W. K. Luk, D. T. Tang, C. K. Wong "Hierarchical global wiring for custom chip design" in Proc. of the 23th Design Automation Conf., pp. 481-489, 1986. [13] Sany M. Leinwand and Yen-Tai Lai "An algorithm for building rectangular floor-plans" in Proc. of the 21th Design Automation Conf., pp.663-664, 1984. [14] R. H. J. M. Otten "Automatic floorplan design" in Proc. of the 19th Design Automation Conf., pp. 261-267, 1982. [15] B. T. Preas "Placement and routing algorithms for hierarchical integrated circuit layout" Ph.D. Dissertation, Dept. of Electrical Eng., Stanford Univ., Stanford, CA, 1979. [16] S. Tsukiyama, K. Koike, and I. Shirakawa "An algorithm to eliminate all complex triangles in a maximal planar graph for use in VLSI floor-plan" in Proc. of 1986 IEEE International Symposium on Circuits and Systems, pp. 321-324, 1986. [17] J. A. Wald and C. J. Colbourn "Steiner trees, partial 2-trees, and minimum IFI networks" Networks, vol. 13, pp.159-167, 1983.


Constructive Placement of General Blocks In VLSI Under Uncertainties in the Position of Ports Shmuel Wimer Dept. of Electrical Engineering Technion - Israel Institute of Technology, Haifa 32000, Israel and IBM Israel Scientific Center Technion City, Haifa 32000, Israel

Israel Koren Dept. of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000, Israel

ABSTRACT Placement problems are in many cases solved at a very early stage of the design cycle when only a rough estimate of the blocks' geometry is available. Hence, the placement can be viewed as a problem of optimization under uncertainties. One type of uncertainties that may arise in the physical design process is in the position of ports. We first present a mathematical framework to model these uncertainties, and then solve the associated stochastic optimization problem. The solution is obtained by proving that the stochastic optimization problem can be reduced to an equivalent deterministic one. Then a normal law of distribution of the placement cost is proved. Finally, a post optimization phase that resolves the uncertainties is suggested. Index Terms - IC layout, Constructive placement, Physical design, Stochastic programming. REFERENCES [1] Avriel M. Nonlinear Programming: Analysis and Methods, Prentice-Hall, 1976. [2] Fisz M. Probability Theory and Mathematical Statistics, John Wiley, 1963. [3] Vajda S. Probabilistic Programming, Academic Press, 1972. [4] Wimer S. and Koren I. Analysis of Algorithms for Constructive General Block Placement in VLSI, Technical Report No. 553, Dept. of Electrical Engineering, Technion, Haifa, 1985. [5] Aoki M. Optimization of Stochastic Systems, Academic Press, 1967.


A Placement and Routing System for Wafer Scale Capt. B. J. Donlan Air Force Institute of Technology, Wright-Patterson AFB, OH 45433

J. F. McDonald Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180

ABSTRACT Wafer Scale Integration (WSI) and the related technology of Wafer Scale Hybrid Packaging (WSHP) are techniques for developing large digital systems on a single wafer. This paper describes a system of design automation tools developed to aid in the implementation of wafer scale digital systems. A placement system which maps the system architecture onto the wafer die sites is presented along with a very fast wafer line router. Placement and routing results are also shown for three wafer architectures. REFERENCES [1] B. Donlan, J. McDonald, G. Taylor, R. Steinvorth, and A. Bergendahl "Computer-Aided Design and Fabrication for Wafer Scale Integration" VLSI Design, April 1985. [2] G. Taylor, B. Donlan, J. McDonald, A. Bergendahl, and R. Steinvorth "The Wafer Transmission Module - Wafer Scale Integration Packaging" Proceedings Custom Integrated Circuits Conference, May 1985. [3] B. Donlan "Design Automation for Wafer Scale Integration" PhD Thesis, Rensselaer Polytechnic Institute, June 1986. [4] N. Quinn and M. Breuer "A Force Directed Component Placement Procedure for Printed Circuit Boards" IEEE Transactions on Circuits and Systems, June 1979, pp 377-388. [5] F. Bourgesois and J.C. Lasalle "An Extension of the Munkres Algorithm for the Assignment Problem to Rectangular Matrices" Communications of the ACM, ACM, Dec 1971, pp 802-806 [6] A. Bergendahl, B. Donlan, J. McDonald, R. Steinvorth, and G. Taylor "A Thick Film Lift-off Technique for High Frequency Interconnections in Wafer Scale Integration" IEEE VLSI Multilevel Interconnection Conference, June 1985, pp 154-162. [7] D. Hightower "A Solution to Line-Routing Problems on the Continuous Plane" Proceedings 1969 Design Automation Workshop, pp 1-24. [8] G. Taylor, R. Steinvorth and J. McDonald "An Architecture for a Wafer Scale Integrated Video Rate Two Dimensional Fast Fourier Transform Processor" Proceedings of the International Conference on Computer Design, IEEE, 1984, pp 623-628.


Rigorous Three - Dimensional Process Simulator on A Super - Computer: SMART - P S. Odanaka, H. Umimoto, M. Wakabayashi, H. Esaki Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., Moriguchi Osaka 570, Japan

Abstract This paper describes a new three-dimensional process simulator based on the finite difference approach to a super-computer. To simulate the impurity redistribution and nonplanar structure in Si / SiO2 system, this simulator contains generalized threedimensional oxidation model, interaction model of impurities, numerical model of interstitial-assisted OED (oxidation-enhanced diffusion), and other process models. The adoption of efficient numerical algorithms based on coordinate transformation method has realized these numerical process modeling on actual process CAD. The excellent capabilities of this simulator are actually proved in the three-dimensional structure of LOCOS isolated 0.5 µm MOSFET with a 1.6 µm gate width on mask. References [1] B.R. Penumalli "A comprehensive two-dimensional VLSI process simulator program, BICEPS" IEEE Trans. Electron Devices, vol.ED-30, no.9, Sept., pp.986-992, Sept., 1983. [2] L. Borucki, H.H. Hansen, and K. Varahramyan "FEDSS A 2-D semiconductor fabrication process simulator" IBM J. Res. and Develop. vol.29, no.3, May, pp.263-276, May, 1985. [3] D. Chin, M. Kump, and R.W. Dutton "SUPRA-Stanford University process analysis program" Stanford Electronics Lab., July 1981. [4] S. Onga and K. Taniguchi "A three-dimensional process simulator and its application to submicron VLSI's" Dig. Tech. papers, 1985 Sympo. VLSI Tech., pp.68-69, May, 1985. [5] D. Chin, Soo-Young Oh, and R.W. Dutton "A general solution method for two-dimensional nonplanar oxidation" IEEE Trans. Electron Devices, vol.ED-30, pp.993-998, Sept., 1983. [6] H.Y. Yeager and R.W. Dutton "An approach to solving multiparticle diffusion exhibiting nonlinear stiff coupling" IEEE Trans. Electron Devices, vol.ED-32, no.10, pp.1964-1976, Oct., 1985. [7] C.P. Ho, J D. Plummer, S.E. Hansen, and R.W. Dutton "VLSI process modeling - SUPREM III" IEEE Trans. Electron Devices, vol. ED-30, no.11, pp.1438-1453, Nov., 1983. [8] D.A. Antoniadis "Oxidation-induced point defects in silicon" IEEE J. Electrchem, Soc., vol. 129, pp. 1093-1097, May 1982. [9] A. Wambecq "Rational Runge-Kutta methods for solving systems of ordinary differential equations" Computing, vol. 20, pp.333-342, 1978.


Fast Two-Dimensional Numerical Analyses of Gaas Mesfets Using Two-Particles Simulation and Regional Simulation Y. Yamada, Y. Kaida Department of Electrical Engineering and Computer Science, Kumamoto University, Kumamoto 860, Japan

ABSTRACT A two-particles simulation (TPS) and a regional simulation (RES) have been developed in order to reduce CPU time and CPU memory in a particle simulation of self-aligned GaAs MESFETs with submicrometer gate-length. The TPS uses two different types of particles. The charge per particle in the highly doped n+-regions is larger than that in the lightly doped n-region. An algorithm for current continuity at the boundaries between the n+- and n-regions are considered. In RES the n+- regions are simply replaced by effective series resistances and a particle simulation is applied to the n-region only. The number of the particles employed in TPS is reduced to about 1/(2N+D/ND+1) of that in a conventional full simulation and it in RES is about one third of that in TPS. Reduction of CPU time is about 1/7 and 1/11 in TPS and RES, respectively. REFERENCES [1] Y. Awano, K. Tomizawa, and N. Hashizume "Principles of Operation of Short-Channel Gallium Arsenidas Field-Effect Transistor Determined by Monte Carlo Method" IEEE Trans. Electron Devices, Vol. ED-31, pp. 448-452, 1984. [2] Y.-J. Park, D. H. Navon, and T.-W. Tang "Monte Carlo Simulation of Bipolar Transistors" IEEE Trans. Electron Devices, Vol. ED-31, pp. 1724-1730, 1984. [3] P. T. Nguyen, D. H. Navon, and T.-W. Tang "Boundary conditions in Regional Monte Carlo Device Analysis" IEEE Electron Devices, Vol. ED-32, pp. 783-787, 1985. [4] B. Carnez, A. Cappy, A. Kaszynski, E. Constant, and G. Salmer "Modeling of a Submicrometer gatefield effect transistor including effects of nonstationary electron dynamics" J. Appl. Phys., Vol. 51, No. 1, pp.784-790, Jan. 1980.


Submicron 2D MOS Modeling Vered Marash, Robert W. Dutton Integrated Circuit Laboratory, Stanford University, Stanford, California 94305

ABSTRACT The development of accurate analytical models for circuit design is critical for submicron device technology, yet to assess real device performance, 2D technology cross sections and device simulation provide essential data. In fact, we are reaching the point where this 2D simulated data provides the only viable technology level diagnostic. In this paper 2D device analysis is coupled into a new model development environment. An improved set of 2D analytical boundary conditions for submicron MOS technology is developed through use of "exact" information from numerical simulations. In addition to the accurate modeling of 2D potential boundary conditions, the new model provides a framework for further enhancements in the context of technology evolution. Specifically, the methodology is general and can be extended to a variety of technologically complex submicron structures, for example, source/drain tip implants (LDD type devices), or a variety of other blanket and locally implanted structures. REFERENCES [1] J. R. Pfiester, J. D. Shott, and J. D. Meindl "Performance Limits off CMOS ULSI" IEEE Transactions on Electron Devices, vol. ED-32, no. 2, February 1985 [2] T. N. Nguyen "Small-Geometry MOS Transistors: Physics and Modelling of Surface- and Buried Channel MOSFETS" Technical Report No. G545-2, Stanford Electronics Lab, Stanford University, Aug. 1984 [3] K. N. Ratnakumar and J. D. Meindl "Short-channel MOST threshold voltage model" IEEE J. SolidState Circuits, vol. SC-17, pp 937-947, Oct. 1982 [4] D. R. Poole and D. L. Kwong "Two-dimensional analytical modeling of threshold voltages of shortchannel MOSFETs" IEEE Electorn Device Letters, vol. EDL-5, pp 443-446, Nov. 1984 [5] M. R. Pinto, C. R. Rafferty, and R. W. Dutton "PISCES II: Poisson and Continuity Equation Solver" Stanford Electronics Lab, Stanford University, Sept. 1984


An Improved Cell Model for Hierarchical Constraint-Graph Compaction Mark Reichelt MIT/AT&T Bell Laboratories

Wayne Wolf AT&T Bell Laboratories

Abstract This paper describes a new cell model, the DONUT abstraction, that enables a pitchmatching hierarchical compactor to determine cell-to-cell spacing constraints. The DONUT model extends the existing port abstraction model to contain information about the components and wires near a cell's boundary that affect cell-to-cell spacing. The designer specifies the minimum spacing (or maximum overlap) between cells, and this distance determines how much of a cell's interior must be represented in each DONUT abstraction. This ability to control the minimum cell spacing gives the designer control over the tradeoff between improved compaction quality and increased computational cost. Experiments for CMOS and nMOS examples show that DONUTs allowing minimal cell spacing (with no overlap) cost about 9 times more in memory and CPU-time than port abstractions. REFERENCES [1] Chris Kingsley, Earl An Integrated Circuit Design Language, MS Thesis, California Institute of Technology (June, 1982). [2] Peter Eichenberger, Fast Symbolic Layout Translation for Custom VLSI Integrated Circuits, PhD thesis, Stanford University (March, 1986). [3] Robert Mathews, John Newkirk, and Peter Eichenberger "A Target Language for Silicon Compilers" Compcon Proceedings, pp. 349-353 (Spring 1982). [4] Chris Kingsley "A Hierarchical, Error-Tolerant Compactor" Proceedings, 21st Design Automation Conference, pp. 293-297 ACM/IEEE, (June, 1984).


An Interactive Symbolic Cell Layout System with High Speed Relational Data Base Yoshio Okamura, Shinji Kato, Takashi Sato Device Development Center, Hitachi Ltd., 2326 Imai Oume-Shi Tokyo, Japan

Abstract An interactive symbolic cell layout system named JUPITER is described. Designers on JUPITER can perform the cell layout designs without considering complex design rules by using parametric symbols, which generate plural complicated real mask patterns automatically. JUPITER constructs a special high speed relational data base in the main memory when the cell layout data are loaded from the disk file. These high speed data base accesses are realized by the optimized use of the extended B-tree indexes and network pointers in the relational data base. References [1] N.Weste "Virtual Grid Symbolic Layout" Proc., 18th Design Automation Conf. pp.225-233,1981. [2] M.Ozaki "MGX: AN INTEGRATED SYMBOLIC LAYOUT SYSTEM FOR VLSI" Proc., 21st Design Automation Conf. pp.572-579,1984. [3] A. Kurosawa "A STRATEGY FOR INTRODUCING CAD INTO MICROCOMPUTER DESIGN" Proc., ICCAD-85, pp. 229-231, 1985. [4] E.F.Codd "Relational Database: A Practical Foundation for Productivity" Comm. ACM 25-2, pp.109117, 1982. [5] R.H.Katz "A Database Approach for Managing VLSI Design Data" Proc., 19th Design Automation Conf. pp.274-282, 1982 [6] M.Hardwick "EXTENDING THE RELATIONAL DATABASE DATAMODEL FOR DESIGN APPLICATIONS" Proc., 21st Design Automation Conf. pp.110-116, 1984.


Generation of VLSI Cells from a Behavioural Description D J Allerton, C I P S Padua Department of Electronics and Computer Science, University of Southampton, England

Abstract An essential part of VLSI design is the provision of a library of proven cells which can be extracted and organised to perform the desired functions of a specification. Most cell design languages require the specification of both the function and layout of individual cells. However, the work described in this paper allows the cell designer to specify the behaviour of the cell. The extraction of function and the synthesis to determine the layout is performed by a silicon compiler. The cell specification is parsed to produce an intermediate functional form which defines the operations, storage and sequencing information. Subsequently, by the application of an automated logic synthesis tool, the intermediate code is translated to a finite-state machine in the form of a set of state tables. The Boolean equations derived from the state tables provide the input to a layout generator program, for example a PLA generator. A simple design example is included to illustrate these phases of silicon compilation and comparative assessment of three NMOS cells is presented. References [1] Johannsen, D.L. Bristle Blocks: A Silicon Compiler, Proc. 16th Design Automation Conf., 1979. [2] Bergmann, N. A Case Study of the F.I.R.S.T. Silicon Compiler, University of Edinburgh, Dept. of Computer Science, Internal Report CSR 159-84, 1984. [3] Siskind, J.M., Southard, J.R. and Crouch, K.W. Generating Custom High Performance VLSI Designs from Succinct Algorithmic Descriptions, Proc. of M.I.T. Conf. on Advanced Research in VLSI, 1982. [4] Feldman, S.I. The Circuit Design Language Xi( ), IEEE International Conf. on Computer Design, 1983. [5] Allerton, D.J. and Currie, A.J. SCHOLAR: Another Approach to Silicon Compilation, IEEE Int. Conf. on Computer-Aided Design, 1984. [6] Allerton, D.J., Batt, D.A., Currie, A.J. and Nichols, K.G. Functional Simulation as an Adjunct to Silicon Compilation, IEE Int. Conf. on Computer Aided Engineering, 1984. [7] Allerton, D.J., Batt, D.A. and Currie, A.J. A VLSI Design Language Incorporating Self-timed Concurrent Processes, Proc. IEE Electronic Design Automation Conf, 1984. [8] Kohavi, Z. Switching and Finite Automata Theory, McGraw-Hill, 1970. [9] Roth, J.P. Algebraic Topological Methods for the Synthesis of Switching Systems: I, Trans. Am. Math. Soc., Vol. 88, pp 301-326, 1958. [10] Newkirk, J. and Mathews, R. The VLSI Designer's Library, Addison-Wesley, 1983. [11] Guimaraes, J.M. and Videira, I.M. Celulas Basicas para Microprocessadores, 2nd Workshop Nacional sobre Tecnologia das Telecomunicacoes, 1985.


Functional Verification of Digital MOS Circuits Douglas S. Reeves, Mary Jane Irwin Department of Computer Science, Pennsylvania State University, University Park, PA 16802

Abstract A major goal of the SNAP CAD system for automatically generating signal-processing circuits is to prove that the designs are functionally correct. The function of a MOS circuit is extracted using techniques due to Bryant. This functional characterization is compared to the high-level description of the circuit to determine correctness. Important aspects of the verifier are i) paths in the switch graph are compiled statically, ii) cells in a hierarchical design are functionally meaningful and may be abstracted for use in verifying the entire design, and iii) optimized algorithms make interactive verification feasible. Experimental results are presented. References [Bar84] Barrow, H. G. Proving the Correctness of Digital Hardware Designs, In VLSI Design (July 1984), 64-77. [Bry84] Bryant, R. A Switch-Level Model and Simulator for MOS Digital Systems. In IEEE Transactions on Computers C-33, 2 (Feb. 1984), 160-177. [Bry85] Bryant, R. Symbolic Verification of MOS Circuits. In Proceedings of the 1985 Chapel Hill Conference on VLSI. H. Fuchs, ed. Computer Science Press, 1985, 419-438. [Bry86] Bryant, R. Papers on a Symbolic Analyzer for MOS Circuits. Rept. No. CMU-CS-86-114, Department of Computer Science, Carnegie-Mellon University, March 1986. [DDR83] Ditlow, G., Donath, W., and Ruehli, A. Logic Equations for MOSFET Circuits. In Proc. of the Int'l Symposium on Circuits and Systems, IEEE, 1983, 752-754. [HS83] Hajj, I. N., and Saab, D. Symbolic Logic Simulation of MOS Circuits. In Proceedings of the International Symposium on Circuits and Systems. IEEE, 1983, 246-249. [Haj85] Hajj, I. N. A Path Algebra for Switch-Level Simulation. In Proceedings of ICCAD-85. IEEE, 1985, 153-155. [Kar86] Karplus, K. Exclusion Constraints: a New Application of Graph Algorithms to VLSI Design. In Proc. of the 4th MIT Conf. on Advanced Research in VLSI. C. Leiserson, ed. MIT Press, 1986, 123-139. [LH82] Lightner, M. and Hachtel, G. Implication Algorithms for MOS Switch Level Functional Macromodeling, Implication, and Testing. In Proceedings of the 19th Design Automation Conference. IEEE, 1982, 691-698. [OI86] Owens, R. and Irwin, M. J. A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. IEEE Transactions on CAD, June 1986. [RI86] Reeves, D. S. and Irwin, M. J. Verification of VLSI Circuits for Signal Processing Applications. in preparation.

[Sho83] Shostak, R. Verification of VLSI Designs. In Proc. of the 3rd Caltech Conf. on VLSI. R. Bryant, ed., Computer Science Press, 1983, 185-206. [Ter83] Terman, C. J. Simulation Tools for Digital LSI Design. Ph.D. thesis, M.I.T. Lab. for Comp. Sci., Sept. 1983. [Wag77] Wagner, T. J. Hardware Verification. Rept. No. STAN-CS-77-632, Stanford U. Computer Science Dept., 1977.


SPIL: A Silicon Compiler with Performance Evaluation B.R. Petersen, B.A. White, D.J. Salomon, M.I. Elmasry VLSI Group, Dept. of Electrical Engineering, University of Waterloo, Waterloo, Ontario, Canada

ABSTRACT A silicon compiler is a computer program that generates IC layouts from a high-level specification. The SPIL silicon compiler is a prototype numerical processor designautomation tool developed at the University of Waterloo. A digital signal processing algorithm is specified in a language similar to Pascal, and IC layouts are generated using a simple register-transfer architecture with a data path controlled by a finite-state machine. For a silicon compiler to be an effective design automation tool it is essential to include some type of performance evaluation to estimate area, speed and power dissipation of the generated chip layout. A design aid called EPAD was developed for performance estimation of propagation delays, power dissipation and silicon area of CMOS VLSI circuits. The objective is to provide the user with an analysis of the IC layout and to provide SPIL with feedback analysis to be used in performing higher levels of compilation. To improve and evaluate the effectiveness of the compiler and the performance evaluation feature, two design examples were used. The first example was the design of a chip which controls timing and exponent calculation for floating-point addition and subtraction. The second was for a chip which performs a conversion from adaptive delta modulation to pulse code modulation. REFERENCES [1] D.J. Salomon, S. Sadler and M.I. Elmasry. A VLSI Architecture and a Silicon Compiler for Designing Numerical Processors, VLSI DESIGN, pp. 62-70, Feb. 1985. [2] C. Mead and L. Conway. Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980. [3] J.R. Burns "Switching Response of Complementary-Symmetry MOS Transistor Logic Circuits“ RCA Review, pp. 627-661, Dec. 1964. [4] Canadian Microelectronics Corporation Guide to the Integrated Circuit Implementation Services of the Canadian Microelectronics Corporation, Queen's University, Mar. 1985. [5] Canadian Microelectronics Corporation CMC Guide for Designers Using the Northern Telecom CMOS3 Process, Queen's University, Jun. 1985. [6] J.L. LoCicero and D.L. Schilling. An All-Digital Technique for ADM to PCM Conversion, 1976 National Telecommunications Conference, Pt.II, Dallas, Texas, U.S.A, pp. 29.2/1-5, Nov. 29 - Dec. 1, 1976. [7] A. Vladimirescu, A.R. Newton and D.O. Pederson. SPICE Version 2G6 User's Guide, University of California, Berkeley, Calif., U.S.A., Oct. 1980.


EASE-An Applications-Oriented CAD System for Process Design J. Mar, K. Bhargavan, S. Duvall, R. Firestone, D. Lucey, S. N. Nandgaonkar, S. Wu, K.S. Yu, F. Zarbakhsh Intel Corporation, Santa Clara, CA 95051

Abstract A new approach for making process/device simulation tools easier to use is presented. Described, is an integrated process CAD system in which users select applications rather than tools. Simulation methodologies for each of the applications are built into the system and supported by automatic execution modules. The addition of "seed" databases and command interfaces tailored to the application provide for a simple user interface, one that greatly reduces user learning requirements for applying such tools. References [1] C. P. Ho and S. E. Hansen "SUPREM III A Program for Integrated Process Modeling and Simulation" Stanford Electronics Laboratories, Technical Report 83-001, July 1983. [2] D. C. D'Avanzo M. Vanzi, and R. W. Dutton "One-Dimensional Semiconductor Device Analysis (SEDAN)" Stanford Electronics Laboratories, Technical Report G-201-5, October 1979. [3] W. G. Oldham, S. N. Nandgaonkar, A. R. Neureuther, and M. M. O'Toole "A General Simulator for VLSI Lithography and Etching Process: Part I Application to Projection Lithography" IEEE Trans. Electron. Devices, Vol. ED-26, No. 4, April 1979. [4] M. R. Pinto, C. S. Rafferty, and R. W. Dutton "PISCES II: Poisson and Continuity Equation Solver" Stanford Electronics Laboratories Technical Report, September 1984. [5] W. D. Murphy, W. F. Hall, and C. D. Maldonado "Efficient Numerical Solution of Two-Dimensional Nonlinear Diffusion Equations with Nonuniformly Moving Boundaries: A Versatile Tool for VLSI Process Modeling" Numerical Analysis of Semiconductor Devices and Integrated Circuits, Proceedings of the NASECODE II Conference, Trinity College, Dublin, June 17-19, 1981, Boole Press, Dublin (1981). [6] D. S. Boning and D. A. Antoniadis "MASTIF - A Workstation Approach to Fabrication Process Design" ICCAD-85 Digest of Technical Papers, pp. 280-282. R. Amantea and C. Davis "MDLGRF, A System of Programs for Computer-Aided Modeling of Semiconductor Devices" ICCAD-83 Digest of Technical Papers, pp. 204-206. [7] S. G. Duvall and D. J. Lucey "An Interchange Format for Process and Device Simulation" to be published.


A Modular Framework for an Interactive Design Synthesis System Michael F. Klein Sun Microsystems, Inc., 2550 Garcia Dr. Mountain View, CA 94043 David A. Hodges Electronics Research Laboratory, University of California, Berkeley

ABSTRACT A new, highly modular framework for supporting the different types of decisions inherent in design synthesis has been implemented in Cameo, an expert integrated circuit process synthesis system for photolithography. The framework is based on a combination of object-oriented programming and a frame-based expert system shell from HewlettPackard Company, HPRL I. A user can rapidly choose and evaluate several alternative methods of depositing, exposing, and developing photoresist using Cameo's built-in knowledge about these fabrication steps. Heuristic, analytic, or empirical solution methods for synthesis decisions are used as appropriate to help guide the user near a "good" solution. Libraries of IC process steps using can be spliced into a process design and reused or customized according to the user's own requirements. Cameo's rough estimates of linewidth variation have been within 0.1 µm of SAMPLE's simulated values under the difficult condition of photoresist deposition on a polysilicon layer with typical vertical features and other nonidealities. These rough estimates are obtained in about five minutes of Cameo's use. Coding time for an application is relatively small and debugging is simplified. REFERENCES [1] Oldham, W.G., et. al. "A General Simulator for VLSI Lithography and Etching Processes: Part 1Application to Projection Lithography" IEEE Transactions on Electron Devices, vol. ED-26, no.4, April 1979, pp. 717-722. [2] Oldham, W.G., et. al. "A General Simulator for VLSI Lithography and Etching Processes: Part 1Application to Deposition and Etching" IEEE Transactions on Electron Devices, vol. ED-27, no.8, August 1980, pp. 1455-1459. [3] Ho, C.P., Hansen, S.E. "SUPREM III-A Program for Integrated Circuit Process Modeling and Simulation" Stanford University Technical Report SEL 83-001, July 1983. [4] Hayes-Roth, F., Waterman, D.A., Lenat, D.B., eds. Building Expert Systems, Addison-Wesley, Reading, Massachusetts, 1983, pp. 264-265. [5] Klein, M.F. "Specifying Integrated Circuit Photolithograpy Processes Using Heuristic and Algorithmic Techniques" ERL Memo no. UCB/ERL M85/73, Electronics Research Laboratory, University of California, Berkeley, Sept. 1985.

[6] Gajski, D.D., Bozek, J.J. "ARSENIC: Methodology and Implementation" Digest of Technical Papers, IEEE International Conference on CAD, November 1984, pp. 116-118. [7] Kramer, G.A. "Helios Design Consultant System," SIGART Newsletter, ACM Special Interest Group on AI, no. 92, pp. 76-78, April 1985. [8] de Kleer, J., Sussman, G.J. "Propagation of Constraints Applied to Circuit Synthesis" Circuit Theory and Applications, volume 8, John Wiley and Sons, 1980, pp. 127-144. [9] Brown, A.L. "Qualitative Knowledge, Causal Reasoning and the Localization of Failures" Ph.D. dissertation, MIT AI Labs Technical Report No. 362, 1977. [10] Pan, Y-C. "Qualitative Reasonings with Deep-Level Mechanism Models for Diagnosis of Dependent Failures" Ph.D. dissertation, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Report no. T-132, Dec. 1983. [11] Nye, W.T. "DELIGHT: An Interactive System for Optimization-Based Engineering Design" ERL Memo no. M83/33, Electronics Research Laboratory, University of California, Berkeley, 1983.


HIPPOCRATES: A Methodology for IC Process Diagnosis Costas J. Spanos SEG/CAD Simulation, Digital Equipment Corporation, 77 Reed Road (HL02-2/H13) Hudson, Massachusetts 01749-2895

Abstract This paper describes a methodology for the statistical diagnosis of non catastrophic process faults. Diagnosis is based on the automatic selection of the minimum required set of measurements and the subsequent solution of a sequence of non-linear minimization problems that yields information about the fault. If one chooses to use electrical measurements, this method is suitable for accurate characterization of a fault, even after processing is complete. A software package called HIPPOCRATES has been written in C and it is used here in conjunction with actual measurements to demonstrate the effectiveness of the method. References [1] O. Melstrand, E. O'Neill, G. Sobelman and D. Dokos "A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and Modeling" IEEE Trans. on Computer-Aided Design, Vol. CAD-3, No. 1, pp. 47-52, January, 1984. [2] D. E. Ward and K. Doganis "Optimized Extraction of MOS Model Parameters" IEEE Trans. on Computer-Aided Design, Vol. CAD-1, No. 4, pp. 163-169, October, 1982. [3] P. Yang and P. Chatterjee "An Optimal Parameter Extraction Program for MOSFET Models" Technical Report, Texas Instruments, 1980 [4] W. Maly and T. Gutt "Base and Emitter Diffusion Simulation Model" Proc. of International Conference on Computer-Aided Design and Manufacturing of Electronics Components, Circuits and Systems, pp. 3842, 1979 [5] W. Maly, A. Strojwas and S.W. Director "Fabrication Based Statistical design of Monolithic IC's" Proc. of International Conference on Circuits and Systems, Chicago, 1980 [6] W. Maly and S.W. Director "Characterization of Random Behaviour of the IC Manufacturing Process" IEEE Proceedings, 1981 [7] W. Maly and A. Strojwas "Statistical Simulation of the IC Manufacturing Process" IEEE Trans. on Computer-Aided Design, Vol. CAD-1 No 3, pp. 120-131, July, 1982 [8] C.J. Spanos and S.W. Director "Parameter Extraction for Statistical IC Process Characterization" IEEE Trans. on Computer-Aided Design Vol. CAD-5 No 1, pp. 66-79, January, 1986 [9] S.R. Nassif, A.J. Strojwas and S.W. Director "Fabrics II: A Statistical Simulator of the IC fabrication Process" IEEE Trans. on Computer-Aided Design Vol. CAD-3 No 1, pp. 40-47, January, 1984 [10] A.J. Strojwas "Pattern Recognition Based Methods for IC Failure Analysis" Research Report No. CMUCAD-82-1, Phd thesis, Carnegie-Mellon University, October, 1982

[11] P. Odryna "A VLSI Fault Diagnosis System" Research Report No. CMUCAD-85-49, Master thesis, Carnegie-Mellon University, May, 1985 [12] M.J.D. Powell "A Fast Algorithm for Nonlinearly Constrained Optimization Calculation" Proceedings of the Dundee Conference on Numerical Analysis, June, 1977


RELIC: A Reliability Simulator for Integrated Circuits Teresa S. Hohol, Lance A. Glasser Department of Electrical Engineering and Computer Science, Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA. 02139

Many of the failure mechanisms which cause reliability problems in VLSI chips can be influenced or avoided in the circuit design phase. RELIC is a reliability simulator developed to analyze and predict the stress and wear on MOS VLSI chips due to such mechanisms. RELIC uses a simple methodology for abstracting the idea of the stress from any particular failure mechanism, thus allowing analyses of many different failure mechanisms. There are currently three failure mechanisms analyzed by RELIC: metal migration, hot electron trapping, and time dependent dielectric breakdown (TDDB). References [Chen85] I.C. Chen, S.E. Holland, and C. Hu "Electrical Breakdown in Thin Gate and Tunneling Oxides" IEEE Trans. Elec. Dev. 32: 413-422, 1985. [Glasser85] L. A. Glasser and D. W. Dobberpuhl. The Design and Analysis of VLSI Circuits, Reading, MA: Addison-Wesley, 1985. [Hohol86] T. S. Hohol "RELIC: A Reliability Simulator for Integrated Circuits" S.M. Thesis, Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1986. [Hsu82] F. C. Hsu, P. K. Ko, S. Tam, C. Hu, and R. S. Muller "An Analytical Breakdown Model for ShortChannel MOSFET's" IEEE Trans. Elec. Dev. 29: 1735-1740, 1982. [Iversen86] W. R. Iversen "Model May Help Solve Chip-Reliability Problem" Electronics pp. 20-21, March 24, 1986 [Kokkonen84] K. Kokkonen "The Interaction of Physics and CAD in VLSI CMOS Design" talk given at MIT Nov 1984. [Sakurai 84] T. Sakurai, M. Kakumu, T. Iizuka "Hot-Carrier Suppressed VLSI with Submicron Geometry" IEEE/ISSCC 272-273, 1985. [Sing80] Y. W. Sing and B. Sudlow "Modeling and VLSI Design Constraints of Substrate Current" IEEE/IEDM 732-734, 1980. [White85] J. K. White, and A. Sangiovanni-Vincentelli "RELAX2.1 - A Waveform Relaxation Based Circuit Simulation Program" Proc. 1984 Int. Custom Integrated Circuits Conference, Rochester, N.Y. June, 1984.