204 pin Unbuffered DDR3 SO-DIMM - Elixir Memory

M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Based on DDR3-1066/1333 128Mx16 (1GB) and DDR3-1066/1333/1600 256Mx8 (2GB/4GB) SDRAM B-Die

Features •Performance: Speed Sort

PC3-8500

PC3-10600

PC3-12800

-BE

-CG

-DG

DIMM CAS Latency

Unit

7

9

9

533

667

800

tck – Clock Cycle

1.875

1.5

1.25

ns

fDQ – DQ Burst Frequency

1066

1333

1600

Mbps

fck – Clock Frequency

MHz

• 240-Pin Dual In-Line Memory Module (UDIMM) •128Mx64 (1GB) / 256Mx64 (2GB) / 512Mx64 (4GB) DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM B-Die devices. • Intended for 533MHz/667MHz/800MHz applications • Inputs and outputs are SSTL-15 compatible • VDD = VDDQ = 1.5V ±0.075V • SDRAMs have 8 internal banks for concurrent operation • Differential clock inputs • Data is read or written on both clock edges • DRAM DLL aligns DQ and DQS transitions with clock transitions. • Address and control signals are fully synchronous to positive clock edge • Nominal and Dynamtic On-Die Termination support • Halogen free product

• Programmable Operation: - DIMM  Latency: 6,7,8,9 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write • Two different termination values (Rtt_Nom & Rtt_WR) • 14/10/1 (row/column/rank) Addressing for 1GB • 15/10/1 (row/column/rank) Addressing for 2GB • 15/10/2 (row/column/rank) Addressing for 4GB • Extended operating temperature rage • Auto Self-Refresh option • Serial Presence Detect • Gold contacts •1GB: SDRAMs are in 96-ball BGA Package • 2GB: SDRAMs are in 78-ball BGA Package • 4GB: SDRAMs are in 78-ball BGA Package • RoHS compliance

Description M2F1G64CBH4B5(9)P / M2F(X)2G64CB88B7N / M2F(X)4G64CB8HB5N / M2F(X)2G64CB88BHN / M2F(X)4G64CB8HB9N are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one rank of 128Mx64 (1GB) / 256Mx64 (2GB) and two ranks of 512Mx64 (4GB) high-speed memory array. Modules use four 128Mx16 (1GB) 96-ball BGA packaged devices, eight 256Mx8 (2GB) 78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint. The DIMM is intended for use in applications operating of 533MHz/667MHz/800MHz clock speeds and achieves high-speed data transfer rates of 1066Mbps/1333Mbps/1600Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 (1GB) / A0-A14 (2GB/4GB) and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

REV 1.0 05/2010

1 © NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Ordering Information Part Number

Speed

Organization

M2F1G64CBH4B5P-BE

DDR3-1066

PC3-8500 533MHz (1.875ns @ CL = 7)

M2F1G64CBH4B5P-CG

DDR3-1333

PC3-10600 667MHz (1.5ns @ CL = 9)

M2F2G64CB88B7N-BE

DDR3-1066

PC3-8500 533MHz (1.875ns @ CL = 7)

M2F2G64CB88B7N-CG

DDR3-1333

PC3-10600 667MHz (1.5ns @ CL = 9)

M2X2G64CB88B7N-DG

DDR3-1600

PC3-12800 800MHz (1.25ns @ CL=9)

M2F4G64CB8HB5N-BE

DDR3-1066

PC3-8500 533MHz (1.875ns @ CL = 7)

M2F4G64CB8HB5N-CG

DDR3-1333

PC3-10600 667MHz (1.5ns @ CL = 9)

M2X4G64CB8HB5N-DG

DDR3-1600

PC3-12800 800MHz (1.25ns @ CL=9)

M2F1G64CBH4B9P-BE

DDR3-1066

PC3-8500 533MHz (1.875ns @ CL = 7)

M2F1G64CBH4B9P-CG

DDR3-1333

PC3-10600 667MHz (1.5ns @ CL = 9)

M2F2G64CB88BHN-BE

DDR3-1066

PC3-8500 533MHz (1.875ns @ CL = 7)

M2F2G64CB88BHN-CG

DDR3-1333

PC3-10600 667MHz (1.5ns @ CL = 9)

M2X2G64CB88BHN-DG

DDR3-1600

PC3-12800 800MHz (1.25ns @ CL=9)

M2F4G64CB8HB9N-BE

DDR3-1066

PC3-8500 533MHz (1.875ns @ CL = 7)

M2F4G64CB8HB9N-CG

DDR3-1333

PC3-10600 667MHz (1.5ns @ CL = 9)

M2X4G64CB8HB9N-DG

DDR3-1600

PC3-12800 800MHz (1.25ns @ CL=9)

Power

Leads

1.5V

Gold

Note

128Mx64

256Mx64

512Mx64

128Mx64

256Mx64

512Mx64

Pin Description Pin Name

Description

Pin Name

Description

CK0, CK1

Clock Inputs, positive line

DQ0-DQ63

, 

Clock Inputs, negative line

DQS0-DQS8

Data strobes

Clock Enable

-

Data strobes complement

CKE0, CKE1 

Row Address Strobe



Column Address Strobe

 , 

DM0-DM8

Data input/output

Data Masks



Temperature event pin

Write Enable



Reset pin

Chip Selects

VREFDQ , VREFCA

A0-A9, A11, A13-A15 Address Inputs A10/AP

Address Input/Auto-Precharge

A12/

Address Input/Burst Chop

VDDSPD

Input/Output Reference SPD and Temp sensor power

SA0, SA1

Serial Presence Detect Address Inputs

Vtt

Termination voltage

BA0-BA2

SDRAM Bank Address Inputs

VSS

Ground

ODT0, ODT1

Active termination control lines

VDD

Core and I/O power

SCL

Serial Presence Detect Clock Input

NC

No Connect

SDA

Serial Presence Detect Data input/output

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin 1

Front

Pin

VREFDQ 121

Back

Pin

Front

Pin

Back

Pin

Front

Pin

Back

Pin

Front

Pin

Back

VSS

31

DQ25

151

VSS

61

A2

181

A1

91

DQ41

211

VSS

DM5, 212 DQS14, TDQS14 NC, 213 , 

2

VSS

122

DQ4

32

VSS

152

DM3,DQS12,T DQS12

62

VDD

182

VDD

92

VSS

3

DQ0

123

DQ5

33



153

NC, 

63

CK1,NC

183

VDD

93



4

DQ1

124

VSS

34

DQS3

154

VSS

64

,NC

184

CK0

94

DQS5

214

VSS

35

VSS

155

DQ30

65

VDD

185



95

VSS

215

DQ46

36

DQ26

156

DQ31

66

VDD

186

VDD

96

DQ42

216

DQ47

37

DQ27

157

VSS

67

VREFCA

187

, NC

97

DQ43

217

VSS

188

A0

98

VSS

218

DQ52

5

VSS

125

6

 126

7

DQS0 127

DM0,DQS9, TDQS9 NC,  VSS

158

CB4,NC

68

PAR_IN, NC

39

CB0,NC 159

CB5,NC

69

VDD

189

VDD

99

DQ48

219

DQ53

40

CB1,NC 160

VSS

70

A10/AP

190

BA1

100

DQ49

220

VSS

8

VSS

128

DQ6

38

9

DQ2

129

DQ7

10

DQ3

130

VSS

VSS

DM6, 221 DQS15, TDQS15 NC, 222 , 

11

VSS

131

DQ12

41

VSS

161

DM8,DQS17, TDQS17,NC

71

BA0

191

VDD

101

VSS

12

DQ8

132

DQ13

42



162

NC,, ,

72

VDD

192



102



13

DQ9

133

VSS

43

DQS8

163

VSS

73



193



103

DQS6

223

VSS

44

VSS

164

CB6,NC

74



194

VDD

104

VSS

224

DQ54

45

CB2,NC 165

CB7,NC

75

VDD

195

ODT0

105

DQ50

225

DQ55

VSS

46

CB3,NC 166

VSS

76

,NC

196

A13

106

DQ51

226

VSS

137

DQ14

47

VSS

167

NC(TEST)

77

ODT1,NC

197

VDD

107

VSS

227

DQ60

18

DQ10 138

DQ15

48

VTT,NC

168



78

VDD

198

,NC

108

DQ56

228

DQ61

19

DQ11 139

VSS

49

VTT,NC

169

CKE1/NC

79

,NC

199

VSS

109

DQ57

229

VSS

140

DQ20

50

CKE0

170

VDD

80

VSS

200

DQ36

110

VSS

230

21

DQ16 141

DQ21

51

VDD

171

A15,NC

81

DQ32

201

DQ37

111



22

DQ17 142

VSS

52

BA2

172

A14

82

DQ33

202

VSS

112

DQS7

232

VSS

VSS

233

DQ62

DQ58

234

DQ63

DQ59

235

VSS

DM1, DQS10, 134 TDQS10 NC, 135 

14

VSS

15



16

DQS1 136

17

VSS

20

VSS

23

VSS

143

DM2, DQS11, TDQS11

53

ERR_OUT 173 ,NC

VDD

83

VSS

DM4, 203 DQS13, 113 TDQS13 NC, 204 , 114 

24

 144

NC, 

54

VDD

174

A12/

84



25

DQS2 145

VSS

55

A11

175

A9

85

DQS4

205

VSS

115

26

VSS

DM7, DQS16, TDQS16 NC, 231 , 

146

DQ22

56

A7

176

VDD

86

VSS

206

DQ38

116

VSS

236

VDDSPD

27

DQ18 147

DQ23

57

VDD

177

A8

87

DQ34

207

DQ39

117

SA0

237

SA1

28

DQ19 148

VSS

58

A5

178

A6

88

DQ35

208

VSS

118

SCL

238

SDA

149

DQ28

59

A4

179

VDD

89

VSS

209

DQ44

119

SA2

239

VSS

DQ24 150

DQ29

60

VDD

180

A3

90

DQ40

210

DQ45

120

VTT

240

VTT

29 30

VSS

Note: CK1, , CKE1,  and ODT1 are for 4GB modules only.

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Input/Output Functional Description Symbol

Type

Polarity

Function

CK0, CK1 , 

Input

Cross point

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock.

CKE0, CKE1

Input

Active High

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.

, 

Input

Active Low

Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue, Rank 0 is selected by ; Rank 1 is selected by 

, , 

Input

Active Low

When sampled at the positive rising edge of CK and falling edge of , signals , ,  define the operation to be executed by the SDRAM.

ODT0, ODT1

Input

Active High

Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM mode register.

DM0 – DM8

Input

Active High

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.  signals are complements, and timing is relative to the cross point of respective DQS and . If the module is to be operated in single ended strobe mode, all  signals must be tied on the system board to VSS and DDR3 SDRAM mode registers programmed appropriately.

DQS0 – DQS8  – 

I/O

Cross point

BA0, BA1, BA2

Input

-

Selects which DDR3 SDRAM internal bank of four or eight is activated.

Input

-

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of . In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

A0 – A9 A10/AP A11 A12/ A13-A15

DQ0 – DQ63

Input

-

Data Input/Output pins.

VDD, VDDSPD, VSS

Supply

-

Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.

VREFDQ, VREFCA

Supply

-

Reference voltage for SSTL15 inputs

SDA

I/O

-

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.

SCL

Input

-

This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.

SA0 – SA2

Input

-

Address pins used to select the Serial Presence Detect and Temp sensor base address.



Output

-

The  pin is reserved for use to flag critical module temperature.



Input

-

This signal resets the DDR3 SDRAM

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM

    CK0  CKE0 ODT0 A[0:13]/BA[0:2]

Functional Block Diagram [1GB – 1 Rank, 128Mx16 DDR3 SDRAMs]

LDQS L LDM DQ[0:7] UDQS  UDM DQ[8:15]

DQS2  DM2 DQ[16:23] DQS3  DM3 DQ[24:31]


240ohm +/-1% ZQ

D0

    CK  CKE ODT A[0:13]/BA[0:2]

DQS0  DM0 DQ[0:7] DQS1  DM1 DQ[8:15]

240ohm +/-1% ZQ SCL D1

    CK  CKE ODT A[0:13]/BA[0:2]


DQS6  DM6 DQ[48:55] DQS7  DM7 DQ[56:63]


Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0

240ohm +/-1% ZQ

D2

 CK1   

    CK  CKE ODT A[0:13]/BA[0:2]

DQS4  DM4 DQ[32:39] DQS5  DM5 DQ[40:47]

SCL A0 A1 A2

SA0 SA1

SPD

SDA

WP

Vtt SPD / TS D0-D7 D0-D7 D0-D7 D0-D7, SPD, Temp sensor D0-D3 D0-D3 D4-D7 D4-D7 Temp Sensor D0-D7

240ohm +/-1% ZQ Notes : D3

    CK  CKE ODT A[0:13]/BA[0:2]

1. DQ wiring may differ from that shown however, DQ, DM, DQS, and relationships are maintained as shown.

Vtt

Vtt

VDD

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram [2GB – 1 Rank, 256Mx8 DDR3 SDRAMs]   DQS0 DM0

 DQS4 DM4 DM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

I/O I/O I/O I/O I/O I/O I/O I/O



DQS

0 1 2 3 4 5 6 7



DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

D0

ZQ

 DQS1 DM1




DQS

0 1 2 3 4 5 6 7




D1

ZQ

 DQS2 DM2




DQS

0 1 2 3 4 5 6 7



SA0 SA1

D2

ZQ




DQS

0 1 2 3 4 5 6 7

SCL A0 A1 A2



D3

ZQ

SPD SDA WP

CKE0, A[13:0], , , , ODT0, BA[2:0], 

VTT

DDR3 SDRAM CK 

05/2010

D4

ZQ



0 1 2 3 4 5 6 7


DQS



D5

ZQ



0 1 2 3 4 5 6 7


DDR3 SDRAM

REV 1.0



DQS



D6

ZQ

 DQS7 DM7 DM

SCL



 DQS3 DM3


DQS

 DQS6 DM6 DM




0 1 2 3 4 5 6 7

 DQS5 DM5 DM



VDD

VDDSPD VDD/VDDQ VREFDQ VSS VREFCA BA0-BA2 A0-A13   CKE0  ODT0 CK0  


0 1 2 3 4 5 6 7



DQS



D7

ZQ

SPD D0-D7 D0-D7 D0-D7 D0-D7 BA0-BA2: SDRAMs D0-D7 A0-A13: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 CKE: SDRAMs D0-D7 : SDRAMs D0-D7 ODT: SDRAMs D0-D7 CK: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7

Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 240Ω±1%. 4. One SPD exists per module.



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram [4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs]    DQS0 DM0


 DQS4 DM4 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D0 I/O 4 I/O 5 I/O 6 I/O 7

DQS

DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D8 I/O 4 I/O 5 I/O 6 I/O 7

ZQ

DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

ZQ

 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15


DQS


ZQ


ZQ

DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

CS

DQS

DQS

D4

ZQ


DQS


DQS


DQS

ZQ

DQS

DQS

D5

ZQ

ZQ

DQS6 DQS6 DM6 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D2 I/O 4 I/O 5 I/O 6 I/O 7

DQS


ZQ


ZQ

 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

CS

 DQS5 DM5

 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23



DQS


DQS

ZQ

CS

DQS

D14

ZQ

 DQS7 DM7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D3 I/O 4 I/O 5 I/O 6 I/O 7

DQS


ZQ

CS

DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

D11

ZQ

VDDSPD VDD/VDDQ VREFDQ VSS VREFCA BA0-BA2 A0-A13    CKE0 CKE1 ODT0 ODT1 CK0  CK1  

DDR3 SDRAM

CKE[1:0], A[13:0], , , , ODT[1:0], BA[2:0], [1:0]

VTT

DDR3 SDRAM CK 

SCL SA0 SA1

VDD

SCL A0 A1 A2

SPD SDA WP

ZQ


DQS

ZQ

SPD D0-D15 D0-D15 D0-D15 D0-D15 BA0-BA2: SDRAMs D0-D15 A0-A13: SDRAMs D0-D15 : SDRAMs D0-D15 : SDRAMs D0-D15 : SDRAMs D0-D15 CKE: SDRAMs D0-D7 CKE: SDRAMs D8-D15 ODT: SDRAMs D0-D7 ODT: SDRAMs D8-D15 CK: SDRAMs D0-D7 : SDRAMs D0-D7 CK: SDRAMs D8-D15 : SDRAMs D8-D15 : SDRAMs D8-D15

Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 240Ω±1%. 4. One SPD exists per module.

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect [M2F1G64CBH4B5(9)P ,1GB – 1 Rank, 128Mx16 DDR3 SDRAMs] Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 60 61 62 63 117 118 119-121 126 127 128-145 146 147 150-175 176-255

REV 1.0 05/2010

Serial PD Data Entry (Hex.) -BE -CG 92 92 10 10 0B 0B 02 02 03 03 11 11 00 00 02 02 03 03 52 52 01 01 08 08 0F 0C 00 00 1C 3C 00 00 69 69 78 78 69 69 50 3C 69 69 11 11 2C 20 95 89 00 00 05 05 3C 3C 3C 3C 01 01 90 68 83 83 05 05 00 00 00 00 0F 0F 01 01 02 02 00 00 83 83 0B 0B --73 0D F7 2E -----------

Description CRC range, EEPROM bytes, bytes used SPD revision DRAM device type Module type (form factor) SDRAM Device density and banks SDRAM device row and column count Module minimum nominal voltage Module ranks and device DQ count ECC tag and module memory Bus width Fine timebase dividend/divisor (in ps) Medium timebase dividend Medium timebase divisor Minimum SDRAM cycle time (tCKmin) Reserved CAS latencies supported CAS latencies supported Minimum CAS latency time (tAAmin) Minimum write recovery time (tWRmin) Minimum CAS-to-CAS delay (tRCDmin) Minimum Row Active to Row Active delay (tRRDmin) Minimum row Precharge delay (tRPmin) Upper nibble for tRAS and tRC Minimum Active-to-Precharge delay (tRASmin) Minimum Active-to-Active/Refresh delay (tRCmin) Minimum refresh recovery delay (tRFCmin) LSB Minimum refresh recovery delay (tRFCmin) MSB Minimum internal Write-to-Read command delay (tWTRmin) Minimum internal Read-to-Precharge command delay (tRTPmin) Minimum four active window delay (tFAWmin) LSB Minimum four active window delay (tFAWmin) MSB SDRAM device output drivers supported SDRAM device thermal and refresh options Module Thermal Sensor SDRAM Device Type Module height (nominal) Module thickness (Max) Raw Card ID reference DRAM address mapping edge connector Module manufacture ID Module manufacture ID Module manufacturer Information CRC CRC Module part number Module die revision Module PCB revision Manufacturer reserved Intel Extreme Memory Profile(XMP)



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM

Serial Presence Detect [M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN , 2GB – 1 Rank, 256Mx8 DDR3 SDRAMs] Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 60 61 62 63 117 118 119-121 126 127 128-145 146 147 150-175 176-255

REV 1.0 05/2010

Serial PD Data Entry (Hex.) -BE -CG -DG 92 92 93 10 10 10 0B 0B 0B 02 02 02 03 03 03 19 19 19 00 00 00 01 01 01 03 03 03 52 52 52 01 01 01 08 08 08 0F 0C 0A 00 00 00 1C 3C 7E 00 00 00 69 69 64 78 78 78 69 69 64 3C 30 30 69 69 64 11 11 11 2C 20 18 95 89 7C 00 00 00 05 05 05 3C 3C 3C 3C 3C 3C 01 00 00 2C F0 F0 83 83 83 05 05 05 00 00 00 00 00 00 0F 0F 0F 01 01 01 01 01 01 01 01 01 83 83 83 0B 0B 0B ---47 05 FB 29 80 32 ----------------




M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect [M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N , 4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs] Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 60 61 62 63 117 118 119-121 126 127 128-145 146 147 150-175 176-255

REV 1.0 05/2010

Serial PD Data Entry (Hex.) -BE -CG -DG 92 92 93 10 10 10 0B 0B 0B 02 02 02 03 03 03 19 19 19 00 00 00 09 09 09 03 03 03 52 52 52 01 01 01 08 08 08 0F 0C 0A 00 00 00 1C 3C 7E 00 00 00 69 69 64 78 78 78 69 69 64 3C 30 30 69 69 64 11 11 11 2C 20 18 95 89 7C 00 00 00 05 05 05 3C 3C 3C 3C 3C 3C 01 00 00 2C F0 F0 83 83 83 05 05 05 00 00 00 00 00 00 0F 0F 0F 11 11 11 01 01 01 01 01 01 83 83 83 0B 0B 0B ---68 2A D4 59 F0 42 ----------------




M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Intel Extreme Memory Profile definition Serial Presence Detect [M2X2G64CB88B7N / M2X2G64CB88BHN , 2GB – 1 Rank, 256Mx8 DDR3 SDRAMs] Byte 176-177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211-218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246-253 254

Serial PD Data Entry (Hex.) -BE -CG -DG --OC4A --07 --12 --01 --08 --01 --0E --00 --2D --0A --5A --24 --00 --5A --5A --5A --78 --11 --18 --72 --20 --00 --00 --05 --3C --30 --00 --F0 --3C --00 --00 --10 --00 --2D -----00 --2D --0F --A5 --84 --00 --A5 --A5 --A5 --D2 --21 --EA --8F --37 --00 --C0 --08 --69 --54 --01 --A4 --69 --00 --00 --1C --00 --2D -------

Description Intel Extreme Memory Profile ID String Intel Extreme Memory Profile Organization Type Intel Extreme Memory Profile Revision Medium Timebase Dividend for Profile 1 Medium Timebase Divisor for Profile 1 Medium Timebase Dividend for Profile 2 Medium Timebase Divisor for Profile 2 RSVD 1 Module VDD Voltage Level for Profile 1 (Certified Settings) SDRAM Minimum Cycle Time (tCKmin) Minimum CAS Latency Time (tAAmin) CAS Latencies Supported, Least Significant Byte (CL MASK) CAS Latencies Supported, Most Significant Byte (CL MASK) Minimum CAS Write Latency Time (tCWLmin) Minimum Row Precharge Time (tRPmin) Minimum RAS# to CAS# Delay Time (tRCDmin) Minimum Write Recovery Time (tWRmin) Upper Nibbles for tRAS and tRC Minimum Active to Precharge Time (tRASmin), Least Significant Byte Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte Maximum tREFI Time (Average Periodic Refresh Interval) – LSB Maximum tREFI Time (Average Periodic Refresh Interval) - MSB Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte Minimum Internal Read to Precharge Command Delay Time (tRTPmin) Minimum Row Active to Row Active Delay Time (tRRDmin) Upper Nibble for tFAW Minimum Four Activate Window Delay Time (tFAWmin) Minimum Internal Write to Read Command Delay Time (tWTRmin) Write to Read & Read to Write CMD Turn-around Time Pull-in Back to Back CMD Turn-around Time Pull-in System ADD/CMD Rate (1N or 2N mode) Auto Self Refresh Performance (Sub 1x Refresh and IDD6 Impacts) Memory Controller Voltage Level for Profile 1 RSVD Vendor Personality Byte for Profile 1 - RSVD Module VDD Voltage Level for Profile 2 (Extreme Settings) SDRAM Minimum Cycle Time (tCKmin) Minimum CAS Latency Time (tAAmin) CAS Latencies Supported, Least Significant Byte (CL MASK) CAS Latencies Supported, Most Significant Byte (CL MASK) Minimum CAS Write Latency Time (tCWLmin) Minimum Row Precharge Time (tRPmin) Minimum RAS# to CAS# Delay Time (tRCDmin) Minimum Write Recovery Time (tWRmin) Upper Nibbles for tRAS and tRC Minimum Active to Precharge Time (tRASmin), Least Significant Byte Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte Maximum tREFI Time (Average Periodic Refresh Interval) - LSB Maximum tREFI Time (Average Periodic Refresh Interval) - MSB Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte Minimum Internal Read to Precharge Command Delay Time (tRTPmin) Minimum Row Active to Row Active Delay Time (tRRDmin) Upper Nibble for tFAW Minimum Four Activate Window Delay Time (tFAWmin) Minimum Internal Write to Read Command Delay Time (tWTRmin) Write to Read & Read to Write CMD Turn-around Time Pull-in Back to Back CMD Turn-around Time Pull-in System ADD/CMD Rate (1N or 2N mode) Auto Self Refresh Performance (Sub 1x Refresh and IDD6 Impacts) Memory Controller Voltage Level for Profile RSVD Vendor Personality Byte for Profile 2 - RSVD

Note

1 1 1 1 1 1 2,4 2,4 2,4 2,4 2 2,4 2,4 2,4 2,4 2,4 2,4 2 2 2,4 2,4 2,4 2,4 2,4 2,4 2,4 2 2 2 2 2 2 3,4 3,4 3,4 3,4 3,4 3 3,4 3,4 3,4 3,4 3,4 3,4 3 3 3,4 3,4 3,4 3,4 3,4 3,4 3,4 3 3 3 3 3 3 3 3

1. Global Parameters used across all profiles 2. Utilized for Profile 1 (Enthusiast / Certified Settings) 3. Utilized for Profile 2 (Extreme Settings) 4. Parameter utilized in the same fashion as the standard DDR3 SPD byte with the exception that it may exceed the DDRx SDRAM datasheet

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect [M2X4G64CB8HB5N / M2X4G64CB8HB9N , 4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs] Byte 176-177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211-218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246-253 254

Serial PD Data Entry (Hex.) -BE -CG -DG --0C4A --07 --12 --01 --08 --01 --0E --00 --2D --0A --5A --24 --00 --5A --5A --5A --78 --11 --18 --72 --20 --00 --00 --05 --3C --30 --00 --F0 --3C --00 --00 --10 --00 --2D -----00 --2D --0F --A5 --84 --00 --A5 --A5 --A5 --D2 --21 --EA --8F --37 --00 --C0 --08 --69 --54 --01 --A4 --69 --00 --00 --1C --00 --2D -------

Description Intel Extreme Memory Profile ID String Intel Extreme Memory Profile Organization Type Intel Extreme Memory Profile Revision Medium Timebase Dividend for Profile 1 Medium Timebase Divisor for Profile 1 Medium Timebase Dividend for Profile 2 Medium Timebase Divisor for Profile 2 RSVD 1 Module VDD Voltage Level for Profile 1 (Certified Settings) SDRAM Minimum Cycle Time (tCKmin) Minimum CAS Latency Time (tAAmin) CAS Latencies Supported, Least Significant Byte (CL MASK) CAS Latencies Supported, Most Significant Byte (CL MASK) Minimum CAS Write Latency Time (tCWLmin) Minimum Row Precharge Time (tRPmin) Minimum RAS# to CAS# Delay Time (tRCDmin) Minimum Write Recovery Time (tWRmin) Upper Nibbles for tRAS and tRC Minimum Active to Precharge Time (tRASmin), Least Significant Byte Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte Maximum tREFI Time (Average Periodic Refresh Interval) – LSB Maximum tREFI Time (Average Periodic Refresh Interval) - MSB Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte Minimum Internal Read to Precharge Command Delay Time (tRTPmin) Minimum Row Active to Row Active Delay Time (tRRDmin) Upper Nibble for tFAW Minimum Four Activate Window Delay Time (tFAWmin) Minimum Internal Write to Read Command Delay Time (tWTRmin) Write to Read & Read to Write CMD Turn-around Time Pull-in Back to Back CMD Turn-around Time Pull-in System ADD/CMD Rate (1N or 2N mode) Auto Self Refresh Performance (Sub 1x Refresh and IDD6 Impacts) Memory Controller Voltage Level for Profile 1 RSVD Vendor Personality Byte for Profile 1 - RSVD Module VDD Voltage Level for Profile 2 (Extreme Settings) SDRAM Minimum Cycle Time (tCKmin) Minimum CAS Latency Time (tAAmin) CAS Latencies Supported, Least Significant Byte (CL MASK) CAS Latencies Supported, Most Significant Byte (CL MASK) Minimum CAS Write Latency Time (tCWLmin) Minimum Row Precharge Time (tRPmin) Minimum RAS# to CAS# Delay Time (tRCDmin) Minimum Write Recovery Time (tWRmin) Upper Nibbles for tRAS and tRC Minimum Active to Precharge Time (tRASmin), Least Significant Byte Minimum Active to Active/Refresh Time (tRCmin), Least Significant Byte Maximum tREFI Time (Average Periodic Refresh Interval) - LSB Maximum tREFI Time (Average Periodic Refresh Interval) - MSB Minimum Refresh Recovery Time (tRFCmin), Least Significant Byte Minimum Refresh Recovery Time (tRFCmin), Most Significant Byte Minimum Internal Read to Precharge Command Delay Time (tRTPmin) Minimum Row Active to Row Active Delay Time (tRRDmin) Upper Nibble for tFAW Minimum Four Activate Window Delay Time (tFAWmin) Minimum Internal Write to Read Command Delay Time (tWTRmin) Write to Read & Read to Write CMD Turn-around Time Pull-in Back to Back CMD Turn-around Time Pull-in System ADD/CMD Rate (1N or 2N mode) Auto Self Refresh Performance (Sub 1x Refresh and IDD6 Impacts) Memory Controller Voltage Level for Profile RSVD Vendor Personality Byte for Profile 2 - RSVD

Note

1 1 1 1 1 1 2,4 2,4 2,4 2,4 2 2,4 2,4 2,4 2,4 2,4 2,4 2 2 2,4 2,4 2,4 2,4 2,4 2,4 2,4 2 2 2 2 2 2 3,4 3,4 3,4 3,4 3,4 3 3,4 3,4 3,4 3,4 3,4 3,4 3 3 3,4 3,4 3,4 3,4 3,4 3,4 3,4 3 3 3 3 3 3 3 3

1. Global Parameters used across all profiles 2. Utilized for Profile 1 (Enthusiast / Certified Settings) 3. Utilized for Profile 2 (Extreme Settings) 4. Parameter utilized in the same fashion as the standard DDR3 SPD byte with the exception that it may exceed the DDRx SDRAM datasheet

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Environmental Requirements Symbol

Rating

Units

Note

TOPR

Module Operating Temperature Range (ambient)

Parameter

0 to 55

°C

3

HOPR

Operating Humidity (relative)

10 to 90

%

1

TSTG

Storage Temperature (Plastic)

-55 to 100

°C

1

HSTG

Storage Humidity (without condensation)

5 to 95

%

1

PBAR

Barometric Pressure (operating & storage)

105 to 69

K Pascal

1, 2

Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. The component maximum case temperature shall not exceed the value specified in the component spec.

Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG

Parameter

Rating

Units

Note

Voltage on VDD pins relative to Vss

-0.4 V ~ 1.975 V

V

1, 3

Voltage on VDDQ pins relative to Vss

-0.4 V ~ 1.975 V

V

1, 3

Voltage on I/O pins relative to Vss

-0.4 V ~ 1.975 V

V

1

-55 to +100

°C

1, 2

Storage Temperature

Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater

Operating temperature Conditions Symbol TOPER

Rating

Units

Note

Normal Operating Temperature Range

Parameter

0 to 85

°C

1, 2

Extended Temperature Range

85 to 95

°C

1, 3

Note: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 to 85 °C under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case temperature. Full specifications are supported in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs. It is also possible to specify a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range.

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions Symbol VDD VDDQ

Min

Typ

Max

Units

Notes

Supply Voltage

Parameter

1.425

1.5

1.575

V

1,2

Output Supply Voltage

1.425

1.5

1.575

V

1,2

Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

Single-Ended AC and DC Input Levels for Command and Address Symbol

Parameter

DDR3-1066 (-BE) Min.

DDR3-1333 (-CG)

Max.

Min.

DDR3-1600(-DG)

Max.

Min.

Max.

Units Note

VIH.CA(DC)

DC Input Logic High

Vref + 0.100

VDD

Vref + 0.100

VDD

Vref + 0.100

VDD

V

1

VIL.CA(DC)

DC Input Logic Low

VSS

Vref - 0.100

VSS

Vref - 0.100

VSS

Vref - 0.100

V

1

VIH.CA(AC)

AC Input Logic High

Vref + 0.175

Note 2

Vref + 0.175

Note 2

Vref + 0.175

Note 2

V

1, 2

VIL.CA(AC)

AC Input Logic Low

Note 2

Vref - 0.175

Note 2

Vref - 0.175

Note 2

Vref - 0.175

V

1, 2

VIH.CA(AC150) AC Input Logic High

Vref + 0.15

Note 2

Vref + 0.15

Note 2

Vref + 0.15

Note 2

V

1, 2

VIL.CA(AC150) AC Input Logic Low

Note 2

Vref - 0.15

Note 2

Vref - 0.15

Note 2

Vref - 0.15

V

1, 2

0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD

V

3, 4

VRefCA(DC)

Reference Voltage for ADD, CMD Inputs

Note: 1. For input only pins except RESET#. Vref = VrefCA(DC). 2. See “Overshoot and Undershoot Specifications” in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV.

Single-Ended AC and DC Input Levels for DQ and DM Symbol

Parameter

DDR3-1066 (-BE) Min.

DDR3-1333 (-CG)

Max.

Min.

DDR3-1600 (-DG)

Max.

Min.

Max.

Units

Note 1

VIH.DQ(DC) DC Input Logic High

Vref + 0.100

VDD

Vref + 0.100

VDD

Vref + 0.100

VDD

V

VIL.DQ(DC) DC Input Logic Low

VSS

Vref - 0.100

VSS

Vref - 0.100

VSS

Vref - 0.100

V

1

VIH.DQ(AC) AC Input Logic High

Vref + 0.175

Note 2

Vref + 0.15

Note 2

Vref + 0.15

Note 2

V

1, 2, 5

VIL.DQ(AC) AC Input Logic Low

Note 2

Vref - 0.175

Note 2

Vref - 0.15

Note 2

Vref - 0.15

V

1, 2, 5

0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD

V

3, 4

VRefDQ(DC)

Reference Voltage for DQ, DM Inputs

Note: 1. For input only pins except RESET#. Vref = VrefDQ(DC). 2. See “Overshoot and Undershoot Specifications” in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. 5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV (peak to peak).

REV 1.0 05/2010



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [1GB – 1 Rank, 128Mx16 DDR3 SDRAMs] Symbol

Parameter/Condition

IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7

Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current

PC3-8500 (-BE)

PC3-10600 (-CG)

Unit

289 424 21 62 92 100 67 104 759 746 732 25 1148

310 456 21 69 104 113 74 118 922 899 746 25 1338

mA mA mA mA mA mA mA mA mA mA mA mA mA

Operating, Standby, and Refresh Currents TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [2GB – 1 Rank, 256Mx8 DDR3 SDRAMs] Symbol

Parameter/Condition



PC3-8500 (-BE) 577 725 33 104 167 182 114 236 1011 1028 1531 83 2590

PC3-10600 (-CG) 579 750 48 132 204 220 144 231 1302 1239 1507 56 2997

PC3-12800 (-DG) 609 790 51 143 185 243 158 255 1510 1438 1531 56 3062

PC3-10600 (-CG) 810 980 95 264 408 440 289 461 1533 1470 1737 113 3228

PC3-12800 (-DG) 864 1045 102 285 370 486 317 510 1765 1693 1786 113 3318

Unit mA mA mA mA mA mA mA mA mA mA mA mA mA

Operating, Standby, and Refresh Currents TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs] Symbol

Parameter/Condition



REV 1.0 05/2010

PC3-8500 (-BE) 813 961 66 209 333 364 228 472 1247 1264 1767 167 2826

Unit mA mA mA mA mA mA mA mA mA mA mA mA mA



M2F1G64CBH4B5P/ M2F1G64CBH4B9P M2F(X)2G64CB88B7N / M2F(X)2G64CB88BHN M2F(X)4G64CB8HB5N / M2F(X)4G64CB8HB9N 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 / PC3-12800 Unbuffered DDR3 SDRAM DIMM Standard Speed Bins DDR3-1066MHz Speed Bin CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL=5 CL=5 CWL=6 CWL=5 CL=6 CWL=6 CWL=5 CL=7 CWL=6 CWL=5 CL=8 CWL=6 Supported CL Settings Supported CWL Settings

Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG)

DDR3-1066 7-7-7 (-BE) Min 13.125 13.125 13.125 50.625 37.500 3.000 Reserved 2.500 Reserved Reserved 1.875 Reserved 1.875 6,7,8 5,6

Max 20.000 9*tREFI 3.300 3.300

204 pin Unbuffered DDR3 SO-DIMM - Elixir Memory

204 pin Unbuffered DDR3 SO-DIMM - Elixir Memory

Suggest Documents