A CMOS class-E Power Amplifiers with Power Control Tongqiang Gao, Dongmei Li
Baoyong Chi, Zhihua Wang
Department of Electronic Engineering Tsinghua University Beijing, 100084, P. R. China
[email protected]
Institute of Microelectronics Tsinghua University Beijing, 100084, P. R. China
Abstract—In this paper, a CMOS class-E power amplifier with power control is presented. Its output power could be varied over a broad range with high efficiency by utilizing the combination of the parallel amplification technique and the drain modulation technique. The drain modulation is implemented as a class-S modulator and the output powers of the parallel amplifiers are combined with quarter-wavelength transmission lines. The simulation results show that the power amplifier could achieves a maximum power-added efficiency (PAE) of 47.9% and maintain a PAE higher than 41% over the 140-700mW output power range.
I. INTRODUCTION With the rapid development of handset wireless devices such as cellular phone and RFID (radio frequency identification), low power IC products are highly desired. To be the power boosting component in the wireless transmitter, the power amplifier (PA) is the largest power dissipation device. The working life of a handset device is mostly determined by PA’s efficiency. Being a mainstream IC process, CMOS technology has the advantages of lower cost and lower power. It would be necessary to implement PA in CMOS process although many challenges exist. In radio frequency applications, the switched-mode PA, such as the class-E or the class-F amplifier, could get the highest efficiency. A typical PA would achieve its peak efficiency at a specific output power (usually the maximum output power), and the efficiency drops rapidly as the output power lowers. Since the output power of the transmitter is statistically below the maximum for most of the transmission time [1], the average efficiency is well below its highest value. So, to keep a high efficiency over a wide output power range is highly desirable. Power control is a method to obtain higher average efficiency. Two main power control approaches exist: analog control and digital control. The analog approach can be implemented by changing the bias, adjusting the supply voltage, or adopting some specific structures, such as Doherty amplifier, etc. [1]-[3]. It has a smooth potential of efficiency variation but a small output power range. The digital approach is to change the size of the output stage
devices, the size of the driver stage devices or the amplitude of the input signal [4]-[7]. It has a wider output power range but a rough potential of efficiency variation. Aiming at the above limitations, this paper introduces a power control technique with the combination of the parallel amplification and the drain modulation. The proposed architecture consists of two identical CMOS class-E amplifiers, their output powers are controlled by DSP (digital signal process) signal and then combined in a power-combination network formed by the quarterwavelength ( λ 4 ) transmission lines. Meanwhile the supply voltage is modulated by class-S amplifier. Simulation results verify the feasibility of the proposed scheme. II.
Figure 1. Scheme of the parallel-amplifier
The diagram of the proposed scheme is illustrated in Fig. 1. The input RF signal is divided into two identical signals by a power divider. A class-S amplifier modulates the duty cycle of the pulse signal from DSP unit and then modulates the supply voltage for the amplifier module. The amplifier module includes two identical CMOS class E PAs. The total output power can be provided by one single amplifier or by two amplifiers simultaneously. To implement such an amplification scheme, it must be able to switch between the
Project supported by the National Natural Science Fundation of China . (No. 90407006) and National High Technology Research and Development Program of China (No. 2004AA1Z1100)
1-4244-0921-7/07 $25.00 © 2007 IEEE.
ARCHITECTURE
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different amplifiers and combine their output powers efficiently. A. Class-E Power Amplifier Among the switched-mode PAs, class-E is the most attractive candidate in term of its circuit simplicity and high frequency performance [8]. A typical class-E PA consists of a switch transistor ( M 1 ) and a passive network ( L1 , C1 , L 2 , C 2 ) as shown in Fig. 2. The input square-wave signal Vin toggles the switch transistor periodically with a frequency of ω 0 . L1 acts as either a RF choke or a finite DC-feed inductance. C1 represents the parasitic capacitance of the switch transistor and an additional shunt capacitor. L 2 and C 2 form a series LC resonator as a band-pass filter to pass the baseband signal and suppress the harmonics in the load of Ropt .
D amplifier. The control signal Vctrl is a pulse width modulated signal (PWM) from DSP. Voltage VLPFin is a square wave with levels 0 and + Vdd . The low-pass filter allows the dc component of VLPFin to pass and generate the output voltage Vout in the load Rload . Vdd
Cb LPF DSP
Vctrl
Vout
V LPFin
L0 C0
Figure 3.
Rload (PA drain)
Basic class-S amplifier
Ideally, the output voltage and current are never nonzero simultaneously. Therefore, the efficiency of the class-S amplifier is 100%. In practice, the efficiency reduces due to the static loss and the dynamic loss. By changing the duty cycle of the control signal Vctrl , various output voltage are generated. C. Parallel Amplification Architecture r s1
Figure 2. Basic configuration of class-E power amplifier
These elements are designed so that the conditions of the soft switching for class-E operation are met: 1) voltage across the switch is zero when the switch turns on; 2) the first derivation of the voltage across the switch is zero when the switch turns on. These conditions ensure no overlapping between the current and voltage waveform over the whole period. So the switch transistor has no power consumption and a theoretical efficiency of 100% can be achieved. To the class-E PA, the load impedance can be calculated using the equations R opt =
2 8 × V dd 2 P out π + 4
(
（1）
)
Then, it can be derived that P = out
2 8 × Vdd
(
R opt π 2 + 4
)
. So the
output power of class-E PA depends on its supply voltage and load Ropt . Power control to class-E PA can be achieved by changing the supply voltage. B. Class-S Amplifier A typical class-S amplifier, shown in Fig.3, consists of a switch-mode amplifier and a low-pass filter (LPF) [9]. A large capacitance Cb will bypass all ac signal components from Vdd to ground. The switch-mode amplifier is a Class
Z
V in1
Z in1
o1 , λ / 4
Z
out1
V out
r s2
Z V in2
Z
in2
o2 , λ / 4
R L Z
out2
Figure 4. Power combination using transmission lines
The principle of the parallel amplification is to employ several amplifiers in parallel, and provide the different output power levels among different output power regions. The maximum output power can be obtained when two signal sources works simultaneously. As the required output power reduces, the amplification can be accomplished by a single amplifier that maintains a high efficiency within a new region. In order to implement such an idea it is necessary to switch between different amplifiers and combine their output power efficiently. A simplified model for the power-combination architecture is shown in Fig. 4. Two λ 4 transmission lines, driven by voltage sources V in1 and V in2 , are connected together with a resistive load R L . It is well known that a λ 4 transmission line with characteristic impedance of Z o converts a load
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resistance RL into an impedance Z in = Z o2 Z L . Hence, the output impedance of each branch in Fig. 4, calculated after shorting the corresponding source, is infinite since the source impedance is zero. The power-combining structure is a linear system and the voltage at the output terminal can be calculated using the superposition principle. If one of the voltage sources, V in1 , is shorted to ground, the output impedance of its corresponding branch is infinite and the voltage generated by the other source at the load terminal is
RL Vin 2 ， where Zo2 is the characteristic Zo2 impedance of the corresponding branch. According to the superposition principle, if both sources are in function, the output voltage then equals the sum of the voltages that each source would generate in the absence of the other [5]. Vout |Vin1 =0 =
Vout =
RL R Vin1 + L Vin 2 Z o1 Zo2
(2)
When taking the finite source impedance ( rs1 , rs2 ) into account, the output voltage of the network is given by Vout =
Z o1Z o 2 RL Z o21rs 2 RL
+ Z o22 rs1RL + Z o21Z o22
( Z o 2Vin1 + Z o1Vin 2 ). (3)
It shows that the power combination with two voltage sources is fulfilled. III.
IMPLEMENTATION
L R
V dd
V dd
L
5
L 1
4
f
M C L
in
C
f
C
C 5
in
M V in V g3
M
4 V g2
2
L
C 1
2
4
C
2
TL
0 R
L
M 1
3
M 2 is a thick gate transistor with the aspect ratio of 6290 µm/0.34 µm. The λ 4 transmission line TL0, which is implemented with a microstrip line in printed circuit board, transforms the antenna resistance (50 Ω ) into a lower value Ropt (7.5 Ω) illustrated in Fig. 2. In the driver stage, a thick gate transistor M3 is used to increase the supply voltage. The on-chip inter-stage matching network consists of L5, C5 and L4, C4, respectively. Class-A amplifier is utilized in the first stage. Meanwhile, Rf and Cf form a feedback network to increases the stability. Circuit performance of the designed PA is simulated. From the simulated curves of AM-AM conversion and the power added efficiency (PAE) at 915MHz, it can be seen that the amplifier is capable of providing an output power above 25dBm with 50.4% PAE.
B. Class-S Amplifier and Drain modulation The class-S modulator is designed to drive a 7 Ω load which is the impedance seen into the drain of class-E PA. It is well known that the mobility of PMOS transistor and NMOS transistor is inherently unequal. The lengths of all transistors are equal. Based on the process parameters and the simulation result the width of PMOS transistors was selected to be about 3 times that of NMOS transistors. The low-pass filter is realized with off-chip components. The 3dB frequency of the filter is designed to be about 1MHz. By changing the duty cycle of the drive signal Vctrl , variable voltage supply is obtained through class-S modulator, leading to a smooth PAE variation. Simulation results show that a PAE range of 40.9-47.2% is provided among the output power range of 90-310mW. The purpose of power control of a single PA is satisfied.
A. Implementation of Class-E PA V dd
gate transistor with the aspect ratio of 5610 µm/0.18 µm and
V g1
Figure 5. Schematic of class-E power amplifier
The implemented three-stage class-E PA is shown in Fig. 5. The operating frequency is 915MHz. The three stages work at class A, class AB and class E, respectively. Each stage provides a about 10dB power gain. Except the L2-C2 series resonator and λ 4 transmission lines, all the other components are integrated. Because the highest drain voltage of the class-E power stage can be over 3 times the supply voltage and the CMOS process sets the breakdown voltage limit for the transistors, a cascode structure is adopted in the output stage to enhance the voltage supply and protect the transistors. M 1 is a thin
C. Power Control Fig. 6 shows a simplified schematic of the parallelamplifier unit. Switched cascode transistors as well as the series resonating circuit L2-C2 are used as low impedance sources, driving the λ 4 transmission lines. Each amplifier can be turned off without interfering the operation of the other one, as long as sufficient low output impedance is maintained by the off amplifier. This problem is overcome by introducing a PMOS switch that pulls the output of the non-amplifying branches to the positive supply rail. The function of PMOS transistor is as follows. When the branch amplifier is in the amplification mode, the gate of the corresponding PMOS transistor is tied toVdd . The parasitic capacitance introduced by this PMOS transistor is absorbed into the capacitance at the output node. The total capacitance at the node is resonated out by the drain inductive load of the amplifier. When the amplifier is in non-amplifying mode, PMOS transistor is turned on by tying its gate to ground. Thus, high impedance is maintained
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at the output terminal of the corresponding λ 4 transmission line. Meanwhile, to ground the gate of the transistors can decrease the power dissipation of the off-mode amplifier, leading to a higher PAE.
whole amplification architecture, including the PA and the class-S modulator. The simulated curve of PAE versus different output power is shown in Fig. 7. The circle-line shows the desired efficiency of the proposed structure at the various output power level. The dashed line shows the simulation results without modulation. Finally, the parallel architecture can provide a maximum output power of 700mW. The circuit achieves a highest PAE of 47.9% and maintains a PAE higher than 41% for the 140-700mW output power range. V. CONCLUSION This paper introduced a feasible CMOS class-E power amplifier architecture for power control with the combination of parallel amplification and drain modulation. Drain modulation is achieved by a class-S modulator. Power combination is implemented by the quarter-wavelength transmission lines. An experimental prototype is implemented in CMOS process. Simulation results show the feasibility of this power control architecture. It can achieves a highest power-added efficiency (PAE) of 47.9% and maintains a PAE greater than 41% over the 140-700mW output power range.
Figure 6. Implemented parallel power amplifier
Power adjustment is implemented by combining the output powers of the two identical amplifiers through λ 4 transmission lines and varying the supply voltage of PAs. The larger output power range is determined by the digital control signal b0/b1 from DSP unit. The little adjustment of the output power is determined by changing the supply voltage of PAs, when applying PWM signal Vctrl to class-S modulator. The input impedance of the designed class-E PA is not 50 Ω, but 56 Ω. So a two-branch Wilkinson power divider is designed to halve the input signal equally. It consists of three λ 4 transmission lines and a protect resistor.
REFERENCES [1] Gary Hanington, etc., “High efficiency power amplifier using dynamic
[2] [3]
[4]
[5]
IV.
SIMULATION RESULTS [6]
[7]
[8] [9] Figure 7. Performance of PAE vs Pout of the parallel structure
The proposed amplifier in Fig. 1 is implemented in UMC 0.18 µm CMOS process. The efficiency here is to the
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power-supply voltage for CDMA applications”, IEEE Transactions on Microwave Theory and Techniques, Vol. 47, No. 8, pp.1471-1476, Aug. 1999. S. C. Cripps, “RF power amplifier for wireless communications”, Norwood, MA: Artech, 1999. Peter M. Asbeck, Lawrence E. Larson, and Ian G. Galton, “Synergistic design of DSP and power amplifier for wireless communications”, IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 11, pp.2163-2168, Nov. 2001. M. M. Hella and M. Ismail, “2GHz controllable power amplifier in standard CMOS process for short-range wireless applications”, IEE Proc.-Circuits Devices Syst., Vol. 49, No. 516, pp363-368, October/December 2002. Alireza Shirvani, David K. Su and Bruce A. Wooley, “A CMOS RF power amplifier with parallel amplification for efficient power control”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 6, pp.684692, Jun. 2002. Pradeep B. Khannur, “A CMOS power amplifier with power control and T/R switch for 2.45-GHz Bluetooth/ISM band applications”, Radio Frequency Integrated Circuits Symposium, 2003 IEEE, pp.145148, Jun. 2003. M. M. Tabrizi and N. Masoumi, “A new topology for power control of high efficiency class-E switched mode power amplifier”, IEEENEWCAS Conference, 2005, the 3rd International, pp.139-142, Jun. 2005. N. O. Sokal and A. D. Sokal, Class E, “A new class of high efficiency tuned single-ended switching power amplifier”, IEEE Journal of Solid State Circuits, vol. 10, June, 1975. Herbert L. Krauss, Charles W. Bostan and Frederick H. Raab, “Solid state radio engineering”, New York: Wiley, 1980.
